From 8d898b16c7d97b924294d6fb010c82b70828a4ad Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 6 Jul 2023 19:48:25 -0700 Subject: [PATCH] fixed sticky bit logic bug --- src/fpu/divremsqrt/divremsqrtround.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/divremsqrt/divremsqrtround.sv b/src/fpu/divremsqrt/divremsqrtround.sv index c199f25b6..2911bd920 100644 --- a/src/fpu/divremsqrt/divremsqrtround.sv +++ b/src/fpu/divremsqrt/divremsqrtround.sv @@ -167,7 +167,7 @@ module divremsqrtround import cvw::*; #(parameter cvw_t P) ( // only add the Addend sticky if doing an FMA opperation // - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits) - assign Sticky = DivSticky&DivOp; + assign Sticky = DivSticky&DivOp | NormSticky;