From 8d40a0a09242e5f9a9a2c55bb2ea04c04e72df5a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 22 Aug 2024 13:56:50 -0700 Subject: [PATCH] Changed names of fpga IP modules to match textbook. Updated boot.h to use the correct clock speed for #DEFINE for UART in the zero stage bootloader. --- fpga/generator/Makefile | 18 ++++------- fpga/generator/wally.tcl | 5 +-- fpga/generator/xlnx_ahblite_axi_bridge.tcl | 28 ---------------- fpga/generator/xlnx_axi_clock_converter.tcl | 28 ---------------- fpga/generator/xlnx_axi_crossbar.tcl | 32 ------------------- .../generator/xlnx_axi_dwidth_conv_32to64.tcl | 25 --------------- .../generator/xlnx_axi_dwidth_conv_64to32.tcl | 27 ---------------- fpga/generator/xlnx_axi_dwidth_converter.tcl | 25 --------------- fpga/generator/xlnx_axi_prtcl_conv.tcl | 23 ------------- fpga/generator/xlnx_mmcm.tcl | 27 ---------------- fpga/generator/xlnx_proc_sys_reset.tcl | 26 --------------- fpga/src/fpgaTopArtyA7.sv | 8 ++--- fpga/zsbl/boot.c | 2 +- 13 files changed, 15 insertions(+), 259 deletions(-) delete mode 100644 fpga/generator/xlnx_ahblite_axi_bridge.tcl delete mode 100644 fpga/generator/xlnx_axi_clock_converter.tcl delete mode 100644 fpga/generator/xlnx_axi_crossbar.tcl delete mode 100644 fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl delete mode 100644 fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl delete mode 100644 fpga/generator/xlnx_axi_dwidth_converter.tcl delete mode 100644 fpga/generator/xlnx_axi_prtcl_conv.tcl delete mode 100644 fpga/generator/xlnx_mmcm.tcl delete mode 100644 fpga/generator/xlnx_proc_sys_reset.tcl diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 3f33d55dd..9c97843d6 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU # Generate IP Blocks .PHONY: IP_Arty IP_VCU -IP_VCU: $(dst)/xlnx_proc_sys_reset.log \ +IP_VCU: $(dst)/sysrst.log \ MEM_VCU \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log \ - $(dst)/xlnx_axi_crossbar.log \ - $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log \ - $(dst)/xlnx_axi_prtcl_conv.log -IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log +IP_Arty: $(dst)/sysrst.log \ MEM_Arty \ - $(dst)/xlnx_mmcm.log \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log + $(dst)/mmcm.log \ + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log #$(dst)/xlnx_axi_crossbar.log \ #$(dst)/xlnx_axi_dwidth_conv_32to64.log \ #$(dst)/xlnx_axi_dwidth_conv_64to32.log \ diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index a5e60a3d5..c0ac9f4a4 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -89,10 +89,11 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - source ../constraints/small-debug.xdc + #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc } else { - source ../constraints/vcu-small-debug.xdc + #source ../constraints/vcu-small-debug.xdc + source ../constraints/small-debug.xdc } diff --git a/fpga/generator/xlnx_ahblite_axi_bridge.tcl b/fpga/generator/xlnx_ahblite_axi_bridge.tcl deleted file mode 100644 index 946e23174..000000000 --- a/fpga/generator/xlnx_ahblite_axi_bridge.tcl +++ /dev/null @@ -1,28 +0,0 @@ - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_ahblite_axi_bridge - -create_project $ipName . -force -part $partNumber -if {$boardName!="ArtyA7"} { - set_property board_part $boardName [current_project] -} - -# really just these two lines which change -create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName -set_property -dict [list CONFIG.C_M_AXI_DATA_WIDTH {64} CONFIG.C_S_AHB_DATA_WIDTH {64} CONFIG.C_M_AXI_THREAD_ID_WIDTH {4}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl deleted file mode 100644 index 87a199cb7..000000000 --- a/fpga/generator/xlnx_axi_clock_converter.tcl +++ /dev/null @@ -1,28 +0,0 @@ - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -set ipName xlnx_axi_clock_converter - -create_project $ipName . -force -part $partNumber -if {$boardName!="ArtyA7"} { - set_property board_part $boardName [current_project] -} - -create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName - -set_property -dict [list CONFIG.ACLK_ASYNC {1} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.ADDR_WIDTH {32} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {4} \ - CONFIG.MI_CLK.FREQ_HZ {208333333} \ - CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl deleted file mode 100644 index 1d9eb4e78..000000000 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ /dev/null @@ -1,32 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_crossbar - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.NUM_SI {2} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ - CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ - CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl deleted file mode 100644 index 97edd97d9..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_32to64 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl deleted file mode 100644 index 3883a8a9d..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl +++ /dev/null @@ -1,27 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_64to32 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_converter.tcl b/fpga/generator/xlnx_axi_dwidth_converter.tcl deleted file mode 100644 index ba979bf01..000000000 --- a/fpga/generator/xlnx_axi_dwidth_converter.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_converter - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_prtcl_conv.tcl b/fpga/generator/xlnx_axi_prtcl_conv.tcl deleted file mode 100644 index 76b6fc6cd..000000000 --- a/fpga/generator/xlnx_axi_prtcl_conv.tcl +++ /dev/null @@ -1,23 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_prtcl_conv - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl deleted file mode 100644 index 146a9cf41..000000000 --- a/fpga/generator/xlnx_mmcm.tcl +++ /dev/null @@ -1,27 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -set ipName xlnx_mmcm - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName - -set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ - CONFIG.NUM_OUT_CLKS {3} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ - CONFIG.CLKIN1_JITTER_PS {10.0} \ - ] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_proc_sys_reset.tcl b/fpga/generator/xlnx_proc_sys_reset.tcl deleted file mode 100644 index 06ca4fb1f..000000000 --- a/fpga/generator/xlnx_proc_sys_reset.tcl +++ /dev/null @@ -1,26 +0,0 @@ - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -set ipName xlnx_proc_sys_reset - -create_project $ipName . -force -part $partNumber -if {$boardName!="ArtyA7"} { - set_property board_part $boardName [current_project] -} - -# really just these two lines which change -create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName -set_property -dict [list CONFIG.C_AUX_RESET_HIGH {1} \ - CONFIG.C_AUX_RST_WIDTH {1} \ - CONFIG.C_EXT_RESET_HIGH {1} \ - CONFIG.C_EXT_RST_WIDTH {1} \ - CONFIG.C_NUM_BUS_RST {1}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 9133baa25..0da6adddf 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // 2. a second clock which is 200 MHz // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz. // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot. - xlnx_mmcm xln_mmcm(.clk_out1(clk167), + mmcm mmcm(.clk_out1(clk167), .clk_out2(clk200), .clk_out3(CPUCLK), .clk_out4(phy_ref_clk), @@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(1'b0), .aux_reset_in(south_reset), @@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), .s_ahb_hsel(HSELEXT), @@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(m_axi_rready)); // AXI Clock Converter - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), .s_axi_awid(m_axi_awid), diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e98eda2c1..b21c49f48 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -153,7 +153,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { int ret = 0; // Initialize UART for messages - init_uart(20000000, 115200); + init_uart(SYSTEMCLOCK, 115200); // Print the wally banner print_uart(BANNER);