From 6772bf9131f58ec0c482bea790c7e6a3241bd29b Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Mon, 1 Apr 2024 00:02:57 -0700 Subject: [PATCH 1/2] Bump the riscv-arch-test to the latest version with 0 fail. --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a52b016d..8a0cdceca 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d +Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b From c11d7ea55e93978fff6de97293e3b6e336f85925 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 1 Apr 2024 10:59:40 -0500 Subject: [PATCH 2/2] Fixed bug in the testbench which did not allow external memory to work correctly. --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee725c245..eef7e3f3b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -469,7 +469,7 @@ module testbench; assign SPIIn = 0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin