diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 8a52b016d..8a0cdceca 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
+Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 60f14e48a..a98e8c5b5 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -479,7 +479,7 @@ module testbench;
   assign SPIIn = 0;
 
   if(P.EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
+    ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
       .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
   end else begin