diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do
index 6e6863d5f..4a23facf6 100644
--- a/pipelined/src/fma/fma.do
+++ b/pipelined/src/fma/fma.do
@@ -8,7 +8,7 @@ onbreak {resume}
 # create library
 vlib worklib
 
-vlog -lint -work worklib fma16.v testbench.v
+vlog -lint -sv -work worklib fma16.v testbench.v
 vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
 vsim -lib worklib testbenchopt
 
diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv
index 4db7e8a0e..082664dd3 100644
--- a/pipelined/src/uncore/plic.sv
+++ b/pipelined/src/uncore/plic.sv
@@ -176,11 +176,7 @@ module plic (
   end
 
   // pending interrupt requests
-  assign nextIntPending = 
-    (intPending |                                                   // existing pending requests
-    (requests & ~intInProgress)) &                                  // assert new requests (if they aren't already being serviced)
-    ~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed
-    ~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1));
+  assign nextIntPending = (intPending | requests) & ~intInProgress;
   flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
 
   // context-dependent signals