From 2ed1c9f14ff4b7693c5ce308f9775d64737276b7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 31 Mar 2022 17:00:38 +0000 Subject: [PATCH 1/2] Added SystemVerilog flag to fma.do so that fma16 compiles properly --- pipelined/src/fma/fma.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do index 6e6863d5f..4a23facf6 100644 --- a/pipelined/src/fma/fma.do +++ b/pipelined/src/fma/fma.do @@ -8,7 +8,7 @@ onbreak {resume} # create library vlib worklib -vlog -lint -work worklib fma16.v testbench.v +vlog -lint -sv -work worklib fma16.v testbench.v vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vsim -lib worklib testbenchopt From 34c94f150e692661cadd3bbdd9e98dbeb6427ecc Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 31 Mar 2022 13:46:24 -0700 Subject: [PATCH 2/2] simplify plic logic --- pipelined/src/uncore/plic.sv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index 4db7e8a0e..082664dd3 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -176,11 +176,7 @@ module plic ( end // pending interrupt requests - assign nextIntPending = - (intPending | // existing pending requests - (requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced) - ~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed - ~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1)); + assign nextIntPending = (intPending | requests) & ~intInProgress; flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); // context-dependent signals