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Merge pull request #553 from ross144/main

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Fixed testbench for coremark. Possibly broke verilator.
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David Harris 2024-01-06 08:17:52 -08:00 committed by GitHub
commit 7196f8ff79
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2 changed files with 11 additions and 1 deletions
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benchmarks/coremark/riscv64-baremetal/crt.S
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@ -134,6 +134,8 @@ _start:
add sp, sp, tp add sp, sp, tp
j _init j _init
sig_end_canary:
nop
.align 2 .align 2
trap_entry: trap_entry:

8
testbench/testbench.sv
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@ -388,6 +388,14 @@ module testbench;
end end
end end
// *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator
integer adrindex;
if (P.UNCORE_RAM_SUPPORTED)
always @(posedge clk)
if (ResetMem) // program memory is sometimes reset
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Actual hardware // Actual hardware
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////