From c1e12e3145550e9a55a3326ef6990d1eb62ed918 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Jan 2024 00:23:03 -0600 Subject: [PATCH 1/2] added sig_end_canary to coremark. --- benchmarks/coremark/riscv64-baremetal/crt.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/benchmarks/coremark/riscv64-baremetal/crt.S b/benchmarks/coremark/riscv64-baremetal/crt.S index d75e81e06..bf974c847 100644 --- a/benchmarks/coremark/riscv64-baremetal/crt.S +++ b/benchmarks/coremark/riscv64-baremetal/crt.S @@ -134,6 +134,8 @@ _start: add sp, sp, tp j _init +sig_end_canary: + nop .align 2 trap_entry: From ab07d64195898be7e4b1436ec9c6368ea707c004 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 6 Jan 2024 00:41:57 -0600 Subject: [PATCH 2/2] Fixes coremark. Maybe works with verilator. --- testbench/testbench.sv | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 7b5877e9c..2d947a591 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -387,7 +387,15 @@ module testbench; end end end - + + // *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator + integer adrindex; + if (P.UNCORE_RAM_SUPPORTED) + always @(posedge clk) + if (ResetMem) // program memory is sometimes reset + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + //////////////////////////////////////////////////////////////////////////////// // Actual hardware ////////////////////////////////////////////////////////////////////////////////