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All regression tests which matter are running!

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This commit is contained in:
Rose Thompson 2023-12-20 14:57:52 -06:00
parent 1b59182d59
commit 70d0169019
2 changed files with 3 additions and 4 deletions
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4
testbench/testbench.sv
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@ -360,8 +360,6 @@ module testbench;
StartIndex = begin_signature_addr >> LogXLEN; StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8; EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
$display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x",
begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN);
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
end end
@ -379,8 +377,6 @@ module testbench;
StartIndex = begin_signature_addr >> LogXLEN; StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8; EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
$display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x",
begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN);
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex]; testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
end end

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
View File

@ -917,4 +917,7 @@ RVMODEL_DATA_BEGIN
# signature output # signature output
wally_signature: wally_signature:
.fill 0x200, 8, 0x00000000 .fill 0x200, 8, 0x00000000
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END RVMODEL_DATA_END