diff --git a/.gitignore b/.gitignore
index 630731b23..41ccba5f9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -59,6 +59,9 @@ examples/C/sum/sum
 examples/C/fir/fir
 examples/fp/softfloat_demo/softfloat_demo
 examples/fp/fpcalc/fpcalc
+examples/C/inline/inline
+examples/C/sum_mixed/sum_mixed
+examples/asm/trap/trap
 src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
@@ -114,4 +117,57 @@ sim/vsim.log
 tests/coverage/*.elf
 *.elf.memfile
 sim/*Cache.log
-sim/branch
\ No newline at end of file
+sim/branch
+tests/fp/combined_IF_vectors/IF_vectors/*.tv
+/sim/branch-march14.tar.gz
+/sim/gshareforward-no-class
+/sim/lint-wally_32
+/sim/lint-wally_32e
+/sim/local16.txt
+/sim/localhistory_m6k10_results_april24.txt
+/sim/log.log
+/sim/obj_dir/Vtestbench.cpp
+/sim/obj_dir/Vtestbench.h
+/sim/obj_dir/Vtestbench.mk
+/sim/obj_dir/Vtestbench__ConstPool_0.cpp
+/sim/obj_dir/Vtestbench__Syms.cpp
+/sim/obj_dir/Vtestbench__Syms.h
+/sim/obj_dir/Vtestbench___024root.h
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__Slow.cpp
+/sim/obj_dir/Vtestbench___024unit.h
+/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024unit__Slow.cpp
+/sim/obj_dir/Vtestbench__verFiles.dat
+/sim/obj_dir/Vtestbench_classes.mk
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
diff --git a/.gitmodules b/.gitmodules
index 78243a1de..6c46deabf 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -24,3 +24,6 @@
 [submodule "addins/branch-predictor-simulator"]
 	path = addins/branch-predictor-simulator
 	url = https://github.com/synxlin/branch-predictor-simulator.git
+[submodule "addins/FreeRTOS-Kernel"]
+	path = addins/FreeRTOS-Kernel
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
diff --git a/Makefile b/Makefile
index 518bcd2dd..8336fe017 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,11 @@
 
 all:
 	make install
-	make regression
+	make testfloat	
+	make riscof
+	make verify
+	make coverage
+	make benchmarks
 
 # install copies over the Makefile.include from riscv-isa-sim
 # And corrects the TARGETDIR path and the RISCV_PREFIX
@@ -18,9 +22,37 @@ install:
 	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
-regression:
+riscof:
 	make -C sim
 
+testfloat:
+	cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
+	cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
+	cd ${WALLY}/tests/fp; ./create_all_vectors.sh
+
+verify:
+	cd ${WALLY}/sim; ./regression-wally
+	cd ${WALLY}/sim; ./sim-testfloat-batch all
+	make imperasdv
+
+imperasdv:
+	iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
+	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
+
+coverage:
+	cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
+
+benchmarks:
+	make coremark
+	make embench
+
+coremark:
+	cd ${WALLY}/benchmarks/coremark; make; make run
+
+embench:
+	cd ${WALLY}/benchmarks/embench; make; make run
+
+
 clean:
 	make clean -C sim
 
diff --git a/README.md b/README.md
index b73aecdb8..0dc68f1c1 100644
--- a/README.md
+++ b/README.md
@@ -33,7 +33,7 @@ Then clone the repo, source setup,  make the tests and run regression
 	
 	On the Linux computer where you will be working, log in
 
-Clone your fork of the repo and run the setup script.  
+Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id. 
 
 	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel
new file mode 160000
index 000000000..17a46c252
--- /dev/null
+++ b/addins/FreeRTOS-Kernel
@@ -0,0 +1 @@
+Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index a3b7f0c2c..873d16e74 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit a3b7f0c2cf89652b8a0cba3146890c512ff8ba44
+Subproject commit 873d16e748ad60023dcdda3926144957c096e31d
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index b412c36ef..81c2b0959 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -3,15 +3,19 @@
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 PORT_DIR = $(CURDIR)/riscv64-baremetal
-cmbase=../../addins/coremark
-work_dir= ../../benchmarks/coremark/work
+cmbase= $(WALLY)/addins/coremark
+work_dir= $(WALLY)/benchmarks/coremark/work
 XLEN ?=64
 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
 	$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
-ARCH := rv$(XLEN)im
+#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
+#ARCH := rv$(XLEN)gc
+ARCH := rv$(XLEN)imc_zicsr
+#ARCH := rv$(XLEN)im_zicsr
+#ARCH := rv$(XLEN)i_zicsr
 PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 	-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
 	-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
@@ -23,9 +27,6 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
 	(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
-	cd ../benchmarks/coremark/
-#	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
-	python3 coremark-postprocess.py
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
@@ -33,13 +34,14 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	extractFunctionRadix.sh $<.elf.objdump
 
 $(work_dir)/coremark.bare.riscv: $(sources) Makefile
-	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)"
+	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)"
 	mkdir -p $(work_dir)
 	mv $(cmbase)/coremark.bare.riscv $(work_dir)
 
 .PHONY: clean
 
 clean:
+	make -C $(cmbase) clean
 	rm -f $(work_dir)/*
 
 
diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py
deleted file mode 100644
index f77f2ef8b..000000000
--- a/benchmarks/coremark/coremark-postprocess.py
+++ /dev/null
@@ -1,58 +0,0 @@
-#!/usr/bin/env python
-#########################################################
-#
-# coremark postprocessing script
-#
-# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
-#
-# Created 2022-09-25
-#
-# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##################################################
-
-logFile = "../../benchmarks/coremark/work/coremark.sim.log"
-
-with open(logFile, "r") as logRead:
-    logLines = logRead.readlines()
-
-for lineNum in range(len(logLines)):
-    contents = logLines[lineNum].lower().split()
-    if "branches" in contents and "miss" in contents:
-        branchMisses = int(contents[-1])
-    elif "branches" in contents:
-        branchesTot = int(contents[-1])
-        branchLineNum = lineNum + 2
-    
-    if "d-cache" in contents and "misses" in contents:
-        dCacheMisses = int(contents[-1])
-    elif "d-cache" in contents:
-        dCacheAccess = int(contents[-1])
-        dCacheLineNum = lineNum + 2
-
-    if "i-cache" in contents and "misses" in contents:
-        ICacheMisses = int(contents[-1])
-    elif "i-cache" in contents:
-        ICacheAccess = int(contents[-1])
-        ICacheLineNum = lineNum + 2
-
-# need to add the number of previously added lines to the line number so that they stay in the intedned order.
-logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
-logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")
-logLines.insert(dCacheLineNum+2, "# D-cache Hit Rate " + str((dCacheAccess - dCacheMisses) / dCacheAccess) + "\n")
-
-logLines.insert(ICacheLineNum+3, "# I-cache Hits " + str(ICacheAccess - ICacheMisses) + "\n")
-logLines.insert(ICacheLineNum+4, "# I-cache Miss Rate " + str(ICacheMisses / ICacheAccess) + "\n")
-logLines.insert(ICacheLineNum+5, "# I-cache Hit Rate " + str((ICacheAccess - ICacheMisses) / ICacheAccess) + "\n")
-
-logLines.insert(branchLineNum+6, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
-
-
-with open(logFile, "w") as logWrite:
-    logWrite.writelines(logLines)
-
-
-
-
-
diff --git a/benchmarks/coremark/riscv64-baremetal/syscalls.c b/benchmarks/coremark/riscv64-baremetal/syscalls.c
index 34615b6e4..29cd5f24a 100644
--- a/benchmarks/coremark/riscv64-baremetal/syscalls.c
+++ b/benchmarks/coremark/riscv64-baremetal/syscalls.c
@@ -84,6 +84,11 @@ void setStats(int enable)
   READ_CTR(mhpmcounter10);
   READ_CTR(mhpmcounter11);
   READ_CTR(mhpmcounter12);  
+  READ_CTR(mhpmcounter13);  
+  READ_CTR(mhpmcounter14);  
+  READ_CTR(mhpmcounter15);  
+  READ_CTR(mhpmcounter16);  
+  READ_CTR(mhpmcounter17);  
 
 #undef READ_CTR
 }
@@ -167,18 +172,21 @@ void _init(int cid, int nc)
   counters[12] = read_csr(mhpmcounter12) - counters[12];
   counters[13] = read_csr(mhpmcounter13) - counters[13];
   counters[14] = read_csr(mhpmcounter14) - counters[14];
+  counters[15] = read_csr(mhpmcounter15) - counters[15];
+  counters[16] = read_csr(mhpmcounter16) - counters[16];
+  counters[17] = read_csr(mhpmcounter17) - counters[17];
 
-  ee_printf("Load Stalls %d\n", counters[3]);
-  ee_printf("D-Cache Accesses %d\n", counters[11]);
-  ee_printf("D-Cache Misses %d\n", counters[12]); 
-  ee_printf("I-Cache Accesses %d\n", counters[13]);
-  ee_printf("I-Cache Misses %d\n", counters[14]);
-  ee_printf("Branches %d\n", counters[5]);
-  ee_printf("Branches Miss Predictions %d\n", counters[4]);
-  ee_printf("BTB Misses %d\n", counters[6]);
-  ee_printf("Jump, JAL, JALR %d\n", counters[7]);
-  ee_printf("RAS Wrong %d\n", counters[8]);
-  ee_printf("Returns %d\n", counters[9]);
+  ee_printf("Load Stalls %d\n", counters[11]);
+  ee_printf("D-Cache Accesses %d\n", counters[13]);
+  ee_printf("D-Cache Misses %d\n", counters[14]); 
+  ee_printf("I-Cache Accesses %d\n", counters[16]);
+  ee_printf("I-Cache Misses %d\n", counters[17]);
+  ee_printf("Branches %d\n", counters[3]);
+  ee_printf("Branches Miss Predictions %d\n", counters[7]);
+  ee_printf("BTB Misses %d\n", counters[8]);
+  ee_printf("Jump and JR %d\n", counters[4]);
+  ee_printf("RAS Wrong %d\n", counters[9]);
+  ee_printf("Returns %d\n", counters[5]);
   ee_printf("BP Class Wrong %d\n", counters[10]);
   ee_printf("Done printing performance counters\n");
 
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 538fb64f9..3dba4daaa 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_speed:
 	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
+	# remove files not used in embench1.0  When changing to 2.0, restore these files		
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount	
 	find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 build_sizeopt_speed:
 	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" 
+	# remove files not used in embench1.0  When changing to 2.0, restore these files		
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount	
 	find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 5b5e0d98b..9e08f2c7a 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -279,12 +279,13 @@ if(sys.argv[1] == '-b'):
                     dct[PredType] = (currSize, currPercent)
         print(dct)
         fig, axes = plt.subplots()
-        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*'}
-        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue'}
+        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
+        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
         for cat in dct:
             (x, y) = dct[cat]
             x=[int(2**int(v)) for v in x]
-            print(x, y)
+            #print(x, y)
+            print(cat)
             axes.plot(x,y, color=colors[cat])
             axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
             #plt.scatter(x, y, label=cat)
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index ef98aed76..cc6254079 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -29,7 +29,7 @@
 
 # Use /opt/riscv for installation - may require running script with sudo
 export RISCV="${1:-/opt/riscv}"
-export PATH=$PATH:$RISCV/bin
+export PATH=$PATH:$RISCV/bin:/usr/bin
 
 set -e # break on error
 
@@ -40,25 +40,25 @@ NUM_THREADS=8  # for >= 32GiB
 #NUM_THREADS=16  # for >= 64GiB
 
 sudo mkdir -p $RISCV
+# *** need to update permissions to local user
 
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
-apt update -y
-apt upgrade -y
-apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
-
+sudo apt update -y
+sudo apt upgrade -y
+sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc 
 # Other python libraries used through the book.
-pip3 install matplotlib scipy scikit-learn adjustText lief
+sudo pip3 install matplotlib scipy scikit-learn adjustText lief
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
 then
     echo "WARNING: python3 was installed as python3 rather than python. Creating symlink."
-    ln -sf /usr/bin/python3 /usr/bin/python
+    sudo ln -sf /usr/bin/python3 /usr/bin/python
 fi
 
 # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
 # To install GCC from source can take hours to compile. 
-#This configuration enables multilib to target many flavors of RISC-V.   
+# This configuration enables multilib to target many flavors of RISC-V.   
 # This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
 # Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
 # objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
@@ -68,10 +68,11 @@ fi
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
-git checkout 2023.01.31 
-./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
+git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
+./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
+#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 make -j ${NUM_THREADS}
-make install
 
 # elf2hex (https://github.com/sifive/elf2hex)
 #The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. 
@@ -112,6 +113,23 @@ cd ../arch_test_target/spike/device
 sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
 sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 
+# Wally needs Verilator 5.0 or later.
+# Verilator needs to be built from scratch to get the latest version
+# apt-get install verilator installs version 4.028 as of 6/8/23
+sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g 
+sudo apt-get install -y libfl2  libfl-dev  # Ubuntu only (ignore if gives error)
+cd $RISCV
+git clone https://github.com/verilator/verilator   # Only first time
+unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
+unset VERILATOR_ROOT  # For bash
+cd verilator
+git pull         # Make sure git repository is up-to-date
+git checkout master      # Use development branch (e.g. recent bug fixes)
+autoconf         # Create ./configure script
+./configure      # Configure and create Makefile
+make -j NUM_THREADS  # Build Verilator itself (if error, try just 'make')
+sudo make install
+
 # Sail (https://github.com/riscv/sail-riscv)
 # Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which 
 # is an object-oriented extension of ML, which in turn is a functional programming 
@@ -131,22 +149,19 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 #pip3 install chardet==3.0.4
 #pip3 install urllib3==1.22
 
+cd $RISCV
 opam init -y --disable-sandboxing
-opam switch create ocaml-base-compiler.4.06.1
+opam switch create ocaml-base-compiler.4.08.0
 opam install sail -y 
 
 eval $(opam config env)
 git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
-# Current bug in Sail - use hash that works for Wally
-#   (may remove later if Sail is ever fixed)
-git checkout 4d05aa1698a0003a4f6f99e1380c743711c32052
 make -j ${NUM_THREADS}
 ARCH=RV32 make -j ${NUM_THREADS}
-ARCH=RV64 make -j ${NUM_THREADS}
-ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
-ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
+sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
+sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
-pip3 install testresources
-pip3 install riscof --ignore-installed PyYAML
+sudo pip3 install testresources
+pip3 install git+https://github.com/riscv/riscof.git
 
diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh
new file mode 100644
index 000000000..371c825e2
--- /dev/null
+++ b/config/buildroot/config.vh
@@ -0,0 +1,163 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 1;
+localparam QEMU = 0;
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+localparam MISA = (32'h0014112D);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h00001FFF;
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h00001FFF;
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000 ;
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h07FFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Bus Interface width
+localparam AHBW = 32'd64;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 0;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd0;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd53;
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_UART_ID = 32'd10;
+localparam PLIC_GPIO_ID = 32'd3;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+
+localparam SVADU_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index 236574288..0957dd003 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -132,6 +132,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 
diff --git a/config/fpga/config.vh b/config/fpga/config.vh
new file mode 100644
index 000000000..dbd7d9687
--- /dev/null
+++ b/config/fpga/config.vh
@@ -0,0 +1,175 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// include shared configuration
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 1;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// MISA RISC-V configuration per specification
+localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
+
+// Bus Interface width
+localparam AHBW = 32'd64;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physical Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h00001FFF;
+
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h00001FFF;
+
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+
+localparam UNCORE_RAM_SUPPORTED = 1'b0;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+
+localparam EXT_MEM_SUPPORTED = 1'b1;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+
+localparam SDC_SUPPORTED = 1'b1;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 0;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd0;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd53;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BPRED_SIZE = 32'd12;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index 1f7447f4d..9230c148e 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -141,6 +141,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 12
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
new file mode 100644
index 000000000..30b7c3050
--- /dev/null
+++ b/config/rv32e/config.vh
@@ -0,0 +1,164 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd32;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// E
+localparam MISA = (32'h00000010); 
+localparam ZICSR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0;
+localparam COUNTERS = 12'd0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 0;
+localparam ICACHE_SUPPORTED = 0;
+localparam VIRTMEM_SUPPORTED = 0;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 0; 
+localparam BIGENDIAN_SUPPORTED = 0;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd0;
+localparam DTLB_ENTRIES = 32'd0;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd1;
+localparam IDIV_ON_FPU = 0;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd0;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h80000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE = 64'h80000000;      
+localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;     
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE = 64'h80000000;     
+localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;     
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE = 64'h00001000;  
+localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; 
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;      
+localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;     
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;      
+localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;     
+localparam CLINT_SUPPORTED = 1'b0;
+localparam logic [63:0] CLINT_BASE = 64'h02000000; 
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b0;
+localparam logic [63:0] GPIO_BASE = 64'h10060000;  
+localparam logic [63:0] GPIO_RANGE = 64'h000000FF; 
+localparam UART_SUPPORTED = 1'b0;
+localparam logic [63:0] UART_BASE = 64'h10000000;  
+localparam logic [63:0] UART_RANGE = 64'h00000007; 
+localparam PLIC_SUPPORTED = 1'b0;
+localparam logic [63:0] PLIC_BASE = 64'h0C000000;  
+localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; 
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE = 64'h00012100;  
+localparam logic [63:0] SDC_RANGE = 64'h0000001F; 
+
+// Bus Interface width
+localparam AHBW = 32'd32;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10; 
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 0;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
+ 
diff --git a/config/rv32e/rv32e-config.vh b/config/rv32e/rv32e-config.vh
new file mode 100644
index 000000000..4701b69f1
--- /dev/null
+++ b/config/rv32e/rv32e-config.vh
@@ -0,0 +1,178 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+localparam PA_BITS = 34;
+//localparam AHBW = 32;
+//localparam XLEN = 32;
+//localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
+////localparam    BUS_SUPPORTED = 1'b1;
+//localparam    ZICSR_SUPPORTED = 1'b0;
+localparam    M_SUPPORTED = 1'b0;
+localparam    F_SUPPORTED = 1'b0;
+//localparam    ZMMUL_SUPPORTED = 1'b0;
+//localparam    F_SUPPORTED = 1'b0;
+//localparam    PMP_ENTRIES = 0;
+localparam    LLEN =     32;
+//localparam    FPGA =     1'b0;
+//localparam    QEMU =     1'b0;
+ //   //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9),
+   // `include "test-shared.vh"
+localparam    FLEN =     32;
+
+`include "test-shared.vh"
+ 
+
+ 
+// include shared configuration
+//`include "wally-shared.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// E
+localparam MISA = (32'h00000010); 
+localparam ZICSR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0;
+localparam COUNTERS = 0;
+localparam ZICOUNTERS_SUPPORTED = 0;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 0;
+localparam ICACHE_SUPPORTED = 0;
+localparam VIRTMEM_SUPPORTED = 0;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 0; 
+localparam BIGENDIAN_SUPPORTED = 0;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 0;
+localparam DTLB_ENTRIES = 0;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 4;
+localparam DCACHE_WAYSIZEINBYTES = 4096;
+localparam DCACHE_LINELENINBITS = 512;
+localparam ICACHE_NUMWAYS = 4;
+localparam ICACHE_WAYSIZEINBYTES = 4096;
+localparam ICACHE_LINELENINBITS = 512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 1;
+localparam IDIV_ON_FPU = 0;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 0;
+
+// Address space
+localparam RESET_VECTOR = 32'h80000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b0;
+localparam DTIM_BASE = 34'h80000000;      
+localparam DTIM_RANGE = 34'h007FFFFF;     
+localparam IROM_SUPPORTED = 1'b0;
+localparam IROM_BASE = 34'h80000000;     
+localparam IROM_RANGE = 34'h007FFFFF;     
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam BOOTROM_BASE = 34'h00001000;  
+localparam BOOTROM_RANGE = 34'h00000FFF; 
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam UNCORE_RAM_BASE = 34'h80000000;      
+localparam UNCORE_RAM_RANGE = 34'h07FFFFFF;     
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam EXT_MEM_BASE = 34'h80000000;      
+localparam EXT_MEM_RANGE = 34'h07FFFFFF;     
+localparam CLINT_SUPPORTED = 1'b0;
+localparam CLINT_BASE = 34'h02000000; 
+localparam CLINT_RANGE = 34'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b0;
+localparam GPIO_BASE = 34'h10060000;  
+localparam GPIO_RANGE = 34'h000000FF; 
+localparam UART_SUPPORTED = 1'b0;
+localparam UART_BASE = 34'h10000000;  
+localparam UART_RANGE = 34'h00000007; 
+localparam PLIC_SUPPORTED = 1'b0;
+localparam PLIC_BASE = 34'h0C000000;  
+localparam PLIC_RANGE = 34'h03FFFFFF; 
+localparam SDC_SUPPORTED = 1'b0;
+localparam SDC_BASE = 34'h00012100;  
+localparam SDC_RANGE = 34'h0000001F; 
+
+// Bus Interface width
+localparam AHBW = 32;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 10; 
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 3;
+localparam PLIC_UART_ID = 10;
+
+localparam BPRED_SUPPORTED = 0;
+localparam BPRED_TYPE = "BP_GSHARE"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 10;
+localparam BTB_SIZE = 10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 4;
+localparam DIVCOPIES = 4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+ 
\ No newline at end of file
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
deleted file mode 100644
index aee0e5410..000000000
--- a/config/rv32e/wally-config.vh
+++ /dev/null
@@ -1,155 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// E
-`define MISA (32'h00000010) 
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 0
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 0 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 1
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10 
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
new file mode 100644
index 000000000..a966b0401
--- /dev/null
+++ b/config/rv32gc/config.vh
@@ -0,0 +1,164 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// include shared configuration
+// `include "wally-shared.vh"
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd32;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 1;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h80000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE       = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE       = 64'h80000000;
+localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE  = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE   = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE   = 64'h10000000;
+localparam logic [63:0] UART_RANGE  = 64'h00000007;
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE   = 64'h00012100;
+localparam logic [63:0] SDC_RANGE  = 64'h0000001F;
+
+// Bus Interface width
+localparam AHBW = 32'd32;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd16;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
deleted file mode 100644
index 37eff79ea..000000000
--- a/config/rv32gc/wally-config.vh
+++ /dev/null
@@ -1,154 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 1
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 16
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 1
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 1
-`define ZBB_SUPPORTED 1
-`define ZBC_SUPPORTED 1
-`define ZBS_SUPPORTED 1
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
new file mode 100644
index 000000000..eda81e298
--- /dev/null
+++ b/config/rv32i/config.vh
@@ -0,0 +1,163 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd32;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// I
+localparam MISA = (32'h00000104);
+localparam ZICSR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0;
+localparam COUNTERS = 0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 0;
+localparam DCACHE_SUPPORTED = 0;
+localparam ICACHE_SUPPORTED = 0;
+localparam VIRTMEM_SUPPORTED = 0;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 0;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 0;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd0;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h80000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b1;
+localparam logic [63:0] DTIM_BASE       = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b1;
+localparam logic [63:0] IROM_BASE       = 64'h80000000;
+localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b0;
+localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b0;
+localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b0;
+localparam logic [63:0] CLINT_BASE  = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b0;
+localparam logic [63:0] GPIO_BASE   = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
+localparam UART_SUPPORTED = 1'b0;
+localparam logic [63:0] UART_BASE   = 64'h10000000;
+localparam logic [63:0] UART_RANGE  = 64'h00000007;
+localparam PLIC_SUPPORTED = 1'b0;
+localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE   = 64'h00012100;
+localparam logic [63:0] SDC_RANGE  = 64'h0000001F;
+
+// Bus Interface width
+localparam AHBW = 32'd32;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 0;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
deleted file mode 100644
index d75d0c462..000000000
--- a/config/rv32i/wally-config.vh
+++ /dev/null
@@ -1,155 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// I
-`define MISA (32'h00000104)
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 0
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10 
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
new file mode 100644
index 000000000..0b2aee01e
--- /dev/null
+++ b/config/rv32imc/config.vh
@@ -0,0 +1,162 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd32;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 0;
+localparam ICACHE_SUPPORTED = 0;
+localparam VIRTMEM_SUPPORTED = 0;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 0;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd0;
+localparam DTLB_ENTRIES = 32'd0;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd2;
+localparam IDIV_ON_FPU = 0;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd0;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h80000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+localparam DTIM_SUPPORTED = 1'b1;
+localparam logic [63:0] DTIM_BASE       = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b1;
+localparam logic [63:0] IROM_BASE       = 64'h80000000;
+localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b0;
+localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b0;
+localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE  = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE   = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE   = 64'h10000000;
+localparam logic [63:0] UART_RANGE  = 64'h00000007;
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE   = 64'h00012100;
+localparam logic [63:0] SDC_RANGE  = 64'h0000001F;
+
+// Bus Interface width
+localparam AHBW = 32'd32;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 0;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
deleted file mode 100644
index 42442d46e..000000000
--- a/config/rv32imc/wally-config.vh
+++ /dev/null
@@ -1,154 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 2
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh
new file mode 100644
index 000000000..a784d369f
--- /dev/null
+++ b/config/rv64fpquad/config.vh
@@ -0,0 +1,165 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// MISA RISC-V configuration per specification
+localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 1;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
+
+// Bus Interface width
+localparam AHBW = 32'd64;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
deleted file mode 100644
index 34d7628e0..000000000
--- a/config/rv64fpquad/wally-config.vh
+++ /dev/null
@@ -1,157 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 1
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW 64
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physiccal Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
new file mode 100644
index 000000000..8d266ab3e
--- /dev/null
+++ b/config/rv64gc/config.vh
@@ -0,0 +1,168 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// include shared configuration
+// `include "wally-shared.vh"
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// MISA RISC-V configuration per specification
+localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 1;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
+
+// Bus Interface width
+localparam AHBW = 32'd64;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physical Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b1;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BPRED_SIZE = 32'd10;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
deleted file mode 100644
index b44351ef2..000000000
--- a/config/rv64gc/wally-config.vh
+++ /dev/null
@@ -1,157 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 1
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW 64
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 1
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 1
-`define ZBB_SUPPORTED 1
-`define ZBC_SUPPORTED 1
-`define ZBS_SUPPORTED 1
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
new file mode 100644
index 000000000..ff6a1c61e
--- /dev/null
+++ b/config/rv64i/config.vh
@@ -0,0 +1,165 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 0;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// MISA RISC-V configuration per specification
+localparam MISA = (32'h00000104);
+localparam ZICSR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0;
+localparam COUNTERS = 0;
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 0;
+localparam DCACHE_SUPPORTED = 0;
+localparam ICACHE_SUPPORTED = 0;
+localparam VIRTMEM_SUPPORTED = 0;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 0;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd0;
+localparam DTLB_ENTRIES = 32'd0;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 0;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd0;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
+
+// Bus Interface width
+localparam AHBW = (XLEN);
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam DTIM_SUPPORTED = 1'b1;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h007FFFFF;
+localparam IROM_SUPPORTED = 1'b1;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h007FFFFF;
+localparam BOOTROM_SUPPORTED = 1'b0;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam UNCORE_RAM_SUPPORTED = 1'b0;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+localparam CLINT_SUPPORTED = 1'b0;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+localparam GPIO_SUPPORTED = 1'b0;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+localparam UART_SUPPORTED = 1'b0;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+localparam PLIC_SUPPORTED = 1'b0;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+localparam SDC_SUPPORTED = 1'b0;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 0;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
deleted file mode 100644
index 34c37f73a..000000000
--- a/config/rv64i/wally-config.vh
+++ /dev/null
@@ -1,157 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104)
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 0
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW (`XLEN)
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physiccal Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/shared/BranchPredictorType.vh b/config/shared/BranchPredictorType.vh
new file mode 100644
index 000000000..e252de249
--- /dev/null
+++ b/config/shared/BranchPredictorType.vh
@@ -0,0 +1,3 @@
+typedef enum logic[3:0] {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC, 
+               BP_GLOBAL_BASIC, BP_LOCAL_BASIC, BP_LOCAL_AHEAD, BP_LOCAL_REPAIR} BranchPredictorType;
+
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
new file mode 100644
index 000000000..f1000d6d9
--- /dev/null
+++ b/config/shared/parameter-defs.vh
@@ -0,0 +1,175 @@
+
+// Populate parameter structure with values specific to the current configuration
+
+parameter cvw_t P = '{ 
+  FPGA :                 FPGA,  
+  QEMU :                 QEMU,  
+  XLEN :                 XLEN,  
+  IEEE754 :              IEEE754, 
+  MISA :                 MISA, 
+  AHBW :                 AHBW, 
+  ZICSR_SUPPORTED :      ZICSR_SUPPORTED,
+  ZIFENCEI_SUPPORTED :   ZIFENCEI_SUPPORTED,
+  COUNTERS :             COUNTERS,
+  ZICNTR_SUPPORTED :     ZICNTR_SUPPORTED,
+  ZIHPM_SUPPORTED :      ZIHPM_SUPPORTED,
+  ZFH_SUPPORTED :        ZFH_SUPPORTED,
+  SSTC_SUPPORTED :       SSTC_SUPPORTED,
+  VIRTMEM_SUPPORTED :    VIRTMEM_SUPPORTED,
+  VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
+  BIGENDIAN_SUPPORTED :  BIGENDIAN_SUPPORTED,
+  SVADU_SUPPORTED :      SVADU_SUPPORTED,
+  ZMMUL_SUPPORTED :      ZMMUL_SUPPORTED,
+  ZICBOM_SUPPORTED :     ZICBOM_SUPPORTED,
+  ZICBOZ_SUPPORTED :     ZICBOZ_SUPPORTED,
+  ZICBOP_SUPPORTED :     ZICBOP_SUPPORTED,
+  SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
+  SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
+  BUS_SUPPORTED :        BUS_SUPPORTED,
+  DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
+  ICACHE_SUPPORTED :     ICACHE_SUPPORTED,
+  ITLB_ENTRIES :         ITLB_ENTRIES,
+  DTLB_ENTRIES :         DTLB_ENTRIES,
+  DCACHE_NUMWAYS :       DCACHE_NUMWAYS,
+  DCACHE_WAYSIZEINBYTES :        DCACHE_WAYSIZEINBYTES,
+  DCACHE_LINELENINBITS :        DCACHE_LINELENINBITS,
+  ICACHE_NUMWAYS :        ICACHE_NUMWAYS,
+  ICACHE_WAYSIZEINBYTES :        ICACHE_WAYSIZEINBYTES,
+  ICACHE_LINELENINBITS :        ICACHE_LINELENINBITS,
+  IDIV_BITSPERCYCLE :        IDIV_BITSPERCYCLE,
+  IDIV_ON_FPU :        IDIV_ON_FPU,
+  PMP_ENTRIES :        PMP_ENTRIES,
+  RESET_VECTOR :        RESET_VECTOR,
+  WFI_TIMEOUT_BIT :        WFI_TIMEOUT_BIT,
+  DTIM_SUPPORTED :        DTIM_SUPPORTED,
+  DTIM_BASE :        DTIM_BASE,
+  DTIM_RANGE :        DTIM_RANGE,
+  IROM_SUPPORTED :        IROM_SUPPORTED,
+  IROM_BASE :        IROM_BASE,
+  IROM_RANGE :        IROM_RANGE,
+  BOOTROM_SUPPORTED :        BOOTROM_SUPPORTED,
+  BOOTROM_BASE :        BOOTROM_BASE,
+  BOOTROM_RANGE :        BOOTROM_RANGE,
+  UNCORE_RAM_SUPPORTED :        UNCORE_RAM_SUPPORTED,
+  UNCORE_RAM_BASE :        UNCORE_RAM_BASE,
+  UNCORE_RAM_RANGE :        UNCORE_RAM_RANGE,
+  EXT_MEM_SUPPORTED :        EXT_MEM_SUPPORTED,
+  EXT_MEM_BASE :        EXT_MEM_BASE,
+  EXT_MEM_RANGE :        EXT_MEM_RANGE,
+  CLINT_SUPPORTED :        CLINT_SUPPORTED,
+  CLINT_BASE :        CLINT_BASE,
+  CLINT_RANGE :        CLINT_RANGE,
+  GPIO_SUPPORTED :        GPIO_SUPPORTED,
+  GPIO_BASE :        GPIO_BASE,
+  GPIO_RANGE :        GPIO_RANGE,
+  UART_SUPPORTED :        UART_SUPPORTED,
+  UART_BASE :        UART_BASE,
+  UART_RANGE :        UART_RANGE,
+  PLIC_SUPPORTED :        PLIC_SUPPORTED,
+  PLIC_BASE :        PLIC_BASE,
+  PLIC_RANGE :        PLIC_RANGE,
+  SDC_SUPPORTED :        SDC_SUPPORTED,
+  SDC_BASE :        SDC_BASE,
+  SDC_RANGE :        SDC_RANGE,
+  GPIO_LOOPBACK_TEST :        GPIO_LOOPBACK_TEST,
+  UART_PRESCALE :        UART_PRESCALE ,
+  PLIC_NUM_SRC :        PLIC_NUM_SRC,
+  PLIC_NUM_SRC_LT_32 :        PLIC_NUM_SRC_LT_32,
+  PLIC_GPIO_ID :        PLIC_GPIO_ID,
+  PLIC_UART_ID :        PLIC_UART_ID,
+  BPRED_SUPPORTED :        BPRED_SUPPORTED,
+                       /* verilator lint_off ENUMVALUE */
+                       // *** definitely need to fix this.
+                       // it thinks we are casting from the enum type to BPRED_TYPE.
+  BPRED_TYPE :        BPRED_TYPE,
+                       /* verilator lint_on ENUMVALUE */
+  BPRED_SIZE :        BPRED_SIZE,
+  BPRED_NUM_LHR : BPRED_NUM_LHR,                       
+  BTB_SIZE :        BTB_SIZE,
+  RADIX :        RADIX,
+  DIVCOPIES :        DIVCOPIES,
+  ZBA_SUPPORTED :        ZBA_SUPPORTED,
+  ZBB_SUPPORTED :        ZBB_SUPPORTED,
+  ZBC_SUPPORTED :        ZBC_SUPPORTED,
+  ZBS_SUPPORTED :        ZBS_SUPPORTED,
+  USE_SRAM :        USE_SRAM,
+  M_MODE  : M_MODE, 
+  S_MODE  : S_MODE, 
+  U_MODE  : U_MODE, 
+  VPN_SEGMENT_BITS : VPN_SEGMENT_BITS,
+  VPN_BITS : VPN_BITS,
+  PPN_BITS : PPN_BITS,
+  PA_BITS : PA_BITS,
+  SVMODE_BITS : SVMODE_BITS,
+  ASID_BASE : ASID_BASE,
+  ASID_BITS : ASID_BITS,
+  NO_TRANSLATE : NO_TRANSLATE,
+  SV32 : SV32,
+  SV39 : SV39,
+  SV48 : SV48,
+  A_SUPPORTED : A_SUPPORTED,
+  B_SUPPORTED : B_SUPPORTED,
+  C_SUPPORTED : C_SUPPORTED,
+  D_SUPPORTED : D_SUPPORTED,
+  E_SUPPORTED : E_SUPPORTED,
+  F_SUPPORTED : F_SUPPORTED,
+  I_SUPPORTED : I_SUPPORTED,
+  M_SUPPORTED : M_SUPPORTED,
+  Q_SUPPORTED : Q_SUPPORTED,
+  S_SUPPORTED : S_SUPPORTED,
+  U_SUPPORTED : U_SUPPORTED,
+  LOG_XLEN : LOG_XLEN,
+  PMPCFG_ENTRIES : PMPCFG_ENTRIES,
+  Q_LEN : Q_LEN,
+  Q_NE : Q_NE,
+  Q_NF : Q_NF,
+  Q_BIAS : Q_BIAS,
+  Q_FMT : Q_FMT,
+  D_LEN : D_LEN,
+  D_NE : D_NE,
+  D_NF : D_NF,
+  D_BIAS : D_BIAS,
+  D_FMT : D_FMT,
+  S_LEN : S_LEN,
+  S_NE : S_NE,
+  S_NF : S_NF,
+  S_BIAS : S_BIAS,
+  S_FMT : S_FMT,
+  H_LEN : H_LEN,
+  H_NE : H_NE,
+  H_NF : H_NF,
+  H_BIAS : H_BIAS,
+  H_FMT : H_FMT,
+  FLEN : FLEN,
+  NE   : NE  ,
+  NF   : NF  ,
+  FMT  : FMT ,
+  BIAS : BIAS,
+  FPSIZES : FPSIZES,
+  FMTBITS : FMTBITS,
+  LEN1  : LEN1 ,
+  NE1   : NE1  ,
+  NF1   : NF1  ,
+  FMT1  : FMT1 ,
+  BIAS1 : BIAS1,
+  LEN2  : LEN2 ,
+  NE2   : NE2  ,
+  NF2   : NF2  ,
+  FMT2  : FMT2 ,
+  BIAS2 : BIAS2,
+  CVTLEN : CVTLEN,
+  LLEN : LLEN,
+  LOGCVTLEN : LOGCVTLEN,
+  NORMSHIFTSZ : NORMSHIFTSZ,
+  LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
+  CORRSHIFTSZ : CORRSHIFTSZ,
+  DIVN        : DIVN,
+  LOGR        : LOGR,
+  RK          : RK,
+  LOGRK       : LOGRK,
+  FPDUR       : FPDUR,
+  DURLEN      : DURLEN,
+  DIVb        : DIVb,
+  DIVBLEN     : DIVBLEN,
+  DIVa        : DIVa
+};
diff --git a/config/shared/test-shared.vh b/config/shared/test-shared.vh
new file mode 100644
index 000000000..96ef1e929
--- /dev/null
+++ b/config/shared/test-shared.vh
@@ -0,0 +1,119 @@
+// constants defining different privilege modes
+// defined in Table 1.1 of the privileged spec
+localparam M_MODE  = (2'b11);
+localparam S_MODE  = (2'b01);
+localparam U_MODE  = (2'b00);
+
+// Virtual Memory Constants
+localparam VPN_SEGMENT_BITS = (XLEN == 32 ? 32'd10 : 32'd9);
+localparam VPN_BITS = (XLEN==32 ? (2*VPN_SEGMENT_BITS) : (4*VPN_SEGMENT_BITS));
+localparam PPN_BITS = (XLEN==32 ? 32'd22 : 32'd44);
+localparam PA_BITS = (XLEN==32 ? 32'd34 : 32'd56);
+localparam SVMODE_BITS = (XLEN==32 ? 32'd1 : 32'd4);
+localparam ASID_BASE = (XLEN==32 ? 32'd22 : 32'd44);
+localparam ASID_BITS = (XLEN==32 ? 32'd9 : 32'd16);
+
+// constants to check SATP_MODE against
+// defined in Table 4.3 of the privileged spec
+localparam NO_TRANSLATE = 4'd0;
+localparam SV32 = 4'd1;
+localparam SV39 = 4'd8;
+localparam SV48 = 4'd9;
+
+// macros to define supported modes
+localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
+localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
+localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
+localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
+localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
+localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
+localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
+localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
+localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
+localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
+localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+
+// logarithm of XLEN, used for number of index bits to select
+localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
+
+// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+localparam PMPCFG_ENTRIES = (PMP_ENTRIES/32'd8);
+
+// Floating point constants for Quad, Double, Single, and Half precisions
+// Lim: I've made some of these 64 bit to avoid width warnings. 
+// If errors crop up, try downsizing back to 32.
+localparam Q_LEN = 32'd128;
+localparam Q_NE = 32'd15;
+localparam Q_NF = 32'd112;
+localparam Q_BIAS = 32'd16383;
+localparam Q_FMT = 2'd3;
+localparam D_LEN = 32'd64;
+localparam D_NE = 32'd11;
+localparam D_NF = 32'd52;
+localparam D_BIAS = 32'd1023;
+localparam D_FMT = 2'd1;
+localparam S_LEN = 32'd32;
+localparam S_NE = 32'd8;
+localparam S_NF = 32'd23;
+localparam S_BIAS = 32'd127;
+localparam S_FMT = 2'd0;
+localparam H_LEN = 32'd16;
+localparam H_NE = 32'd5;
+localparam H_NF = 32'd10;
+localparam H_BIAS = 32'd15;
+localparam H_FMT = 2'd2;
+
+// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
+localparam FLEN = (Q_SUPPORTED ? Q_LEN  : D_SUPPORTED ? D_LEN  : S_LEN);
+localparam NE   = (Q_SUPPORTED ? Q_NE   : D_SUPPORTED ? D_NE   : S_NE);
+localparam NF   = (Q_SUPPORTED ? Q_NF   : D_SUPPORTED ? D_NF   : S_NF);
+localparam FMT  = (Q_SUPPORTED ? 2'd3    : D_SUPPORTED ? 2'd1    : 2'd0);
+localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS);
+/* Delete once tested dh 10/10/22
+
+localparam FLEN = (Q_SUPPORTED ? Q_LEN  : D_SUPPORTED ? D_LEN  : F_SUPPORTED ? S_LEN  : H_LEN);
+localparam NE   = (Q_SUPPORTED ? Q_NE   : D_SUPPORTED ? D_NE   : F_SUPPORTED ? S_NE   : H_NE);
+localparam NF   = (Q_SUPPORTED ? Q_NF   : D_SUPPORTED ? D_NF   : F_SUPPORTED ? S_NF   : H_NF); 
+localparam FMT  = (Q_SUPPORTED ? 2'd3       : D_SUPPORTED ? 2'd1       : F_SUPPORTED ? 2'd0       : 2'd2);
+localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : F_SUPPORTED ? S_BIAS : H_BIAS);*/
+
+// Floating point constants needed for FPU paramerterization
+localparam FPSIZES = ((32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED));
+localparam FMTBITS = ((32)'(FPSIZES>=3)+1);
+localparam LEN1  = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_LEN  : (F_SUPPORTED & (FLEN != S_LEN)) ? S_LEN  : H_LEN);
+localparam NE1   = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NE   : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NE   : H_NE);
+localparam NF1   = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NF   : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NF   : H_NF);
+localparam FMT1  = ((D_SUPPORTED & (FLEN != D_LEN)) ? 2'd1    : (F_SUPPORTED & (FLEN != S_LEN)) ? 2'd0    : 2'd2);
+localparam BIAS1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_BIAS : (F_SUPPORTED & (FLEN != S_LEN)) ? S_BIAS : H_BIAS);
+localparam LEN2  = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_LEN  : H_LEN);
+localparam NE2   = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NE   : H_NE);
+localparam NF2   = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF   : H_NF);
+localparam FMT2  = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0    : 2'd2);
+localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
+
+// division constants
+localparam DIVN        = (((NF+2<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
+localparam LOGR        = ($clog2(RADIX));           // r = log(R)
+localparam RK          = (LOGR*DIVCOPIES);         // r*k used for intdiv preproc
+localparam LOGRK       = ($clog2(RK));               // log2(r*k)
+localparam FPDUR       = ((DIVN+1+(LOGR*DIVCOPIES))/(LOGR*DIVCOPIES)+(RADIX/4));
+localparam DURLEN      = ($clog2(FPDUR+1));
+localparam DIVb        = (FPDUR*LOGR*DIVCOPIES-1); // canonical fdiv size (b)
+localparam DIVBLEN     = ($clog2(DIVb+1)-1);
+localparam DIVa        = (DIVb+1-XLEN); // used for idiv on fpu
+
+// largest length in IEU/FPU
+localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));
+localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
+localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
+localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6)));
+localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
+localparam CORRSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVN+1+NF) > (3*NF+4) ? (DIVN+1+NF) : (3*NF+4)));
+
+
+// Disable spurious Verilator warnings
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off ASSIGNDLY */
+/* verilator lint_off PINCONNECTEMPTY */
diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
index 3da14abd5..c743753ab 100644
--- a/config/shared/wally-shared.vh
+++ b/config/shared/wally-shared.vh
@@ -98,7 +98,7 @@
 `define FLEN (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `F_SUPPORTED ? `S_LEN  : `H_LEN)
 `define NE   (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `F_SUPPORTED ? `S_NE   : `H_NE)
 `define NF   (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `F_SUPPORTED ? `S_NF   : `H_NF) 
-`define FMT  (`Q_SUPPORTED ? 2'd3       : `D_SUPPORTED ? 2'd1       : `F_SUPPORTED ? 2'd0       : 2'd2)
+`define FMT  (`Q_SUPPORTED ? 2'd3    : `D_SUPPORTED ? 2'd1    : `F_SUPPORTED ? 2'd0    : 2'd2)
 `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
 
 // Floating point constants needed for FPU paramerterization
@@ -125,7 +125,7 @@
 
 // division constants
 
-`define DIVN        (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
+`define DIVN        ((((`NF+2)<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
 `define LOGR        ($clog2(`RADIX))            // r = log(R)
 `define RK          (`LOGR*`DIVCOPIES)          // r*k used for intdiv preproc
 `define LOGRK       ($clog2(`RK))               // log2(r*k)
diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md
index a25b3a189..37390a632 100644
--- a/docs/testplans/testplan.md
+++ b/docs/testplans/testplan.md
@@ -1,6 +1,29 @@
-# CORE-V Wally Test Plan
+# CORE-V Wally Design Verification Test Plan
+
+CORE-V Wally is functionally tested in the following ways.  Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
+
+| Functions      | Coverage Method | Status |
+| ----------- | ----------- |----|
+|  Instructions | riscv-arch-test | Pass   |
+| Privileged Unit   | wally-riscv-arch-test        | Pass   |
+| Virtual Memory | wally-riscv-arch-test | Pass |
+| PMP | wally-riscv-arch-test | Pass
+| Peripherals | wally-riscv-arch-test | Pass |
+| Floating-Point | TestFloat | Pass |
+| General | Code Coverage | 91% |
+| General | Boot Linux in Sim | Pass | 
+| General | Boot Linux on FPGA | Pass |
+
+
+The following performance validation is also run:
+| Function | Method | Status |
+| --- | --- | --- |
+| Overall Performance | embench | Pass|
+| Overall Performance | coremark | Pass |
+| Branch Predictor | *** | Pass |
+| Cache Miss Rate | *** | Pass |
+
 
-CORE-V Wally is tested in the following ways:
 
 * Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
 * Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
diff --git a/examples/C/common/test.ld b/examples/C/common/test.ld
index a50b017e8..5eccb434c 100644
--- a/examples/C/common/test.ld
+++ b/examples/C/common/test.ld
@@ -28,8 +28,8 @@ SECTIONS
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
 
-  . = ALIGN(0x1000);
-  .text : { *(.text) }
+/*  . = ALIGN(0x1000);
+  .text : { *(.text) } */
 
   /* data segment */
   .data : { *(.data) }
diff --git a/examples/C/inline/inline b/examples/C/inline/inline
deleted file mode 100755
index 29b5b8bff..000000000
Binary files a/examples/C/inline/inline and /dev/null differ
diff --git a/examples/C/sum_mixed/sum_mixed b/examples/C/sum_mixed/sum_mixed
deleted file mode 100755
index 62ac4022a..000000000
Binary files a/examples/C/sum_mixed/sum_mixed and /dev/null differ
diff --git a/examples/asm/trap/trap b/examples/asm/trap/trap
deleted file mode 100755
index 1d7d3bbc6..000000000
Binary files a/examples/asm/trap/trap and /dev/null differ
diff --git a/examples/verilog/fulladder/fulladder-batch-coverage.do b/examples/verilog/fulladder/fulladder-batch-coverage.do
new file mode 100644
index 000000000..324ac9142
--- /dev/null
+++ b/examples/verilog/fulladder/fulladder-batch-coverage.do
@@ -0,0 +1,8 @@
+# fulladder-batch-coverage.do 
+# David_Harris@hmc.edu 22 May 2023
+vlog fulladder.sv 
+vopt +acc work.testbench -o workopt +cover=sbecf
+vsim workopt -coverage
+run -all
+coverage save -instance /testbench/dut fulladder.ucdb
+quit
\ No newline at end of file
diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 4b760eb65..f09acb6c1 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -17,1130 +17,1130 @@ endgroup
 connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe6]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe10]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe11]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe12]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe13]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe14]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe15]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe16]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 5 [get_debug_ports u_ila_0/probe17]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe18]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe19]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 63 [get_debug_ports u_ila_0/probe20]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe21]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe23]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe24]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
+connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe25]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
+connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe26]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe27]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe28]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
+connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe29]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
+connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe30]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
+connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe31]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
+connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe34]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe35]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe36]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe37]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe38]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe39]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe40]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe41]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe42]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe43]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe44]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe45]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe46]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe47]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe48]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe49]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe50]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe51]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe52]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe53]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe54]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe55]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]]
+connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe56]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]]
+connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe57]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe58]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]]
+connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe59]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
+connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe60]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
+connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe61]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
+connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe62]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
+connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe63]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
+connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe64]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe65]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe66]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe67]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe68]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
+connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe69]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe70]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe71]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
 
 # StallW is StallM.  trying to connect to StallW causes issues.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe72]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe73]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe74]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
+connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe75]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe76]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
+connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe77]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
+connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe78]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
+connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe79]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe80]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe81]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
+connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe82]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
+connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe83]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 53 [get_debug_ports u_ila_0/probe84]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
+connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe85]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
+connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe86]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
+connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe87]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
+connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe88]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
+connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe89]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
+connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe90]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
+connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe91]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
+connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe92]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
+connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe93]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
+connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe94]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
+connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe95]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
+connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe96]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
+connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe97]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
+connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe98]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
+connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 56 [get_debug_ports u_ila_0/probe100]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe101]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe102]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
+connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe103]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe105]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe106]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
-connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe107]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
-connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe108]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
-connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
+connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe109]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
-connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
+connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe110]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
-connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
+connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe111]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
-connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
+connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe112]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
-connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
+connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe113]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
-connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
+connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe114]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
-connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
+connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe115]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
-connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
+connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe116]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
-connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
+connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe117]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
-connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
+connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe118]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
-connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
+connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe119]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
-connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
+connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe120]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
-connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
+connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe122]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
-connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
+connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe123]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
-connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
+connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe124]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
-connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe125]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
-connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe126]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
-connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe130]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
-connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe131]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
-connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
+connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe132]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
-connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
+connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe133]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
-connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
+connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe134]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
-connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
+connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe135]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
-connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
+connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe136]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
-connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
+connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
-connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
+connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe138]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
-connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
 
 # UART Signals -------------------------------------------------------
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe139]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
-connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe140]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
-connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe141]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
-connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe142]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
-connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe143]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
-connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe144]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
-connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe145]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
-connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe146]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
-connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe147]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
-connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe148]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
-connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe149]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
-connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe150]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150]
-connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]]
+connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe151]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151]
-connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]]
+connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe152]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152]
-connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]]
+connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe153]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153]
-connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]]
+connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe154]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
-connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]]
+connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe155]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
-connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]]
+connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 5 [get_debug_ports u_ila_0/probe156]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
-connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]]
+connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe157]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
-connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]]
+connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe158]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
-connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]]
+connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe159]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
-connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]]
+connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe160]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
-connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]]
+connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe161]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
-connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]]
+connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe162]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
-connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]]
+connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe163]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
-connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]]
+connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe164]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
-connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]]
+connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe165]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
-connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]]
+connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe166]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
-connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]]
+connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe167]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
-connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]]
+connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe168]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
-connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]]
+connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe169]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
-connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]]
+connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe170]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
-connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]]
+connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe171]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
-connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]]
+connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe172]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
-connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]]
+connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe173]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173]
-connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]]
+connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe174]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174]
-connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]]
+connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe175]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175]
-connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]]
+connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe176]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176]
-connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]]
+connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe177]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177]
-connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]]
+connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe178]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178]
-connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]]
+connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe179]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179]
-connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]]
+connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe180]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180]
-connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]]
+connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe181]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181]
-connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]]
+connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe182]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182]
-connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]]
+connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe183]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183]
-connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]]
+connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe184]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184]
-connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]]
+connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe185]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185]
-connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]]
+connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe186]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186]
-connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]]
+connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe187]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187]
-connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]]
+connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe188]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188]
-connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]]
+connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 31 [get_debug_ports u_ila_0/probe189]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189]
-connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]]
+connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 16 [get_debug_ports u_ila_0/probe190]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190]
-connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]]
+connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 16 [get_debug_ports u_ila_0/probe191]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191]
-connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]]
+connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe192]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192]
-connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]]
+connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe193]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193]
-connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
+connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe194]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194]
-connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
+connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe195]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195]
-connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]]
+connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe196]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196]
-connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]]
+connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe197]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197]
-connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]]
+connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe198]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198]
-connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]]
+connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe199]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199]
-connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]]
+connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe200]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200]
-connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]]
+connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe201]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201]
-connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]]
+connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe202]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202]
-connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]]
+connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe203]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203]
-connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]]
+connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe204]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204]
-connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]]
+connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe205]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205]
-connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]]
+connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe206]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206]
-connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]]
+connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe207]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207]
-connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]]
+connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe208]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208]
-connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]]
+connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe209]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209]
-connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]]
+connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe210]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210]
-connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]]
+connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe211]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211]
-connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]]
+connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe212]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212]
-connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]]
+connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe213]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213]
-connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]]
+connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 70 [get_debug_ports u_ila_0/probe214]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214]
-connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]]
+connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe215]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215]
-connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]]
+connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 10 [get_debug_ports u_ila_0/probe216]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216]
-connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]]
+connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe217]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217]
-connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]]
+connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe218]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218]
-connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]]
+connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe219]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219]
-connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]]
+connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe220]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220]
-connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]]
+connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe221]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221]
-connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]]
+connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe222]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222]
-connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]]
+connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 53 [get_debug_ports u_ila_0/probe223]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223]
-connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]]
+connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]]
 
diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc
index 98200a3d1..170b38346 100644
--- a/fpga/constraints/debug4.xdc
+++ b/fpga/constraints/debug4.xdc
@@ -17,705 +17,705 @@ endgroup
 connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe6]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe10]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe11]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe12]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe13]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe14]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe15]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe16]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 5 [get_debug_ports u_ila_0/probe17]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe18]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe19]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 63 [get_debug_ports u_ila_0/probe20]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe21]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe23]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe24]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
+connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe25]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
+connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe26]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe27]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe28]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
+connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe29]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
+connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe30]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
+connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe31]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
+connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe34]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe35]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe36]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe37]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe38]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe39]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe40]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe41]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe42]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe43]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe44]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe45]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe46]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe47]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe48]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe49]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe50]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe51]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe52]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe53]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe54]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe55]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]]
+connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe56]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]]
+connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe57]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe58]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]]
+connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe59]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
+connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe60]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
+connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe61]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
+connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe62]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
+connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe63]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
+connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe64]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe65]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe66]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe67]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe68]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
+connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe69]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe70]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe71]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
 
 # StallW is StallM.  trying to connect to StallW causes issues.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe72]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe73]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe74]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
+connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe75]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe76]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
+connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe77]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
+connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe78]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
+connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe79]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe80]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe81]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
+connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe82]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
+connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe83]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 53 [get_debug_ports u_ila_0/probe84]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
+connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe85]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
+connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe86]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
+connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe87]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
+connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe88]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
+connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe89]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
+connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe90]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
+connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe91]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
+connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe92]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
+connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe93]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
+connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe94]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
+connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe95]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
+connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe96]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
+connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe97]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
+connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe98]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
+connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 56 [get_debug_ports u_ila_0/probe100]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe101]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe102]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
+connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe103]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe105]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe106]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
-connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe107]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
-connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe108]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
-connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
+connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe109]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
-connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
+connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe110]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
-connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
+connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe111]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
-connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
+connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe112]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
-connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
+connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe113]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
-connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
+connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe114]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
-connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
+connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe115]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
-connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
+connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe116]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
-connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
+connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe117]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
-connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
+connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe118]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
-connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
+connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe119]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
-connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
+connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe120]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
-connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
+connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe122]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
-connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
+connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe123]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
-connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
+connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe124]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
-connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe125]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
-connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe126]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
-connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe130]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
-connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe131]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
-connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
+connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe132]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
-connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
+connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe133]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
-connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
+connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe134]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
-connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
+connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe135]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
-connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
+connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe136]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
-connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
+connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
-connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
+connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe138]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
-connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
 
 
 create_debug_port u_ila_0 probe
diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc
index b50777f0d..2938c3ec0 100644
--- a/fpga/constraints/small-debug.xdc
+++ b/fpga/constraints/small-debug.xdc
@@ -21,32 +21,32 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK]
 
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 28 [get_debug_ports u_ila_0/probe6]
@@ -131,7 +131,7 @@ connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
 
 # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
 #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc
new file mode 100644
index 000000000..62fea508f
--- /dev/null
+++ b/fpga/constraints/vcu-small-debug.xdc
@@ -0,0 +1,52 @@
+create_debug_core u_ila_0 ila
+
+set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+startgroup 
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
+endgroup
+connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
+
+set_property port_width 64 [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index ff34c0327..1d6f5bcce 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -3,9 +3,9 @@ sdc_src := ~/repos/sdc.tar.gz
 
 # Select the desired board and the all build rules
 # vcu118
-#export XILINX_PART := xcvu9p-flga2104-2L-e
-#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
-#export board := vcu118
+export XILINX_PART := xcvu9p-flga2104-2L-e
+export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
+export board := vcu118
 
 # vcu108
 #export XILINX_PART := xcvu095-ffva2104-2-e
@@ -13,15 +13,15 @@ sdc_src := ~/repos/sdc.tar.gz
 #export board := vcu108
 
 # Arty A7
-export XILINX_PART := xc7a100tcsg324-1
-export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
-export board := ArtyA7
+#export XILINX_PART := xc7a100tcsg324-1
+#export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
+#export board := ArtyA7
 
 # for Arty A7 and S7 boards
-all: FPGA_Arty
+#all: FPGA_Arty
 
 # VCU 108 and VCU 118 boards
-#all: FPGA_VCU
+all: FPGA_VCU
 
 FPGA_Arty: PreProcessFiles IP_Arty SDC
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index d5a2fca43..a28d42654 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -12,6 +12,17 @@ if {$boardName!="ArtyA7"} {
     set_property board_part $boardName [current_project]
 }
 
+# read package first
+read_verilog -sv  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
+read_verilog -sv  ../src/wallypipelinedsocwrapper.sv
+# then read top level
+if {$board=="ArtyA7"} {
+    read_verilog  {../src/fpgaTopArtyA7.v}
+} else {
+    read_verilog  {../src/fpgaTop.v}
+}
+
+# read in ip
 read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
 read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
 read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
@@ -23,17 +34,13 @@ if {$board=="ArtyA7"} {
     read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 }
 
-read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
-if {$board=="ArtyA7"} {
-    read_verilog  {../src/fpgaTopArtyA7.v}
-} else {
-    read_verilog  {../src/fpgaTop.v}
-}
+# read in all other rtl
+read_verilog -sv [glob -type f  ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
+
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
 set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
-
 if {$board=="ArtyA7"} {
     add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
     set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$board.xdc]
@@ -45,7 +52,6 @@ if {$board=="ArtyA7"} {
 # define top level
 set_property top fpgaTop [current_fileset]
 
-
 update_compile_order -fileset sources_1
 # This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
 exec mkdir -p reports/
@@ -76,8 +82,8 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
 if {$board=="ArtyA7"} {
     source ../constraints/small-debug.xdc
 
-} else {    
-    source ../constraints/debug4.xdc
+} else {
+    source ../constraints/vcu-small-debug.xdc
 }
 
 
diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
index 0d36926cf..81fc67f05 100644
--- a/fpga/generator/wave_config.wcfg
+++ b/fpga/generator/wave_config.wcfg
@@ -20,17 +20,17 @@
    <WVObjectSize size="32" />
    <wave_markers>
    </wave_markers>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/PCM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63:0]</obj_property>
       <obj_property name="ObjectShortName">PCM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/InstrM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrM[31:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31:0]</obj_property>
       <obj_property name="ObjectShortName">InstrM[31:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -40,37 +40,37 @@
       <obj_property name="label">rd</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[11]">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]">
          <obj_property name="ElementShortName">[11]</obj_property>
          <obj_property name="ObjectShortName">[11]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[10]">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]">
          <obj_property name="ElementShortName">[10]</obj_property>
          <obj_property name="ObjectShortName">[10]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[9]">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]">
          <obj_property name="ElementShortName">[9]</obj_property>
          <obj_property name="ObjectShortName">[9]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[8]">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]">
          <obj_property name="ElementShortName">[8]</obj_property>
          <obj_property name="ObjectShortName">[8]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[7]">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]">
          <obj_property name="ElementShortName">[7]</obj_property>
          <obj_property name="ObjectShortName">[7]</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrValidM">
+   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrValidM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM</obj_property>
       <obj_property name="ObjectShortName">InstrValidM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/TrapM">
+   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/TrapM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM</obj_property>
       <obj_property name="ObjectShortName">TrapM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -78,66 +78,66 @@
    <wvobject type="group" fp_name="group468">
       <obj_property name="label">CPU to LSU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
          <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
          <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
          <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
          <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
       <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
       <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
       <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
       <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -150,49 +150,49 @@
    <wvobject type="group" fp_name="group471">
       <obj_property name="label">interrupts</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
          <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
          <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
          <obj_property name="ObjectShortName">InterruptM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
       <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
+   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
       <obj_property name="ObjectShortName">InterruptM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -200,55 +200,55 @@
    <wvobject type="group" fp_name="group463">
       <obj_property name="label">LSU to Bus</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHADDR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHADDR[31:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHBURST">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHBURST[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHREADY">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
          <obj_property name="ObjectShortName">LSUHREADY</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHSIZE">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHSIZE[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHWDATA">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHWDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHWRITE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWRITE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE</obj_property>
          <obj_property name="ObjectShortName">LSUHWRITE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -259,9 +259,9 @@
       <obj_property name="label">dcache</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -273,71 +273,71 @@
       <obj_property name="label">EBU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HTRANS">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]</obj_property>
          <obj_property name="ObjectShortName">HTRANS[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HWRITE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWRITE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE</obj_property>
          <obj_property name="ObjectShortName">HWRITE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HBURST">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]</obj_property>
          <obj_property name="ObjectShortName">HBURST[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HSIZE">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]</obj_property>
          <obj_property name="ObjectShortName">HSIZE[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HADDR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]</obj_property>
          <obj_property name="ObjectShortName">HADDR[31:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HWDATA">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">HWDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HREADY">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HREADY</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY</obj_property>
          <obj_property name="ObjectShortName">HREADY</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HRESP">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HRESP</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP</obj_property>
          <obj_property name="ObjectShortName">HRESP</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -346,225 +346,225 @@
    <wvobject type="group" fp_name="group2103">
       <obj_property name="label">uart</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/DTRb">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/DTRb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb</obj_property>
          <obj_property name="ObjectShortName">DTRb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/INTR">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/INTR</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR</obj_property>
          <obj_property name="ObjectShortName">INTR</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b</obj_property>
          <obj_property name="ObjectShortName">OUT1b</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b</obj_property>
          <obj_property name="ObjectShortName">OUT2b</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/RTSb">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/RTSb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb</obj_property>
          <obj_property name="ObjectShortName">RTSb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb</obj_property>
          <obj_property name="ObjectShortName">RXRDYb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/SIN">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/SIN</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN</obj_property>
          <obj_property name="ObjectShortName">SIN</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/SOUT">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/SOUT</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT</obj_property>
          <obj_property name="ObjectShortName">SOUT</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb</obj_property>
          <obj_property name="ObjectShortName">TXRDYb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0]</obj_property>
          <obj_property name="ObjectShortName">DLL[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0]</obj_property>
          <obj_property name="ObjectShortName">DLM[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">FCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled</obj_property>
          <obj_property name="ObjectShortName">fifoenabled</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/IER">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0]</obj_property>
          <obj_property name="ObjectShortName">IER[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0]</obj_property>
          <obj_property name="ObjectShortName">intrID[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">LCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0]</obj_property>
          <obj_property name="ObjectShortName">LSR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0]</obj_property>
          <obj_property name="ObjectShortName">MCR[4:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0]</obj_property>
          <obj_property name="ObjectShortName">MSR[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0]</obj_property>
          <obj_property name="ObjectShortName">RBR[10:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr</obj_property>
          <obj_property name="ObjectShortName">rxdataavailintr</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready</obj_property>
          <obj_property name="ObjectShortName">rxdataready</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP</obj_property>
          <obj_property name="ObjectShortName">RXerrIP</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1</obj_property>
          <obj_property name="ObjectShortName">RXerrIP_1</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0]</obj_property>
          <obj_property name="ObjectShortName">rxfifoentries[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered</obj_property>
          <obj_property name="ObjectShortName">rxfifotriggered</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr</obj_property>
          <obj_property name="ObjectShortName">rxparityerr</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0]</obj_property>
          <obj_property name="ObjectShortName">rxstate[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">SCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0]</obj_property>
          <obj_property name="ObjectShortName">txstate[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -574,79 +574,79 @@
    <wvobject type="group" fp_name="group2207">
       <obj_property name="label">faults</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BreakpointFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
          <obj_property name="ObjectShortName">BreakpointFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/EcallFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
          <obj_property name="ObjectShortName">EcallFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM</obj_property>
          <obj_property name="ObjectShortName">IllegalInstrFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">InstrAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM</obj_property>
          <obj_property name="ObjectShortName">InstrPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadMisalignedFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoMisalignedFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -655,86 +655,86 @@
    <wvobject type="group" fp_name="group1735">
       <obj_property name="label">hazards</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BPPredWrongE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPPredWrongE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BPPredWrongE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPPredWrongE</obj_property>
          <obj_property name="ObjectShortName">BPPredWrongE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BreakpointFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
          <obj_property name="ObjectShortName">BreakpointFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/CSRRdStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/CSRRdStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD</obj_property>
          <obj_property name="ObjectShortName">CSRRdStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM</obj_property>
          <obj_property name="ObjectShortName">CSRWriteFencePendingDEM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/DivBusyE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/DivBusyE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/DivBusyE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/DivBusyE</obj_property>
          <obj_property name="ObjectShortName">DivBusyE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/EcallFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
          <obj_property name="ObjectShortName">EcallFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FDivBusyE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FDivBusyE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE</obj_property>
          <obj_property name="ObjectShortName">FDivBusyE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/IFUStallF">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/IFUStallF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF</obj_property>
          <obj_property name="ObjectShortName">IFUStallF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/LoadStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/LoadStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD</obj_property>
          <obj_property name="ObjectShortName">LoadStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/LSUStallM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/LSUStallM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM</obj_property>
          <obj_property name="ObjectShortName">LSUStallM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/MDUStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/MDUStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD</obj_property>
          <obj_property name="ObjectShortName">MDUStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StoreStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StoreStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD</obj_property>
          <obj_property name="ObjectShortName">StoreStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -744,74 +744,74 @@
       <obj_property name="label">flush/stall</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD</obj_property>
          <obj_property name="ObjectShortName">FlushD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE</obj_property>
          <obj_property name="ObjectShortName">FlushE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM</obj_property>
          <obj_property name="ObjectShortName">FlushM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushW">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushW</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW</obj_property>
          <obj_property name="ObjectShortName">FlushW</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallD">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallD</obj_property>
          <obj_property name="ObjectShortName">StallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallE">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE</obj_property>
          <obj_property name="ObjectShortName">StallE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallF">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF</obj_property>
          <obj_property name="ObjectShortName">StallF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM</obj_property>
          <obj_property name="ObjectShortName">StallM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">csrs.SCAUSE_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">MCAUSE_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -821,35 +821,35 @@
       <obj_property name="label">IFU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
          <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="label">icache fsm</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
          <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="label">ifu bus fsm</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCNextF">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
          <obj_property name="ObjectShortName">PCNextF[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCPF">
+      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
          <obj_property name="ObjectShortName">PCPF[55:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -860,78 +860,78 @@
       <obj_property name="label">TLB</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBMissM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
          <obj_property name="ObjectShortName">DTLBMissM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBWriteM">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
          <obj_property name="ObjectShortName">DTLBWriteM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBMissF">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
          <obj_property name="ObjectShortName">ITLBMissF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBWriteF">
+      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
          <obj_property name="ObjectShortName">ITLBWriteF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">MEPC_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">SEPC_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[2]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[4]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[10]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState">
+   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0]</obj_property>
       <obj_property name="ObjectShortName">WalkerState[3:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index 990495f44..b6d2a4d9e 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -24,8 +24,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
    input 		   default_250mhz_clk1_0_p, 
@@ -72,12 +70,12 @@ module fpgaTop
   
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
-  wire [`AHBW-1:0] HRDATAEXT;
+  wire [64-1:0] HRDATAEXT;
   wire 			   HREADYEXT;
   wire 			   HRESPEXT;
   wire 			   HSELEXT;
   wire [31:0] 	   HADDR;
-  wire [`AHBW-1:0] HWDATA;
+  wire [64-1:0] HWDATA;
   wire 			   HWRITE;
   wire [2:0] 	   HSIZE;
   wire [2:0] 	   HBURST;
@@ -211,7 +209,7 @@ module fpgaTop
   
 
   // wally
-  wallypipelinedsoc wallypipelinedsoc
+  wallypipelinedsocwrapper wallypipelinedsocwrapper
     (.clk(CPUCLK),
      .reset_ext(bus_struct_reset),
      // bus interface
diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v
index 86e441b0c..0b10fe4e9 100644
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@@ -225,7 +225,7 @@ module fpgaTop
      .peripheral_aresetn(peripheral_aresetn));
 
   // wally
-  wallypipelinedsoc wallypipelinedsoc
+  wallypipelinedsocwrapper wallypipelinedsocwrapper
     (.clk(CPUCLK),
      .reset_ext(bus_struct_reset),
      // bus interface
diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv
new file mode 100644
index 000000000..bdde7f4fc
--- /dev/null
+++ b/fpga/src/wallypipelinedsocwrapper.sv
@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// wallypipelinedsocwrapper.sv
+//
+// Written: Ross Thompson ross1728@gmail.com 16 June 2023
+// Modified: 
+//
+// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
+//          not system verilog.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+
+import cvw::*;
+
+module wallypipelinedsocwrapper (
+  input  logic                clk, 
+  input  logic                reset_ext,        // external asynchronous reset pin
+  output logic                reset,            // reset synchronized to clk to prevent races on release
+  // AHB Interface
+  input  logic [64-1:0]     HRDATAEXT,
+  input  logic                HREADYEXT, HRESPEXT,
+  output logic                HSELEXT,
+  // outputs to external memory, shared with uncore memory
+  output logic                HCLK, HRESETn,
+  output logic [64-1:0]  HADDR,
+  output logic [64-1:0]     HWDATA,
+  output logic [64/8-1:0]   HWSTRB,
+  output logic                HWRITE,
+  output logic [2:0]          HSIZE,
+  output logic [2:0]          HBURST,
+  output logic [3:0]          HPROT,
+  output logic [1:0]          HTRANS,
+  output logic                HMASTLOCK,
+  output logic                HREADY,
+  // I/O Interface
+  input  logic                TIMECLK,          // optional for CLINT MTIME counter
+  input  logic [31:0]         GPIOIN,           // inputs from GPIO
+  output logic [31:0]         GPIOOUT,          // output values for GPIO
+  output logic [31:0]         GPIOEN,           // output enables for GPIO
+  input  logic                UARTSin,          // UART serial data input
+  output logic                UARTSout,         // UART serial data output
+  input  logic                SDCCmdIn,         // SDC Command input
+  output logic                SDCCmdOut,        // SDC Command output
+  output logic                SDCCmdOE,         // SDC Command output enable
+  input  logic [3:0]          SDCDatIn,         // SDC data input
+  output logic                SDCCLK            // SDC clock
+);
+  `include "parameter-defs.vh"
+
+  wallypipelinedsoc  #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+endmodule
diff --git a/setup.sh b/setup.sh
index 2115a0d71..95026beb1 100755
--- a/setup.sh
+++ b/setup.sh
@@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY}
 export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change this to your Siemens license server
 export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
 export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim        # Change this for your path to Questa, excluding bin
+#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim        # Change this for your path to Questa, excluding bin
 export SNPS_HOME=/cad/synopsys/SYN                                  # Change this for your path to Design Compiler, excluding bin
 
 # Path to RISC-V Tools
diff --git a/sim/FPbuild.txt b/sim/FPbuild.txt
new file mode 100644
index 000000000..99f414804
--- /dev/null
+++ b/sim/FPbuild.txt
@@ -0,0 +1,56 @@
+Procedure for Runnning SoftFloat/TestFloat with Wally
+
+1.) First, compile SoftFloat and TestFloat by going to the addins
+directory and finding the specific build directory (e.g.,
+Linux_x86_64-GCC.  Currently, we are using v3e of
+SoftFloat/TestFloat.  I am not sure of the order, but I always compile
+SoftFloat first as I believe TestFloat uses the static library
+SoftFloat creates.
+
+2.) Once compiled both, go to the tests/fp directory and run the
+create_vectors.sh Linux script.  In the past, we have automated this,
+but I believe this has fallen into more of a manual state lately.
+
+3.) Then, run remove_spaces.sh which will remove spaces from the
+output and put underscores between vectors (this helps differentiate
+the vectors that are generated).  Again, this can be combined with
+Step 2.
+
+4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with
+its respective test.  The format is ./sim-testfloat-add add.  All of
+the tests are listed below.  This can be augmented or added to for
+other FP tests given by the great SoftFloat/TestFloat output.
+
+ cvtint - test integer conversion unit (fcvtint)
+ cvtfp  - test floating-point conversion unit (fcvtfp)
+ cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+ add    - test addition
+ fma    - test fma
+ mul    - test mult with fma
+ sub    - test subtraction
+ div    - test division
+ sqrt   - test square root
+ all    - test everything
+
+4a.) Each test will test all its vectors - if you want to test a
+subset of the vectors (e.g., only binary16), you should modify the
+testfloat.do in the sim directory.  Change the TEST_SIZE="all" to the
+specific test you want to run.  For example, if you want to run only
+binary16, you should set this variable to TEST_SIZE="HP".
+
+4b.) If you want to turn off the generation of wlf files while running
+sim-testfloat-batch, you can modify testfloat.do in the sim
+directory.  Inside this DO file, modify the WAV file to 0 --> i.e.,
+set "quietly set WAV 0;"
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/sim/Makefile b/sim/Makefile
index 9cf3f0034..ac37a36b7 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -18,8 +18,8 @@ all: riscoftests memfiles coveragetests
 coverage:
 	#make -C ../tests/coverage --jobs
 	#iter-elf.bash --cover --search ../tests/coverage
-	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
-#	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log
+	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log
+#	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
 	vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 60574e371..4f1757cb8 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -46,18 +46,33 @@ configs = [
     )
 ]
 
+# bpdSize = [6, 8, 10, 12, 14, 16]
+# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
+# for CurrBPType in bpdType:
+#     for CurrBPSize in bpdSize:
+#         name = CurrBPType+str(CurrBPSize)
+#         configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
+#         tc = TestCase(
+#             name=name,
+#             variant="rv32gc",
+#             cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+#             grepstr="")
+#         configs.append(tc)
+
 bpdSize = [6, 8, 10, 12, 14, 16]
-bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic']
+LHRSize = [4, 8, 10]
+bpdType = ['local_repair']
 for CurrBPType in bpdType:
     for CurrBPSize in bpdSize:
-        name = CurrBPType+str(CurrBPSize)
-        configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
-        tc = TestCase(
-            name=name,
-            variant="rv32gc",
-            cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
-            grepstr="")
-        configs.append(tc)
+        for CurrLHRSize in  LHRSize:
+            name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
+            configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
+            tc = TestCase(
+                name=name,
+                variant="rv32gc",
+                cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+                grepstr="")
+            configs.append(tc)
 
 import os
 from multiprocessing import Pool, TimeoutError
diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index 4f90333a9..074997bf4 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -31,11 +31,14 @@
 do GetLineNum.do
 
 # LZA (i<64) statement confuses coverage tool 
-# This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
+# DH 4/22/23: Exclude all LZAs
 coverage exclude -srcfile lzc.sv 
 
-# FDIVSQRT has 
+# DH 4/22/23: FDIVSQRT can't go directly from done to busy again
 coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
+# DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy.  The flush is caused by a trap or return,
+# which won't happen while the divider is busy. 
+coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
 
 ### Exclude D$ states and logic for the I$ instance
 # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
@@ -74,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} {
     coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
     coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
     # below: flushD can't go high during an icache write b/c of pipeline stall
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
+    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
 }
 
 ## D$ Exclusions.
@@ -85,11 +88,18 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get
 coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
 set numcacheways 4
 for {set i 0} {$i < $numcacheways} {incr i} {
-    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4
+    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
+
+    # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
+    # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
+    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
 }
 # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
 coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
 
+####################
+# Unused / illegal peripheral accesses
+####################
 
 # Excluding peripherals as sources of instructions for the ifu
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
@@ -97,31 +107,134 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
 
+# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+
 # Excluding so far un-used instruction sources for the ifu
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
 
-
 #Excluding the bootrom, uncoreran, and clint as sources for the lsu
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
 
-
 #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
 
-# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
+set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
+
+####################
+# Unused access types due to sharing IFU and LSU logic
+####################
+
+## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
+set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
+set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF    \\|"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3 
 
-# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
+
+## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
 set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
\ No newline at end of file
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
+set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM    & PMAAccessFault"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM   & PMAAccessFault"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
+set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
+set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM     \\| PMPLoadAccessFaultM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
+
+# IMMU only makes word-sized accesses
+set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"] 
+set line2 [expr $line + 6 ]
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
+
+# No irom
+set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] 
+coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
+set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"] 
+coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
+
+# Excluding reset and clear for impossible case in the wficountreg in privdec
+set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
+coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
+
+# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
+# This is a blunt instrument; perhaps there is a more graceful exclusion
+coverage exclude -srcfile priorityonehot.sv 
+
+# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
diff --git a/sim/imperas.ic b/sim/imperas.ic
index d561b22f2..ad19aaf68 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,7 +1,7 @@
 #--mpdconsole
 #--gdbconsole
---showoverrides
---showcommands
+#--showoverrides
+#--showcommands
 
 # Core settings
 --override cpu/priv_version=1.12 
diff --git a/sim/lint-wally b/sim/lint-wally
index 4ff93af60..6db56b0a9 100755
--- a/sim/lint-wally
+++ b/sim/lint-wally
@@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
 for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
 #for config in  rv64gc; do
     echo "$config linting..."
-    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
diff --git a/sim/linux-wave.do b/sim/linux-wave.do
index d8bb0f3db..614c6ab07 100644
--- a/sim/linux-wave.do
+++ b/sim/linux-wave.do
@@ -3,17 +3,18 @@ quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/co
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
-add wave -noupdate -expand -group Testbench /testbench/reset_ext
-add wave -noupdate -expand -group Testbench -radix unsigned /testbench/InstrCountW
-add wave -noupdate -expand -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
-add wave -noupdate -expand -group Testbench -radix decimal /testbench/interruptInstrCount
-add wave -noupdate -expand -group Testbench /testbench/interruptCauseVal
-add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal
-add wave -noupdate -expand -group Testbench /testbench/interruptTVal
-add wave -noupdate -expand -group Testbench /testbench/interruptDesc
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW
+add wave -noupdate -group Testbench /testbench/reset_ext
+add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW
+add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
+add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount
+add wave -noupdate -group Testbench /testbench/interruptCauseVal
+add wave -noupdate -group Testbench /testbench/interruptEpcVal
+add wave -noupdate -group Testbench /testbench/interruptTVal
+add wave -noupdate -group Testbench /testbench/interruptDesc
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
 add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
 add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
@@ -30,17 +31,16 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv
 add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
 add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
 add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
 add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
 add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
 add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
 add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
 add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
@@ -73,55 +73,12 @@ add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
 add wave -noupdate -group {WriteBack stage} /testbench/textW
-add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
-add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
 add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
-add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
 add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
 add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
 add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/core/PCF
 add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
 add wave -noupdate -group PCS /testbench/dut/core/PCE
 add wave -noupdate -group PCS /testbench/dut/core/PCM
@@ -129,10 +86,6 @@ add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
@@ -147,7 +100,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
@@ -165,10 +117,6 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
 add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
@@ -176,162 +124,149 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNe
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
 add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
 add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/PAdrM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
-add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
-add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
+add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
+add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
@@ -344,23 +279,12 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F
-add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
-add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
-add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/funct
-add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/result
-add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srca
-add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srcb
-add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/width
 add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
 add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
 add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
@@ -412,9 +336,10 @@ add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
 add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
 add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
 add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {15300495 ns} 1} {{Cursor 4} {4919381 ns} 1} {{Cursor 5} {4934568 ns} 0}
-quietly wave cursor active 5
+WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1}
+quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
 configure wave -justifyvalue left
@@ -429,4 +354,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {4934554 ns} {4934778 ns}
+WaveRestoreZoom {165196205 ns} {165196487 ns}
diff --git a/sim/regression-wally b/sim/regression-wally
index fa112731a..1569abd77 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -85,7 +85,7 @@ for test in tests64i:
   configs.append(tc)
 
 tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
-tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a",  "wally32priv", "wally32periph"]  
+tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a",  "wally32priv", "wally32periph"]  
 for test in tests32gc:
   tc = TestCase(
         name=test,
@@ -132,15 +132,13 @@ for test in ahbTests:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", 
+tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", 
              "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
-#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
     tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", 
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
-                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
-                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
+                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs"]
     if (fp):
        tests64gc.append("arch64f")
        tests64gc.append("arch64d")
diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh
index 00e9845cf..fd265cb9e 100755
--- a/sim/run-imperas-linux.sh
+++ b/sim/run-imperas-linux.sh
@@ -4,6 +4,7 @@
 
 export IMPERAS_TOOLS=$(pwd)/imperas.ic
 export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
-export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" 
+#export OTHERFLAGS="+TRACE2LOG_ENABLE=1  +TRACE2LOG_AFTER=10500000"
+export OTHERFLAGS=""
 
 vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"
diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch
index 4cb03792e..073553e52 100755
--- a/sim/sim-testfloat-batch
+++ b/sim/sim-testfloat-batch
@@ -10,6 +10,4 @@
 # sqrt   - test square root
 # all    - test everything
 
-# nowave for 2nd argument supresses wlf files
-
-vsim -c -do "do testfloat.do rv64fpquad $1 $2"
\ No newline at end of file
+vsim -c -do "do testfloat.do rv64fpquad $1"
\ No newline at end of file
diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch
index 46c35c75c..f2c2a3c30 100755
--- a/sim/sim-wally-batch
+++ b/sim/sim-wally-batch
@@ -1 +1 @@
-vsim -c -do "do wally-batch.do rv32gc wally32priv"
+vsim -c -do "do wally-batch.do rv64gc wally64priv"
diff --git a/sim/testfloat.do b/sim/testfloat.do
index b2fb2e1dc..85bd6dfc5 100644
--- a/sim/testfloat.do
+++ b/sim/testfloat.do
@@ -25,14 +25,18 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 # $num = the added words after the call
-vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
-vsim -voptargs=+acc work.testbenchfp -G TEST=$2
+# Change TEST_SIZE to only test certain FP width
+# values are QP, DP, SP, HP
+vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" 
 
-# Determine if nowave argument is provided
-#   this removes any output to a wlf or wave window to reduce
-#   disk space.
-if {($argc > 2) && ($3 eq "nowave")} {
+# Set WAV variable to avoid having any output to wave (to limit disk space)
+quietly set WAV 1;
+
+# Determine if nowave argument is provided this removes any output to
+# a wlf or wave window to reduce disk space.
+if {$WAV eq 0} {
     puts "No wave output is selected"
 } else {
     puts "wave output is selected"
diff --git a/sim/verilate b/sim/verilate
new file mode 100755
index 000000000..9555322f9
--- /dev/null
+++ b/sim/verilate
@@ -0,0 +1,22 @@
+#!/bin/bash
+# simulate with Verilator
+
+export PATH=$PATH:/usr/local/bin/
+verilator=`which verilator`
+
+basepath=$(dirname $0)/..
+#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
+for config in  rv64gc; do
+    echo "$config simulating..."
+    if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+        echo "Exiting after $config lint due to errors or warnings"
+        exit 1
+    fi
+done
+echo "All lints run with no errors or warnings"
+
+# --lint-only just runs lint rather than trying to compile and simulate
+# -I points to the include directory where files such as `include wally-config.vh  are found
+
+# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
+# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
diff --git a/sim/wally-batch.do b/sim/wally-batch.do
index df49518c1..29d31bd25 100644
--- a/sim/wally-batch.do
+++ b/sim/wally-batch.do
@@ -59,7 +59,7 @@ if {$argc >= 3} {
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32imc rv32imc
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
-    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     if { $coverage } {
         echo "wally-batch buildroot coverage"
@@ -88,7 +88,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     exec ./slack-notifier/slack-notifier.py
 
 } elseif {$2 eq "ahb"} {
-    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
     vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
@@ -112,7 +112,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     # **** fix this so we can pass any number of +defines.
     # only allows 3 right now
 
-    vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
+    vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
     vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt
@@ -126,7 +126,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     # power off -r /dut/core/*
 
 } else {
-    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
+    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
     if {$coverage} {
diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do
index 567ef6b1d..2309b01df 100644
--- a/sim/wally-imperas-cov.do
+++ b/sim/wally-imperas-cov.do
@@ -29,20 +29,21 @@ vlog +incdir+../config/$1 \
      +define+USE_IMPERAS_DV \
      +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
      \
      +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
        +define+COVER_RV64I \
        +define+COVER_RV64C \
        +define+COVER_RV64M \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
-     \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
+    \
+    ../src/cvw.sv \
      ../testbench/testbench_imperas.sv \
      ../testbench/common/*.sv   \
      ../src/*/*.sv \
diff --git a/sim/wally-imperas-no-idv.do b/sim/wally-imperas-no-idv.do
index 6050211bf..47d8bf07b 100644
--- a/sim/wally-imperas-no-idv.do
+++ b/sim/wally-imperas-no-idv.do
@@ -26,7 +26,8 @@ vlib work
         # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
 vlog +incdir+../config/$1 \
      +incdir+../config/shared \
-     ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \
+     ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \
+     ../src/cvw.sv \
      ../testbench/testbench_imperas.sv \
      ../testbench/common/*.sv   \
      ../src/*/*.sv \
diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do
index 14634c612..7f0b060e2 100644
--- a/sim/wally-imperas.do
+++ b/sim/wally-imperas.do
@@ -30,13 +30,14 @@ vlog +incdir+../config/$1 \
      +define+USE_IMPERAS_DV \
      +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
+     ../src/cvw.sv \
      ../testbench/testbench_imperas.sv \
      ../testbench/common/*.sv   \
      ../src/*/*.sv \
diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do
index a95dc51a3..fcf6ceec4 100644
--- a/sim/wally-linux-imperas.do
+++ b/sim/wally-linux-imperas.do
@@ -33,9 +33,9 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
+    vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation
@@ -53,13 +53,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
       +incdir+../config/shared \
       +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
       +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
-      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
+      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
+      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
+      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
+      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
+      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
+      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
+      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
+      ../src/cvw.sv \
        ../testbench/testbench-linux-imperas.sv \
        ../testbench/common/*.sv ../src/*/*.sv \
        ../src/*/*/*.sv -suppress 2583
@@ -93,7 +94,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } elseif {$2 eq "fpga"} {
     echo "hello"
-    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
+    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
     vsim workopt +nowarn3829  -fatal 7
     
@@ -103,10 +104,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } else {
     if {$2 eq "ahb"} {
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+        vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
     } else {
         # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
+        vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
     }
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
diff --git a/sim/wally.do b/sim/wally.do
index 9b9fc30fc..bc987e3d3 100644
--- a/sim/wally.do
+++ b/sim/wally.do
@@ -33,7 +33,7 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
@@ -47,7 +47,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     exec ./slack-notifier/slack-notifier.py
     
 } elseif {$2 eq "buildroot-no-trace"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
@@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } elseif {$2 eq "fpga"} {
     echo "hello"
-    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
+    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
     vsim workopt +nowarn3829  -fatal 7
     
@@ -78,10 +78,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } else {
     if {$2 eq "ahb"} {
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+        vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
     } else {
         # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
+        vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 
     }
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
diff --git a/sim/wally.xrun b/sim/wally.xrun
new file mode 100644
index 000000000..67b3cdd5f
--- /dev/null
+++ b/sim/wally.xrun
@@ -0,0 +1,6 @@
+xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
+xrun -elaborate -top testbench ../testbench/testbench-xcelium.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench
+
+
+xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -top testbench -defparam testbench.TEST=arch64i
+
diff --git a/sim/wave-fpu.do b/sim/wave-fpu.do
index 05ccb2154..08b6b3378 100644
--- a/sim/wave-fpu.do
+++ b/sim/wave-fpu.do
@@ -7,8 +7,15 @@ add wave -noupdate /testbenchfp/Y
 add wave -noupdate /testbenchfp/Z
 add wave -noupdate /testbenchfp/Res
 add wave -noupdate /testbenchfp/Ans
+add wave -noupdate /testbenchfp/reset
 add wave -noupdate /testbenchfp/DivStart
 add wave -noupdate /testbenchfp/FDivBusyE
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/DivDone
+add wave -noupdate /testbenchfp/ResMatch
+add wave -noupdate /testbenchfp/FlagMatch
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/NaNGood
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
diff --git a/sim/wave.do b/sim/wave.do
index 5aa5deb0a..73aaf02d8 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -6,47 +6,42 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/core/SATP_REGW
-add wave -noupdate /testbench/FunctionName/FunctionName/PCD
-add wave -noupdate /testbench/FunctionName/FunctionName/PCE
-add wave -noupdate /testbench/FunctionName/FunctionName/PCF
-add wave -noupdate /testbench/FunctionName/FunctionName/PCM
-add wave -noupdate /testbench/FunctionName/FunctionName/PCM_temp
-add wave -noupdate /testbench/FunctionName/FunctionName/PCMOld
 add wave -noupdate /testbench/dut/core/InstrValidM
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -79,29 +74,30 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
@@ -120,8 +116,8 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/BALUControl
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
@@ -152,28 +148,30 @@ add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/ebufsmarb/CurrState
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
-add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUReq
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
+add wave -noupdate -group AHB -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/HRDATA
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
@@ -190,17 +188,17 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
 add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
 add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
 add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
 add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
@@ -210,12 +208,12 @@ add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/d
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
 add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
 add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
 add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
@@ -235,7 +233,7 @@ add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
@@ -252,60 +250,59 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
@@ -323,14 +320,7 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
-add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
 add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
 add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
 add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
@@ -362,22 +352,27 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMASt
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
+add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
 add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
 add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -396,18 +391,6 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/un
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
 add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
@@ -462,16 +445,17 @@ add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
 add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
-add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
+add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
 add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
@@ -483,54 +467,38 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
@@ -553,31 +521,31 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
-add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
-add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
-add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
+add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
+add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
+add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
@@ -609,34 +577,38 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
 add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
 add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
-add wave -noupdate /testbench/clk
-add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
-add wave -noupdate /testbench/HPMCSample/EndSample
-add wave -noupdate /testbench/HPMCSample/StartSample
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
+add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW
+add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {23 ns} 0} {{Cursor 5} {394987 ns} 1}
-quietly wave cursor active 4
+WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1}
+quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
 configure wave -justifyvalue left
@@ -651,4 +623,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {52 ns}
+WaveRestoreZoom {6124 ns} {6284 ns}
diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index c5ad8e1fa..1275d0cbc 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -27,9 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+module cache import cvw::*; #(parameter cvw_t P,
+                              parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
   input  logic                   clk,
   input  logic                   reset,
   input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@@ -40,7 +39,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   input  logic                   FlushCache,        // Flush all dirty lines back to memory
   input  logic                   InvalidateCache,   // Clear all valid bits
   input  logic [11:0]            NextSet,           // Virtual address, but we only use the lower 12 bits.
-  input  logic [`PA_BITS-1:0]    PAdr,              // Physical address
+  input  logic [PA_BITS-1:0]     PAdr,              // Physical address
   input  logic [(WORDLEN-1)/8:0] ByteMask,          // Which bytes to write (D$ only)
   input  logic [WORDLEN-1:0]     CacheWriteData,    // Data to write to cache (D$ only)
   output logic                   CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
@@ -57,7 +56,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   input  logic [LOGBWPL-1:0]     BeatCount,         // Beat in burst
   input  logic [LINELEN-1:0]     FetchBuffer,       // Buffer long enough to hold entire cache line arriving from bus
   output logic [1:0]             CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
-  output logic [`PA_BITS-1:0]    CacheBusAdr        // Address for bus access
+  output logic [PA_BITS-1:0]     CacheBusAdr        // Address for bus access
 );
 
   // Cache parameters
@@ -65,7 +64,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   localparam                     OFFSETLEN = $clog2(LINEBYTELEN);    // Number of bits in offset field
   localparam                     SETLEN = $clog2(NUMLINES);          // Number of set bits
   localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
-  localparam                     TAGLEN = `PA_BITS - SETTOP;         // Number of tag bits
+  localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
   localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
   localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
   localparam                     FLUSHADRTHRESHOLD = NUMLINES - 1;   // Used to determine when flush is complete
@@ -114,7 +113,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     AdrSelMuxSel, CacheSet);
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
+  cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
     .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
@@ -152,7 +151,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
   
   // Bus address for fetch, writeback, or flush writeback
-  mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
+  mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
     .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
     .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
     .s({SelFlush, SelWriteback}), .y(CacheBusAdr));
@@ -184,6 +183,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
       assign LineWriteData = FetchBuffer;
       assign LineByteMask = '1;
     end
+  
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
   /////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 0a1a07cab..5fb00dc90 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cacheLRU
   #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
   input  logic                clk, 
@@ -104,8 +102,7 @@ module cacheLRU
     if (node == NUMWAYS-2) begin
       assign LRUUpdate[lchild] = ~WayEncoded[r];
       assign LRUUpdate[rchild] = WayEncoded[r];
-    end
-    else begin
+    end else begin
       assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
       assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
     end
@@ -113,7 +110,7 @@ module cacheLRU
 
   // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
   assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2];
-  mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
+  if (NUMWAYS > 2) mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
 
   // Compute next victim way.
   for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 34f1778f5..58aa9b477 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   input  logic       clk,
   input  logic       reset,
@@ -94,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;
 
   // outputs for the performance counters.
-  assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
+  assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
+                                     (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
   assign CacheMiss = CacheAccess & ~CacheHit;
 
   // special case on reset. When the fsm first exists reset the
@@ -159,7 +158,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   assign SelFlush = (CurrState == STATE_READY & FlushCache) |
           (CurrState == STATE_FLUSH) | 
           (CurrState == STATE_FLUSH_WRITEBACK);
-  // coverage off -item e -fecexprrow 1
+  // coverage off -item e 1 -fecexprrow 1
   // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck)
   assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
              (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 368c7b587..4438ea2c7 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -27,16 +27,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
+module cacheway import cvw::*; #(parameter cvw_t P, 
+                  parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
                   OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
   input  logic                        clk,
   input  logic                        reset,
   input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [$clog2(NUMLINES)-1:0] CacheSet,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
-  input  logic [`PA_BITS-1:0]         PAdr,           // Physical address 
+  input  logic [PA_BITS-1:0]          PAdr,           // Physical address 
   input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
   input  logic                        SetDirty,       // Set the dirty bit in the selected way and set
@@ -54,11 +53,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   output logic                        DirtyWay,       // This way is dirty
   output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
-  localparam                          WORDSPERLINE = LINELEN/`XLEN;
+  localparam                          WORDSPERLINE = LINELEN/XLEN;
   localparam                          BYTESPERLINE = LINELEN/8;
   localparam                          LOGWPL = $clog2(WORDSPERLINE);
-  localparam                          LOGXLENBYTES = $clog2(`XLEN/8);
-  localparam                          BYTESPERWORD = `XLEN/8;
+  localparam                          LOGXLENBYTES = $clog2(XLEN/8);
+  localparam                          BYTESPERWORD = XLEN/8;
 
   logic [NUMLINES-1:0]                ValidBits;
   logic [NUMLINES-1:0]                DirtyBits;
@@ -82,10 +81,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
     mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
 
     // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
+    // coverage off -item e 1 -fecexprrow 3
+    // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
     assign FlushWayEn = FlushWay & SelFlush;
     assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
-  end
-  else begin:flushlogic // no flush operation for read-only caches.
+  end else begin:flushlogic // no flush operation for read-only caches.
     assign SelTag = VictimWay;
     assign SelNonHit = SetValid;
   end
@@ -100,7 +100,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   assign SetDirtyWay = SetDirty & SelData;                                 // exclusion-tag: icache SetDirtyWay
   assign ClearDirtyWay = ClearDirty & SelData;
   assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;  // exclusion-tag: icache SelectedWiteWordEn
-  assign SetValidEN = SetValidWay & ~FlushStage;                           // exclusion-tag: icache SetValidEN
+  assign SetValidEN = SetValidWay & ~FlushStage;                           // exclusion-tag: cache SetValidEN
 
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
@@ -109,14 +109,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   // Tag Array
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
+  ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
     .addr(CacheSet), .dout(ReadTag),
-    .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
+    .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
 
   // AND portion of distributed tag multiplexer
   assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
   assign DirtyWay = SelTag & Dirty & ValidWay;
-  assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
+  assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Data Array
@@ -124,20 +124,19 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
 
   genvar               words;
 
-  localparam           SRAMLEN = 128;
+  localparam           SRAMLEN = 128;             // *** make this a global parameter
   localparam           NUMSRAM = LINELEN/SRAMLEN;
   localparam           SRAMLENINBYTES = SRAMLEN/8;
   localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     if (!READ_ONLY_CACHE) begin:wordram
-      ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
+      ram1p1rwbe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
-    end
-    else begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
+    end else begin:wordram // no byte-enable needed for i$.
+      ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn));
@@ -154,8 +153,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   always_ff @(posedge clk) begin // Valid bit array, 
     if (reset) ValidBits        <= #1 '0;
     if(CacheEn) begin 
-    ValidWay <= #1 ValidBits[CacheSet];
-    if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
+      ValidWay <= #1 ValidBits[CacheSet];
+      if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
       else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay;
     end
   end
@@ -175,8 +174,4 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
       end
     end
   end else assign Dirty = 1'b0;
-
-
 endmodule
-
-
diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
index ea305fb6c..db80cfc83 100644
--- a/src/cache/subcachelineread.sv
+++ b/src/cache/subcachelineread.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module subcachelineread #(parameter LINELEN, WORDLEN, 
   parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
@@ -43,9 +41,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
   logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0]   ReadDataLinePad;
   logic [WORDLEN-1:0]                         ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
 
-  if (PADLEN > 0) begin
-    assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
-  end else assign ReadDataLinePad = ReadDataLine;
+  if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
+  else            assign ReadDataLinePad = ReadDataLine;
 
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
diff --git a/src/cvw.sv b/src/cvw.sv
new file mode 100644
index 000000000..e2c81b4e2
--- /dev/null
+++ b/src/cvw.sv
@@ -0,0 +1,272 @@
+//////////////////////////////////////////
+// cvw.sv
+//
+// Written: David_Harris@hmc.edu 27 January 2022
+//
+// Purpose: package with shared CORE-V-Wally global parameters
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// Usiing global `define statements isn't ideal in a large SystemVerilog system because
+// of the risk of `define name conflicts across different subsystems.
+// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
+// that is referenced by all Wally modules but not by other subsystems.
+
+`ifndef CVW_T
+
+`define CVW_T 1
+
+package cvw;
+
+  `include "BranchPredictorType.vh"
+
+typedef struct packed {
+  logic         FPGA;     // Modifications to tare
+  logic         QEMU;     // Hacks to agree with QEMU during Linux boot
+  int           XLEN;     // Machine width (32 or 64)
+  logic         IEEE754;  // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
+  int           MISA;     // Machine Instruction Set Architecture
+  int           AHBW;     // AHB bus width (usually = XLEN)
+
+  // RISC-V Features
+  logic         ZICSR_SUPPORTED;
+  logic         ZIFENCEI_SUPPORTED;
+  logic [11:0]  COUNTERS;
+  logic         ZICNTR_SUPPORTED;
+  logic         ZIHPM_SUPPORTED;
+  logic         ZFH_SUPPORTED;
+  logic         SSTC_SUPPORTED;
+  logic         VIRTMEM_SUPPORTED;
+  logic         VECTORED_INTERRUPTS_SUPPORTED;
+  logic         BIGENDIAN_SUPPORTED;
+  logic         SVADU_SUPPORTED;
+  logic         ZMMUL_SUPPORTED;
+  logic         ZICBOM_SUPPORTED;
+  logic         ZICBOZ_SUPPORTED;
+  logic         ZICBOP_SUPPORTED;
+  logic         SVPBMT_SUPPORTED;
+  logic         SVINVAL_SUPPORTED;
+
+  // Microarchitectural Features
+  logic         BUS_SUPPORTED;
+  logic         DCACHE_SUPPORTED;
+  logic         ICACHE_SUPPORTED;
+
+// TLB configuration.  Entries should be a power of 2
+  int           ITLB_ENTRIES;
+  int           DTLB_ENTRIES;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
+  int           DCACHE_NUMWAYS;
+  int           DCACHE_WAYSIZEINBYTES;
+  int           DCACHE_LINELENINBITS;
+  int           ICACHE_NUMWAYS;
+  int           ICACHE_WAYSIZEINBYTES;
+  int           ICACHE_LINELENINBITS;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+  int           IDIV_BITSPERCYCLE;
+  logic         IDIV_ON_FPU;
+
+// Legal number of PMP entries are 0, 16, or 64
+  int           PMP_ENTRIES;
+
+// Address space
+  logic [63:0]  RESET_VECTOR;
+
+// WFI Timeout Wait
+  int           WFI_TIMEOUT_BIT;
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+  logic         DTIM_SUPPORTED;
+  logic [63:0]  DTIM_BASE;
+  logic [63:0]  DTIM_RANGE;
+  logic         IROM_SUPPORTED;
+  logic [63:0]  IROM_BASE;
+  logic [63:0]  IROM_RANGE;
+  logic         BOOTROM_SUPPORTED;
+  logic [63:0]  BOOTROM_BASE;
+  logic [63:0]  BOOTROM_RANGE;
+  logic         UNCORE_RAM_SUPPORTED;
+  logic [63:0]  UNCORE_RAM_BASE;
+  logic [63:0]  UNCORE_RAM_RANGE;
+  logic         EXT_MEM_SUPPORTED;
+  logic [63:0]  EXT_MEM_BASE;
+  logic [63:0]  EXT_MEM_RANGE;
+  logic         CLINT_SUPPORTED;
+  logic [63:0]  CLINT_BASE;
+  logic [63:0]  CLINT_RANGE;
+  logic         GPIO_SUPPORTED;
+  logic [63:0]  GPIO_BASE;
+  logic [63:0]  GPIO_RANGE;
+  logic         UART_SUPPORTED;
+  logic [63:0]  UART_BASE;
+  logic [63:0]  UART_RANGE;
+  logic         PLIC_SUPPORTED;
+  logic [63:0]  PLIC_BASE;
+  logic [63:0]  PLIC_RANGE;
+  logic         SDC_SUPPORTED;
+  logic [63:0]  SDC_BASE;
+  logic [63:0]  SDC_RANGE;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+  logic         GPIO_LOOPBACK_TEST;
+
+// Hardware configuration
+  int           UART_PRESCALE ;
+
+// Interrupt configuration
+  int           PLIC_NUM_SRC;
+  logic         PLIC_NUM_SRC_LT_32;
+  int           PLIC_GPIO_ID;
+  int           PLIC_UART_ID;
+
+  logic                BPRED_SUPPORTED;
+  BranchPredictorType  BPRED_TYPE;
+  int                  BPRED_NUM_LHR;
+  int                  BPRED_SIZE;
+  int                  BTB_SIZE;
+
+// FPU division architecture
+  int           RADIX;
+  int           DIVCOPIES;
+
+// bit manipulation
+  logic         ZBA_SUPPORTED;
+  logic         ZBB_SUPPORTED;
+  logic         ZBC_SUPPORTED;
+  logic         ZBS_SUPPORTED;
+
+// Memory synthesis configuration
+  logic         USE_SRAM;
+
+// constants defining different privilege modes
+// defined in Table 1.1 of the privileged spec
+  logic [1:0] M_MODE ;
+  logic [1:0] S_MODE ;
+  logic [1:0] U_MODE ;
+
+// Virtual Memory Constants
+  int VPN_SEGMENT_BITS;
+  int VPN_BITS;
+  int PPN_BITS;
+  int PA_BITS;
+  int SVMODE_BITS;
+  int ASID_BASE;
+  int ASID_BITS;
+
+// constants to check SATP_MODE against
+// defined in Table 4.3 of the privileged spec
+  logic [3:0] NO_TRANSLATE;
+  logic [3:0] SV32; 
+  logic [3:0] SV39;
+  logic [3:0] SV48;
+
+// macros to define supported modes
+  logic A_SUPPORTED;
+  logic B_SUPPORTED;
+  logic C_SUPPORTED;
+  logic D_SUPPORTED;
+  logic E_SUPPORTED;
+  logic F_SUPPORTED;
+  logic I_SUPPORTED;
+  logic M_SUPPORTED;
+  logic Q_SUPPORTED;
+  logic S_SUPPORTED;
+  logic U_SUPPORTED;
+  
+// logarithm of XLEN, used for number of index bits to select
+  int LOG_XLEN;
+
+// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+  int PMPCFG_ENTRIES;
+
+// Floating point constants for Quad, Double, Single, and Half precisions
+  int         Q_LEN;
+  int         Q_NE;
+  int         Q_NF;
+  int         Q_BIAS;
+  logic [1:0] Q_FMT;
+  int         D_LEN;
+  int         D_NE;
+  int         D_NF;
+  int         D_BIAS;
+  logic [1:0] D_FMT;
+  int         S_LEN;
+  int         S_NE;
+  int         S_NF;
+  int         S_BIAS;
+  logic [1:0] S_FMT;
+  int         H_LEN;
+  int         H_NE;
+  int         H_NF;
+  int         H_BIAS;
+  logic [1:0] H_FMT;
+
+// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
+  int FLEN;
+  int         NE  ;
+  int         NF  ;
+  logic [1:0] FMT ;
+  int         BIAS;
+
+// Floating point constants needed for FPU paramerterization
+  int         FPSIZES;
+  int         FMTBITS;
+  int         LEN1 ;
+  int         NE1  ;
+  int         NF1  ;
+  logic [1:0] FMT1 ;
+  int         BIAS1;
+  int         LEN2 ;
+  int         NE2  ;
+  int         NF2  ;
+  logic [1:0] FMT2 ;
+  int         BIAS2;
+
+// largest length in IEU/FPU
+  int CVTLEN;
+  int LLEN;
+  int LOGCVTLEN;
+  int NORMSHIFTSZ;
+  int LOGNORMSHIFTSZ;
+  int CORRSHIFTSZ;
+
+// division constants
+  int DIVN       ;
+  int LOGR       ;
+  int RK         ;
+  int LOGRK      ;
+  int FPDUR      ;
+  int DURLEN     ;
+  int DIVb       ;
+  int DIVBLEN    ;
+  int DIVa       ;
+
+} cvw_t;
+
+endpackage
+
+`endif
diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
index 38b1e6879..9c2ff3a89 100644
--- a/src/ebu/ahbcacheinterface.sv
+++ b/src/ebu/ahbcacheinterface.sv
@@ -27,9 +27,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ahbcacheinterface #(
+  parameter AHBW,
+  parameter LLEN,
+  parameter PA_BITS,
   parameter BEATSPERLINE,  // Number of AHBW words (beats) in cacheline
   parameter AHBWLOGBWPL,   // Log2 of ^
   parameter LINELEN,       // Number of bits in cacheline
@@ -44,14 +45,14 @@ module ahbcacheinterface #(
   output logic [2:0]          HSIZE,                   // AHB transaction width
   output logic [2:0]          HBURST,                  // AHB burst length
   // bus interface buses
-  input  logic [`AHBW-1:0]    HRDATA,                  // AHB read data
-  output logic [`PA_BITS-1:0] HADDR,                   // AHB address
-  output logic [`AHBW-1:0]    HWDATA,                  // AHB write data
-  output logic [`AHBW/8-1:0]  HWSTRB,                  // AHB byte mask
+  input  logic [AHBW-1:0]     HRDATA,                  // AHB read data
+  output logic [PA_BITS-1:0]  HADDR,                   // AHB address
+  output logic [AHBW-1:0]     HWDATA,                  // AHB write data
+  output logic [AHBW/8-1:0]   HWSTRB,                  // AHB byte mask
   
   // cache interface
-  input  logic [`PA_BITS-1:0] CacheBusAdr,            // Address of cache line
-  input  logic [`LLEN-1:0]    CacheReadDataWordM,     // One word of cache line during a writeback
+  input  logic [PA_BITS-1:0]  CacheBusAdr,            // Address of cache line
+  input  logic [LLEN-1:0]     CacheReadDataWordM,     // One word of cache line during a writeback
   input  logic                CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
   input  logic                Cacheable,              // Memory operation is cachable
   input  logic [1:0]          CacheBusRW,             // Cache bus operation, 01: writeback, 10: fetch
@@ -61,8 +62,8 @@ module ahbcacheinterface #(
   output logic                SelBusBeat,             // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
 
   // uncached interface 
-  input logic [`PA_BITS-1:0]  PAdr,                    // Physical address of uncached memory operation
-  input logic [`LLEN-1:0]     WriteDataM,              // IEU write data for uncached store
+  input logic [PA_BITS-1:0]   PAdr,                    // Physical address of uncached memory operation
+  input logic [LLEN-1:0]      WriteDataM,              // IEU write data for uncached store
   input logic [1:0]           BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
   input logic [2:0]           Funct3,                  // Size of uncached memory operation
 
@@ -74,11 +75,11 @@ module ahbcacheinterface #(
   
 
   localparam                  BeatCountThreshold = BEATSPERLINE - 1;  // Largest beat index
-  logic [`PA_BITS-1:0]        LocalHADDR;                             // Address after selecting between cached and uncached operation
+  logic [PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
   logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
   logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
-  logic [`AHBW/8-1:0]         BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
-  logic [`AHBW-1:0]           PreHWDATA;                              // AHB Address phase write data
+  logic [AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
+  logic [AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
 
   genvar                      index;
 
@@ -86,35 +87,35 @@ module ahbcacheinterface #(
   for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
     logic [BEATSPERLINE-1:0] CaptureBeat;
     assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
-    flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
-      .q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
+    flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
+      .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW]));
   end
 
-  mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
-  assign HADDR = ({{`PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
+  mux2 #(PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
+  assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR;
 
-  mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
+  mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
 
   // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
-  logic [`AHBW-1:0]          CacheReadDataWordAHB;
+  logic [AHBW-1:0]          CacheReadDataWordAHB;
   if(LLENPOVERAHBW > 1) begin
-    logic [`AHBW-1:0]          AHBWordSets [(LLENPOVERAHBW)-1:0];
+    logic [AHBW-1:0]          AHBWordSets [(LLENPOVERAHBW)-1:0];
     genvar                     index;
     for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
-        assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
+        assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)];
     end
     assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
-  end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];      
+  end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0];      
   
-  mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
+  mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]),
     .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
-  flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
+  flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
 
   // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
   // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
-  swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
+  swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
   
-  flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
+  flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);
   
   buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
     .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
index 1a9308dd4..9a65a5cda 100644
--- a/src/ebu/ahbinterface.sv
+++ b/src/ebu/ahbinterface.sv
@@ -27,9 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ahbinterface #(
+  parameter XLEN,
   parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
 )( 
   input  logic                          HCLK, HRESETn,
@@ -37,30 +36,30 @@ module ahbinterface #(
   input  logic                          HREADY,       // AHB peripheral ready
   output logic [1:0]                    HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                          HWRITE,       // AHB 0: Read operation 1: Write operation 
-  input  logic [`XLEN-1:0]              HRDATA,       // AHB read data
-  output logic [`XLEN-1:0]              HWDATA,       // AHB write data
-  output logic [`XLEN/8-1:0]            HWSTRB,       // AHB byte mask
+  input  logic [XLEN-1:0]               HRDATA,       // AHB read data
+  output logic [XLEN-1:0]               HWDATA,       // AHB write data
+  output logic [XLEN/8-1:0]             HWSTRB,       // AHB byte mask
   
   // lsu/ifu interface
   input  logic                          Stall,        // Core pipeline is stalled
   input  logic                          Flush,        // Pipeline stage flush. Prevents bus transaction from starting
   input  logic [1:0]                    BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input  logic [`XLEN/8-1:0]            ByteMask,     // Bytes enables within a word
-  input  logic [`XLEN-1:0]              WriteData,    // IEU write data for a store
+  input  logic [XLEN/8-1:0]             ByteMask,     // Bytes enables within a word
+  input  logic [XLEN-1:0]               WriteData,    // IEU write data for a store
   output logic                          BusStall,     // Bus is busy with an in flight memory operation
   output logic                          BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-  output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus
+  output logic [(LSU ? XLEN : 32)-1:0]  FetchBuffer   // Register to hold HRDATA after arriving from the bus
 );
   
   logic                                 CaptureEn;
-  localparam                            LEN = (LSU ? `XLEN : 32);   // 32 bits for IFU, XLEN for LSU
+  localparam                            LEN = (LSU ? XLEN : 32);   // 32 bits for IFU, XLEN for LSU
   
   flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
 
   if(LSU) begin
     // delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN    
-    flop #(`XLEN)   wdreg(HCLK, WriteData, HWDATA); 
-    flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
+    flop #(XLEN)   wdreg(HCLK, WriteData, HWDATA); 
+    flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
   end else begin
     assign HWDATA = '0;
     assign HWSTRB = '0;
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index 7456cac8b..c286b1bb9 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -27,7 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 `define BURST_EN 1         // Enables burst mode.  Disable to show the lost performance.
 
 // HCLK and clk must be the same clock!
diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
index de1dd7583..108cd546d 100644
--- a/src/ebu/busfsm.sv
+++ b/src/ebu/busfsm.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // HCLK and clk must be the same clock!
 module busfsm (
   input  logic       HCLK,
diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv
index 6e3c27d3b..60df9e44b 100644
--- a/src/ebu/controllerinput.sv
+++ b/src/ebu/controllerinput.sv
@@ -31,9 +31,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module controllerinput #(
+  parameter PA_BITS, 
   parameter SAVE_ENABLED = 1           // 1: Save manager inputs if Save = 1, 0: Don't save inputs
 )(
   input  logic                HCLK, 
@@ -47,14 +46,14 @@ module controllerinput #(
   input  logic                HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
   input  logic [2:0]          HSIZEIn,   // Manager input. AHB transaction width
   input  logic [2:0]          HBURSTIn,  // Manager input. AHB burst length
-  input  logic [`PA_BITS-1:0] HADDRIn,   // Manager input. AHB address
+  input  logic [PA_BITS-1:0]  HADDRIn,   // Manager input. AHB address
   output logic                HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
   // controller output
   output logic [1:0]          HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation 
   output logic [2:0]          HSIZEOut,  // Arbitrated manager transaction. AHB transaction width
   output logic [2:0]          HBURSTOut, // Arbitrated manager transaction. AHB burst length 
-  output logic [`PA_BITS-1:0] HADDROut,  // Arbitrated manager transaction. AHB address
+  output logic [PA_BITS-1:0]  HADDROut,  // Arbitrated manager transaction. AHB address
   input  logic                HREADYIn   // Peripheral ready
 );
 
@@ -62,13 +61,13 @@ module controllerinput #(
   logic [2:0]                 HSIZESave;
   logic [2:0]                 HBURSTSave;
   logic [1:0]                 HTRANSSave;
-  logic [`PA_BITS-1:0]        HADDRSave;
+  logic [PA_BITS-1:0]         HADDRSave;
 
   if (SAVE_ENABLED) begin
-    flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
+    flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
       {HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
-    mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
+    mux2 #(1+3+3+2+PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
       Restore,
       {HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
@@ -84,6 +83,3 @@ module controllerinput #(
   assign HREADYOut = HREADYIn & ~Disable;
 
 endmodule
-  
-  
-   
diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv
index 8dddff35a..39975aa4b 100644
--- a/src/ebu/ebu.sv
+++ b/src/ebu/ebu.sv
@@ -31,33 +31,31 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module ebu (
+module ebu #(parameter XLEN, PA_BITS, AHBW)(
   input  logic                clk, reset,
   // Signals from IFU
   input  logic [1:0]          IFUHTRANS, // IFU AHB transaction request
   input  logic [2:0]          IFUHSIZE,  // IFU AHB transaction size
   input  logic [2:0]          IFUHBURST, // IFU AHB burst length
-  input  logic [`PA_BITS-1:0] IFUHADDR,  // IFU AHB address
+  input  logic [PA_BITS-1:0]  IFUHADDR,  // IFU AHB address
   output logic                IFUHREADY, // AHB peripheral ready gated by possible non-grant
   // Signals from LSU
   input  logic [1:0]          LSUHTRANS, // LSU AHB transaction request
   input  logic                LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
   input  logic [2:0]          LSUHSIZE,  // LSU AHB size
   input  logic [2:0]          LSUHBURST, // LSU AHB burst length
-  input  logic [`PA_BITS-1:0] LSUHADDR,  // LSU AHB address
-  input  logic [`XLEN-1:0]    LSUHWDATA, // initially support AHBW = XLEN
-  input  logic [`XLEN/8-1:0]  LSUHWSTRB, // AHB byte mask
+  input  logic [PA_BITS-1:0]  LSUHADDR,  // LSU AHB address
+  input  logic [XLEN-1:0]     LSUHWDATA, // initially support AHBW = XLEN
+  input  logic [XLEN/8-1:0]   LSUHWSTRB, // AHB byte mask
   output logic                LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
 
   // AHB-Lite external signals
   output logic                HCLK, HRESETn, 
   input  logic                HREADY,    // AHB peripheral ready
   input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error
-  output logic [`PA_BITS-1:0] HADDR,     // AHB address to peripheral after arbitration
-  output logic [`AHBW-1:0]    HWDATA,    // AHB Write data after arbitration
-  output logic [`XLEN/8-1:0]  HWSTRB,    // AHB byte write enables after arbitration
+  output logic [PA_BITS-1:0]  HADDR,     // AHB address to peripheral after arbitration
+  output logic [AHBW-1:0]     HWDATA,    // AHB Write data after arbitration
+  output logic [XLEN/8-1:0]   HWSTRB,    // AHB byte write enables after arbitration
   output logic                HWRITE,    // AHB transaction direction after arbitration
   output logic [2:0]          HSIZE,     // AHB transaction size after arbitration
   output logic [2:0]          HBURST,    // AHB burst length after arbitration
@@ -73,13 +71,13 @@ module ebu (
   logic                       IFUDisable;
   logic                       IFUSelect;
 
-  logic [`PA_BITS-1:0]        IFUHADDROut;
+  logic [PA_BITS-1:0]         IFUHADDROut;
   logic [1:0]                 IFUHTRANSOut;
   logic [2:0]                 IFUHBURSTOut;
   logic [2:0]                 IFUHSIZEOut;
   logic                       IFUHWRITEOut;
   
-  logic [`PA_BITS-1:0]        LSUHADDROut;
+  logic [PA_BITS-1:0]         LSUHADDROut;
   logic [1:0]                 LSUHTRANSOut;
   logic [2:0]                 LSUHBURSTOut;
   logic [2:0]                 LSUHSIZEOut;
@@ -98,14 +96,14 @@ module ebu (
   // input stages and muxing for IFU and LSU
   ////////////////////////////////////////////////////////////////////////////////////////////////////
 
-  controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
+  controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
     .Request(IFUReq),
     .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
     .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
     .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
 
   // LSU always has priority so there should never be a need to save and restore the address phase inputs.
-  controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
+  controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
     .Request(LSUReq),
     .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
     .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv
index a61a3961f..91fa9e491 100644
--- a/src/ebu/ebufsmarb.sv
+++ b/src/ebu/ebufsmarb.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ebufsmarb (
   input  logic       HCLK,
   input  logic       HRESETn,
diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv
index af159878f..1a8f0fc19 100644
--- a/src/fpu/fclassify.sv
+++ b/src/fpu/fclassify.sv
@@ -25,16 +25,15 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module fclassify (
+module fclassify import cvw::*;  #(parameter cvw_t P) (
   input  logic                Xs,         // sign bit
   input  logic                XNaN,       // is NaN
   input  logic                XSNaN,      // is signaling NaN
   input  logic                XSubnorm,   // is Subnormal
   input  logic                XZero,      // is zero
   input  logic                XInf,       // is infinity
-  output logic [`XLEN-1:0]    ClassRes    // classify result
+  output logic [P.XLEN-1:0]   ClassRes    // classify result
 );
 
   logic PInf, PZero, PNorm, PSubnorm;     // is the input a positive infinity/zero/normal/subnormal
@@ -63,6 +62,6 @@ module fclassify (
   //  bit 7 - +Inf
   //  bit 8 - signaling NaN
   //  bit 9 - quiet NaN
-  assign ClassRes = {{`XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
+  assign ClassRes = {{P.XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
 
 endmodule
diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
index 63c234328..9d0d582b5 100755
--- a/src/fpu/fcmp.sv
+++ b/src/fpu/fcmp.sv
@@ -1,4 +1,3 @@
-
 ///////////////////////////////////////////
 // fcmp.sv
 //
@@ -27,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // OpCtrl values
 //    110   min
 //    101   max
@@ -36,25 +33,25 @@
 //    001   less than
 //    011   less than or equal
 
-module fcmp (   
-  input  logic [`FMTBITS-1:0]   Fmt,           // format of fp number
-  input  logic [2:0]            OpCtrl,        // see above table
-  input  logic                  Xs, Ys,        // input signs
-  input  logic [`NE-1:0]        Xe, Ye,        // input exponents
-  input  logic [`NF:0]          Xm, Ym,        // input mantissa
-  input  logic                  XZero, YZero,  // is zero
-  input  logic                  XNaN, YNaN,    // is NaN
-  input  logic                  XSNaN, YSNaN,  // is signaling NaN
-  input  logic [`FLEN-1:0]      X, Y,          // original inputs (before unpacker)
-  output logic                  CmpNV,         // invalid flag
-  output logic [`FLEN-1:0]      CmpFpRes,      // compare floating-point result
-  output logic [`XLEN-1:0]      CmpIntRes      // compare integer result
+module fcmp import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0]   Fmt,           // format of fp number
+  input  logic [2:0]             OpCtrl,        // see above table
+  input  logic                   Xs, Ys,        // input signs
+  input  logic [P.NE-1:0]        Xe, Ye,        // input exponents
+  input  logic [P.NF:0]          Xm, Ym,        // input mantissa
+  input  logic                   XZero, YZero,  // is zero
+  input  logic                   XNaN, YNaN,    // is NaN
+  input  logic                   XSNaN, YSNaN,  // is signaling NaN
+  input  logic [P.FLEN-1:0]      X, Y,          // original inputs (before unpacker)
+  output logic                   CmpNV,         // invalid flag
+  output logic [P.FLEN-1:0]      CmpFpRes,      // compare floating-point result
+  output logic [P.XLEN-1:0]      CmpIntRes      // compare integer result
 );
 
-  logic LTabs, LT, EQ;         // is X < or > or = Y
-  logic [`FLEN-1:0] NaNRes;    // NaN result
-  logic BothZero;              // are both inputs zero
-  logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
+  logic LTabs, LT, EQ;          // is X < or > or = Y
+  logic [P.FLEN-1:0] NaNRes;    // NaN result
+  logic BothZero;               // are both inputs zero
+  logic EitherNaN, EitherSNaN;  // are either input a (signaling) NaN
   
   assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
   assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
@@ -64,7 +61,6 @@ module fcmp (
   assign EitherNaN = XNaN|YNaN;
   assign EitherSNaN = XSNaN|YSNaN;
 
-
   // flags
   //    Min/Max - if an input is a signaling NaN set invalid flag
   //    LT/LE - signaling - sets invalid if NaN input
@@ -85,47 +81,46 @@ module fcmp (
   // for RISC-V, return the canonical NaN
 
   // select the NaN result
-  if (`FPSIZES == 1)
-    if(`IEEE754) assign NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-    else         assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+  if (P.FPSIZES == 1)
+    if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+    else          assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
 
-  else if (`FPSIZES == 2) 
-    if(`IEEE754) assign NaNRes = Fmt ? {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
-    else         assign NaNRes = Fmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+  else if (P.FPSIZES == 2) 
+    if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
+    else          assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
   
-  else if (`FPSIZES == 3)
+  else if (P.FPSIZES == 3)
     always_comb
           case (Fmt)
-              `FMT:  
-                if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-                else         NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
-              `FMT1:
-                if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
-                else         NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
-              `FMT2:
-                if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, Xs, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
-                else         NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
-              default:        NaNRes = {`FLEN{1'bx}};
+              P.FMT:  
+                if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+                else         NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
+              P.FMT1:
+                if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
+                else         NaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
+              P.FMT2:
+                if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN2{1'b1}}, Xs, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
+                else         NaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
+              default:        NaNRes = {P.FLEN{1'bx}};
           endcase
 
-  else if (`FPSIZES == 4)
+  else if (P.FPSIZES == 4)
     always_comb
           case (Fmt)
               2'h3:  
-                if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-                else         NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+                else         NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
               2'h1:  
-                if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, Xs, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
-                else         NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+                if(P.IEEE754) NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, Xs, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
+                else         NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
               2'h0: 
-                if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, Xs, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
-                else         NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+                if(P.IEEE754) NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, Xs, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
+                else         NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
               2'h2:
-                if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, Xs, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
-                else         NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+                if(P.IEEE754) NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, Xs, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
+                else         NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
           endcase
 
-
   // Min/Max
   //    - outputs the min/max of X and Y
   //    - -0 < 0
@@ -155,6 +150,5 @@ module fcmp (
   //    - -0 = 0
   //    - inf = inf and -inf = -inf
   //    - return 0 if comparison with NaN (unordered)
-  assign CmpIntRes = {(`XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
-  
+  assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
 endmodule
diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index b9584bc9e..bdc61f784 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -25,69 +25,69 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module fctrl (
-  input  logic                clk,
-  input  logic                reset,
+module fctrl import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk,
+  input  logic                 reset,
   // input control signals
-  input  logic                StallE, StallM, StallW,             // stall signals
-  input  logic                FlushE, FlushM, FlushW,             // flush signals
-  input  logic                IntDivE,                            // is inteteger division
-  input  logic [2:0]          FRM_REGW,                           // rounding mode from CSR
-  input  logic [1:0]          STATUS_FS,                          // is FPU enabled?
-  input  logic                FDivBusyE,                          // is the divider busy
-  // intruction                                                   
-  input  logic [31:0]         InstrD,                             // the full instruction
-  input  logic [6:0]          Funct7D,                            // bits 31:25 of instruction - may contain percision
-  input  logic [6:0]          OpD,                                // bits 6:0 of instruction
-  input  logic [4:0]          Rs2D,                               // bits 24:20 of instruction
-  input  logic [2:0]          Funct3D, Funct3E,                   // bits 14:12 of instruction - may contain rounding mode
+  input  logic                 StallE, StallM, StallW,             // stall signals
+  input  logic                 FlushE, FlushM, FlushW,             // flush signals
+  input  logic                 IntDivE,                            // is inteteger division
+  input  logic [2:0]           FRM_REGW,                           // rounding mode from CSR
+  input  logic [1:0]           STATUS_FS,                          // is FPU enabled?
+  input  logic                 FDivBusyE,                          // is the divider busy
+  // instruction                                                   
+  input  logic [31:0]          InstrD,                             // the full instruction
+  input  logic [6:0]           Funct7D,                            // bits 31:25 of instruction - may contain percision
+  input  logic [6:0]           OpD,                                // bits 6:0 of instruction
+  input  logic [4:0]           Rs2D,                               // bits 24:20 of instruction
+  input  logic [2:0]           Funct3D, Funct3E,                   // bits 14:12 of instruction - may contain rounding mode
   // input mux selections                                         
-  output logic                XEnD, YEnD, ZEnD,                   // enable inputs
-  output logic                XEnE, YEnE, ZEnE,                   // enable inputs
+  output logic                 XEnD, YEnD, ZEnD,                   // enable inputs
+  output logic                 XEnE, YEnE, ZEnE,                   // enable inputs
   // opperation mux selections                                    
-  output logic                FCvtIntE, FCvtIntW,                 // convert to integer opperation
-  output logic [2:0]          FrmM,                               // FP rounding mode
-  output logic [`FMTBITS-1:0] FmtE, FmtM,                         // FP format
-  output logic [2:0]          OpCtrlE, OpCtrlM,                   // Select which opperation to do in each component
-  output logic                FpLoadStoreM,                       // FP load or store instruction
-  output logic [1:0]          PostProcSelE, PostProcSelM,         // select result in the post processing unit
-  output logic [1:0]          FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
+  output logic                 FCvtIntE, FCvtIntW,                 // convert to integer opperation
+  output logic [2:0]           FrmM,                               // FP rounding mode
+  output logic [P.FMTBITS-1:0] FmtE, FmtM,                         // FP format
+  output logic [2:0]           OpCtrlE, OpCtrlM,                   // Select which opperation to do in each component
+  output logic                 FpLoadStoreM,                       // FP load or store instruction
+  output logic [1:0]           PostProcSelE, PostProcSelM,         // select result in the post processing unit
+  output logic [1:0]           FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
+  output logic                 FPUActiveE,                         // FP instruction being executed
   // register control signals
-  output logic                FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
-  output logic                FWriteIntE, FWriteIntM,             // Write to integer register
-  output logic [4:0]          Adr1D, Adr2D, Adr3D,                // adresses of each input
-  output logic [4:0]          Adr1E, Adr2E, Adr3E,                // adresses of each input
+  output logic                 FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
+  output logic                 FWriteIntE, FWriteIntM,             // Write to integer register
+  output logic [4:0]           Adr1D, Adr2D, Adr3D,                // adresses of each input
+  output logic [4:0]           Adr1E, Adr2E, Adr3E,                // adresses of each input
   // other control signals
-  output logic                IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
-  output logic                FDivStartE, IDivStartE              // Start division or squareroot
+  output logic                 IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
+  output logic                 FDivStartE, IDivStartE              // Start division or squareroot
   );
 
   `define FCTRLW 12
 
-  logic [`FCTRLW-1:0]         ControlsD;          // control signals
-  logic                       FRegWriteD;         // FP register write enable
-  logic                       FDivStartD;         // start division/sqrt
-  logic                       FWriteIntD;         // integer register write enable
-  logic [2:0]                 OpCtrlD;            // Select which opperation to do in each component
-  logic [1:0]                 PostProcSelD;       // select result in the post processing unit
-  logic [1:0]                 FResSelD;           // Select one of the results that finish in the memory stage
-  logic [2:0]                 FrmD, FrmE;         // FP rounding mode
-  logic [`FMTBITS-1:0]        FmtD;               // FP format
-  logic [1:0]                 Fmt, Fmt2;          // format - before possible reduction
-  logic                       SupportedFmt;       // is the format supported
-  logic                       SupportedFmt2;      // is the source format supported for fp -> fp
-  logic                       FCvtIntD, FCvtIntM; // convert to integer opperation
+  logic [`FCTRLW-1:0]          ControlsD;                          // control signals
+  logic                        FRegWriteD;                         // FP register write enable
+  logic                        FDivStartD;                         // start division/sqrt
+  logic                        FWriteIntD;                         // integer register write enable
+  logic [2:0]                  OpCtrlD;                            // Select which opperation to do in each component
+  logic [1:0]                  PostProcSelD;                       // select result in the post processing unit
+  logic [1:0]                  FResSelD;                           // Select one of the results that finish in the memory stage
+  logic [2:0]                  FrmD, FrmE;                         // FP rounding mode
+  logic [P.FMTBITS-1:0]        FmtD;                               // FP format
+  logic [1:0]                  Fmt, Fmt2;                          // format - before possible reduction
+  logic                        SupportedFmt;                       // is the format supported
+  logic                        SupportedFmt2;                      // is the source format supported for fp -> fp
+  logic                        FCvtIntD, FCvtIntM;                 // convert to integer opperation
 
   // FPU Instruction Decoder
   assign Fmt = Funct7D[1:0];
   assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp
 
-  assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) |
-                         (Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
-  assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & `D_SUPPORTED) |
-                         (Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED));
+  assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) |
+                         (Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED));
+  assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) |
+                         (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED));
 
   // decode the instruction                       
   // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
@@ -98,19 +98,19 @@ module fctrl (
       ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
     else begin 
       ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
-      /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
+      /* verilator lint_off CASEINCOMPLETE */   // default value above has priority so no other default needed
       case(OpD)
         7'b0000111: case(Funct3D)
-                      3'b010:                      ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
-                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
-                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
-                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
+                      3'b010:                       ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
+                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
+                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
+                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
                     endcase
         7'b0100111: case(Funct3D)
-                      3'b010:                      ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
-                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
-                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
-                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
+                      3'b010:                       ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
+                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
+                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
+                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
                     endcase
         7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
         7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
@@ -139,9 +139,9 @@ module fctrl (
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
                                                 ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
                                   else if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register
-                      7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x   to fp reg
+                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w/d/h/q  fp to int register
+                      7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
+                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w/d/h/q.x  int to fp reg
                       7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
                                                 ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
                       7'b0100001: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b01)
@@ -227,14 +227,13 @@ module fctrl (
   //    10 - half
   //    11 - quad
   
-    if (`FPSIZES == 1)
+    if (P.FPSIZES == 1)
       assign FmtD = 0;
-    else if (`FPSIZES == 2)begin
+    else if (P.FPSIZES == 2)begin
       logic [1:0] FmtTmp;
       assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
-      assign FmtD = (`FMT == FmtTmp);
-    end
-    else if (`FPSIZES == 3|`FPSIZES == 4)
+      assign FmtD = (P.FMT == FmtTmp);
+    end else if (P.FPSIZES == 3|P.FPSIZES == 4)
       assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
 
   // Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
@@ -251,12 +250,9 @@ module fctrl (
                   ((FResSelD==2'b11)&(PostProcSelD==2'b00))|                                       // mv float to int 
                   ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
 
-
-
   //    Z - fma ops only
   assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]);                                    // fma, add, sub   
 
-
   //  Final Res Sel:
   //        fp      int
   //  00  other     cmp
@@ -313,19 +309,19 @@ module fctrl (
   assign Adr3D = InstrD[31:27];
  
   // D/E pipleine register
-  flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
-              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD},
-              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE});
+  flopenrc #(14+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ~IllegalFPUInstrD},
+              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, FPUActiveE});
   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
   flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
   flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
 
   // Integer division on FPU divider
-  if (`M_SUPPORTED & `IDIV_ON_FPU) assign IDivStartE = IntDivE;
-  else                             assign IDivStartE = 0; 
+  if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE;
+  else                               assign IDivStartE = 0; 
 
   // E/M pipleine register
-  flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
+  flopenrc #(13+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
               {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE},
               {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM});
   
diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv
index 32ca7542f..86321ae2f 100644
--- a/src/fpu/fcvt.sv
+++ b/src/fpu/fcvt.sv
@@ -1,4 +1,3 @@
-
 ///////////////////////////////////////////
 // fcvt.sv
 //
@@ -27,23 +26,21 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fcvt (
-  input  logic                    Xs,          // input's sign
-  input  logic [`NE-1:0]          Xe,          // input's exponent
-  input  logic [`NF:0]            Xm,          // input's fraction
-  input  logic [`XLEN-1:0]        Int,         // integer input - from IEU
-  input  logic [2:0]              OpCtrl,      // choose which opperation (look below for values)
-  input  logic                    ToInt,       // is fp->int (since it's writting to the integer register)
-  input  logic                    XZero,       // is the input zero
-  input  logic [`FMTBITS-1:0]     Fmt,         // the input's precision (11=quad 01=double 00=single 10=half)
-  output logic [`NE:0]            Ce,          // the calculated expoent
-  output logic [`LOGCVTLEN-1:0]   ShiftAmt,    // how much to shift by
-  output logic                    ResSubnormUf,// does the result underflow or is subnormal
-  output logic                    Cs,          // the result's sign
-  output logic                    IntZero,     // is the integer zero?
-  output logic [`CVTLEN-1:0]      LzcIn        // input to the Leading Zero Counter (priority encoder)
+module fcvt import cvw::*;  #(parameter cvw_t P) (
+  input  logic                    Xs,           // input's sign
+  input  logic [P.NE-1:0]         Xe,           // input's exponent
+  input  logic [P.NF:0]           Xm,           // input's fraction
+  input  logic [P.XLEN-1:0]       Int,          // integer input - from IEU
+  input  logic [2:0]              OpCtrl,       // choose which opperation (look below for values)
+  input  logic                    ToInt,        // is fp->int (since it's writting to the integer register)
+  input  logic                    XZero,        // is the input zero
+  input  logic [P.FMTBITS-1:0]    Fmt,          // the input's precision (11=quad 01=double 00=single 10=half)
+  output logic [P.NE:0]           Ce,           // the calculated expoent
+  output logic [P.LOGCVTLEN-1:0]  ShiftAmt,     // how much to shift by
+  output logic                    ResSubnormUf, // does the result underflow or is subnormal
+  output logic                    Cs,           // the result's sign
+  output logic                    IntZero,      // is the integer zero?
+  output logic [P.CVTLEN-1:0]     LzcIn         // input to the Leading Zero Counter (priority encoder)
   );
 
   // OpCtrls:
@@ -56,17 +53,16 @@ module fcvt (
   //                            bit 2              bit 1                   bit 0
   //      for example: signed long -> single floating point has the OpCode 101
 
-  logic [`FMTBITS-1:0]    OutFmt;     // format of the output
-  logic [`XLEN-1:0]       PosInt;     // the positive integer input
-  logic [`XLEN-1:0]       TrimInt;    // integer trimmed to the correct size
-  logic [`NE-2:0]         NewBias;    // the bias of the final result
-  logic [`NE-1:0]         OldExp;     // the old exponent
-  logic                   Signed;     // is the opperation with a signed integer?
-  logic                   Int64;      // is the integer 64 bits?
-  logic                   IntToFp;    // is the opperation an int->fp conversion?
-  logic [`CVTLEN:0]       LzcInFull;  // input to the Leading Zero Counter (priority encoder)
-  logic [`LOGCVTLEN-1:0]  LeadingZeros; // output from the LZC
-
+  logic [P.FMTBITS-1:0]           OutFmt;       // format of the output
+  logic [P.XLEN-1:0]              PosInt;       // the positive integer input
+  logic [P.XLEN-1:0]              TrimInt;      // integer trimmed to the correct size
+  logic [P.NE-2:0]                NewBias;      // the bias of the final result
+  logic [P.NE-1:0]                OldExp;       // the old exponent
+  logic                           Signed;       // is the opperation with a signed integer?
+  logic                           Int64;        // is the integer 64 bits?
+  logic                           IntToFp;      // is the opperation an int->fp conversion?
+  logic [P.CVTLEN:0]              LzcInFull;    // input to the Leading Zero Counter (priority encoder)
+  logic [P.LOGCVTLEN-1:0]         LeadingZeros; // output from the LZC
 
   // seperate OpCtrl for code readability
   assign Signed =  OpCtrl[0];
@@ -76,12 +72,11 @@ module fcvt (
   // choose the ouptut format depending on the opperation
   //      - fp -> fp: OpCtrl contains the percision of the output
   //      - int -> fp: Fmt contains the percision of the output
-  if (`FPSIZES == 2) 
-      assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == `FMT); 
-  else if (`FPSIZES == 3 | `FPSIZES == 4) 
+  if (P.FPSIZES == 2) 
+      assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == P.FMT); 
+  else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
       assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0]; 
 
-
   ///////////////////////////////////////////////////////////////////////////
   // negation
   ///////////////////////////////////////////////////////////////////////////
@@ -89,7 +84,7 @@ module fcvt (
   // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed)
 
   assign PosInt = Cs ? -Int : Int;
-  assign TrimInt = {{`XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
+  assign TrimInt = {{P.XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
   assign IntZero = ~|TrimInt;
 
   ///////////////////////////////////////////////////////////////////////////
@@ -99,13 +94,13 @@ module fcvt (
   // choose the input to the leading zero counter i.e. priority encoder
   //             int -> fp : | positive integer | 00000... (if needed) | 
   //             fp  -> fp : | fraction         | 00000... (if needed) | 
-  assign LzcInFull = IntToFp ? {TrimInt, {`CVTLEN-`XLEN+1{1'b0}}} :
-                            {Xm, {`CVTLEN-`NF{1'b0}}};
+  assign LzcInFull = IntToFp ? {TrimInt, {P.CVTLEN-P.XLEN+1{1'b0}}} :
+                               {Xm, {P.CVTLEN-P.NF{1'b0}}};
 
   // used as shifter input in postprocessor
-  assign LzcIn = LzcInFull[`CVTLEN-1:0];
+  assign LzcIn = LzcInFull[P.CVTLEN-1:0];
   
-  lzc #(`CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
+  lzc #(P.CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
   
   ///////////////////////////////////////////////////////////////////////////
   // exp calculations
@@ -114,42 +109,41 @@ module fcvt (
   // Select the bias of the output
   //      fp -> int : select 1
   //      ??? -> fp : pick the new bias depending on the output format 
-  if (`FPSIZES == 1) begin
-      assign NewBias = ToInt ? (`NE-1)'(1) : (`NE-1)'(`BIAS); 
+  if (P.FPSIZES == 1) begin
+      assign NewBias = ToInt ? (P.NE-1)'(1) : (P.NE-1)'(P.BIAS); 
 
-  end else if (`FPSIZES == 2) begin
-      logic [`NE-2:0] NewBiasToFp;
-      assign NewBiasToFp = OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
-      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
+  end else if (P.FPSIZES == 2) begin
+      logic [P.NE-2:0] NewBiasToFp;
+      assign NewBiasToFp = OutFmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
+      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
 
-  end else if (`FPSIZES == 3) begin
-      logic [`NE-2:0] NewBiasToFp;
+  end else if (P.FPSIZES == 3) begin
+      logic [P.NE-2:0] NewBiasToFp;
       always_comb
           case (OutFmt)
-              `FMT: NewBiasToFp =  (`NE-1)'(`BIAS);
-              `FMT1: NewBiasToFp = (`NE-1)'(`BIAS1);
-              `FMT2: NewBiasToFp = (`NE-1)'(`BIAS2);
-              default: NewBiasToFp = {`NE-1{1'bx}};
+              P.FMT: NewBiasToFp =  (P.NE-1)'(P.BIAS);
+              P.FMT1: NewBiasToFp = (P.NE-1)'(P.BIAS1);
+              P.FMT2: NewBiasToFp = (P.NE-1)'(P.BIAS2);
+              default: NewBiasToFp = {P.NE-1{1'bx}};
           endcase
-      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
+      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
 
-  end else if (`FPSIZES == 4) begin        
-      logic [`NE-2:0] NewBiasToFp;
+  end else if (P.FPSIZES == 4) begin        
+      logic [P.NE-2:0] NewBiasToFp;
       always_comb
           case (OutFmt)
-              2'h3: NewBiasToFp =  (`NE-1)'(`Q_BIAS);
-              2'h1: NewBiasToFp =  (`NE-1)'(`D_BIAS);
-              2'h0: NewBiasToFp =  (`NE-1)'(`S_BIAS);
-              2'h2: NewBiasToFp =  (`NE-1)'(`H_BIAS);
+              2'h3: NewBiasToFp =  (P.NE-1)'(P.Q_BIAS);
+              2'h1: NewBiasToFp =  (P.NE-1)'(P.D_BIAS);
+              2'h0: NewBiasToFp =  (P.NE-1)'(P.S_BIAS);
+              2'h2: NewBiasToFp =  (P.NE-1)'(P.H_BIAS);
           endcase
-      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
+      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
   end
 
-
   // select the old exponent
   //      int -> fp : largest bias + XLEN-1
   //      fp -> ??? : XExp
-  assign OldExp = IntToFp ? (`NE)'(`BIAS)+(`NE)'(`XLEN-1) : Xe;
+  assign OldExp = IntToFp ? (P.NE)'(P.BIAS)+(P.NE)'(P.XLEN-1) : Xe;
   
   // calculate CalcExp
   //      fp -> fp : 
@@ -159,13 +153,13 @@ module fcvt (
   //              - correct the expoent when there is a normalization shift ( + LeadingZeros+1) 
   //              - the plus 1 is built into the leading zeros by counting the leading zeroes in the mantissa rather than the fraction
   //      fp -> int : XExp - Largest Bias + 1 - (LeadingZeros+1)
-  //          |  `XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
+  //          |  P.XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
   //          process:
   //              - start
-  //                  |  `XLEN  zeros     |     Mantissa      | 0's if nessisary |
+  //                  |  P.XLEN  zeros     |     Mantissa      | 0's if nessisary |
   //
   //              - shift left 1 (1)
-  //                  | `XLEN-1 zeros |bit|     frac      | 0's if nessisary |
+  //                  | P.XLEN-1 zeros |bit|     frac      | 0's if nessisary |
   //                                      . <- binary point
   //
   //              - shift left till unbiased exponent is 0 (XExp - Largest Bias)
@@ -185,14 +179,12 @@ module fcvt (
   //                  - newBias to make the biased exponent
   //
   //          oldexp         - biasold         - LeadingZeros                               + newbias
-  assign Ce = {1'b0, OldExp} - (`NE+1)'(`BIAS) - {{`NE-`LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
-
+  assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
 
   // find if the result is dnormal or underflows
   //      - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
   //      - can't underflow an integer to Fp conversion
-  assign ResSubnormUf = (~|Ce | Ce[`NE])&~XZero&~IntToFp;
-
+  assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
 
   ///////////////////////////////////////////////////////////////////////////
   // shifter
@@ -211,10 +203,9 @@ module fcvt (
   //                  - this is a problem because the input to the lzc was the fraction rather than the mantissa
   //                  - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
   always_comb
-      if(ToInt)                       ShiftAmt = Ce[`LOGCVTLEN-1:0]&{`LOGCVTLEN{~Ce[`NE]}};
-      else if (ResSubnormUf)  ShiftAmt = (`LOGCVTLEN)'(`NF-1)+Ce[`LOGCVTLEN-1:0];
+      if(ToInt)                       ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
+      else if (ResSubnormUf)  ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
       else                            ShiftAmt = LeadingZeros;
-
       
   ///////////////////////////////////////////////////////////////////////////
   // sign
@@ -227,9 +218,7 @@ module fcvt (
   //      - otherwise: the floating point input's sign
   always_comb
       if(IntToFp)
-          if(Int64)   Cs = Int[`XLEN-1]&Signed;
+          if(Int64)   Cs = Int[P.XLEN-1]&Signed;
           else        Cs = Int[31]&Signed;
       else            Cs = Xs;
-
 endmodule
-
diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
index f4d465012..9112da9d1 100644
--- a/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -26,74 +26,72 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrt(
-  input  logic                clk, 
-  input  logic                reset, 
-  input  logic [`FMTBITS-1:0] FmtE,
-  input  logic                XsE,
-  input  logic [`NF:0]        XmE, YmE,
-  input  logic [`NE-1:0]      XeE, YeE,
-  input  logic                XInfE, YInfE, 
-  input  logic                XZeroE, YZeroE, 
-  input  logic                XNaNE, YNaNE, 
-  input  logic                FDivStartE, IDivStartE,
-  input  logic                StallM,
-  input  logic                FlushE,
-  input  logic                SqrtE, SqrtM,
-  input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-  input  logic [2:0]          Funct3E, Funct3M,
-  input  logic                IntDivE, W64E,
-  output logic                DivStickyM,
-  output logic                FDivBusyE, IFDivStartE, FDivDoneE,
-  output logic [`NE+1:0]      QeM,
-  output logic [`DIVb:0]      QmM,
-  output logic [`XLEN-1:0]    FIntDivResultM
+module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk, 
+  input  logic                 reset, 
+  input  logic [P.FMTBITS-1:0] FmtE,
+  input  logic                 XsE,
+  input  logic [P.NF:0]        XmE, YmE,
+  input  logic [P.NE-1:0]      XeE, YeE,
+  input  logic                 XInfE, YInfE, 
+  input  logic                 XZeroE, YZeroE, 
+  input  logic                 XNaNE, YNaNE, 
+  input  logic                 FDivStartE, IDivStartE,
+  input  logic                 StallM,
+  input  logic                 FlushE,
+  input  logic                 SqrtE, SqrtM,
+  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+  input  logic [2:0]           Funct3E, Funct3M,
+  input  logic                 IntDivE, W64E,
+  output logic                 DivStickyM,
+  output logic                 FDivBusyE, IFDivStartE, FDivDoneE,
+  output logic [P.NE+1:0]      QeM,
+  output logic [P.DIVb:0]      QmM,
+  output logic [P.XLEN-1:0]    FIntDivResultM
 );
 
   // Floating-point division and square root module, with optional integer division and remainder
   // Computes X/Y, sqrt(X), A/B, or A%B
 
-  logic [`DIVb+3:0]           WS, WC;                       // Partial remainder components
-  logic [`DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [`DIVb+3:0]           D;                            // Iterator Divisor
-  logic [`DIVb:0]             FirstU, FirstUM;              // Intermediate result values
-  logic [`DIVb+1:0]           FirstC;                       // Step tracker
-  logic                       Firstun;                      // Quotient selection
-  logic                       WZeroE;                       // Early termination flag
-  logic [`DURLEN-1:0]         cycles;                       // FSM cycles
-  logic                       SpecialCaseM;                 // Divide by zero, square root of negative, etc.
-  logic                       DivStartE;                    // Enable signal for flops during stall
+  logic [P.DIVb+3:0]           WS, WC;                       // Partial remainder components
+  logic [P.DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
+  logic [P.DIVb+3:0]           D;                            // Iterator Divisor
+  logic [P.DIVb:0]             FirstU, FirstUM;              // Intermediate result values
+  logic [P.DIVb+1:0]           FirstC;                       // Step tracker
+  logic                        Firstun;                      // Quotient selection
+  logic                        WZeroE;                       // Early termination flag
+  logic [P.DURLEN-1:0]         CyclesE;                      // FSM cycles
+  logic                        SpecialCaseM;                 // Divide by zero, square root of negative, etc.
+  logic                        DivStartE;                    // Enable signal for flops during stall
                                                             
   // Integer div/rem signals                                
-  logic                       BZeroM;                       // Denominator is zero
-  logic                       IntDivM;                      // Integer operation
-  logic [`DIVBLEN:0]          nM, mM;                       // Shift amounts
-  logic                       NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
-  logic [`XLEN-1:0]           AM;                           // Original Numerator for postprocessor
-  logic                       ISpecialCaseE;                // Integer div/remainder special cases
+  logic                        BZeroM;                       // Denominator is zero
+  logic                        IntDivM;                      // Integer operation
+  logic [P.DIVBLEN:0]          nM, mM;                       // Shift amounts
+  logic                        NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
+  logic [P.XLEN-1:0]           AM;                           // Original Numerator for postprocessor
+  logic                        ISpecialCaseE;                // Integer div/remainder special cases
 
-  fdivsqrtpreproc fdivsqrtpreproc(                          // Preprocessor
+  fdivsqrtpreproc #(P) fdivsqrtpreproc(                          // Preprocessor
     .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
-    .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .cycles,
+    .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .CyclesE,
     // Int-specific 
     .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
     .BZeroM, .nM, .mM, .AM, 
     .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
 
-  fdivsqrtfsm fdivsqrtfsm(                                  // FSM
+  fdivsqrtfsm #(P) fdivsqrtfsm(                                  // FSM
     .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
     .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
-    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .cycles,
+    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .CyclesE,
     // Int-specific 
     .IDivStartE, .ISpecialCaseE, .IntDivE);
 
-  fdivsqrtiter fdivsqrtiter(                                // CSA Iterator
+  fdivsqrtiter #(P) fdivsqrtiter(                                // CSA Iterator
     .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
     .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
 
-  fdivsqrtpostproc fdivsqrtpostproc(                        // Postprocessor
+  fdivsqrtpostproc #(P) fdivsqrtpostproc(                        // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
     .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
     .QmM, .WZeroE, .DivStickyM, 
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
index f1ad32cd8..09b17871a 100644
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -1,10 +1,10 @@
 ///////////////////////////////////////////
-// fdivsqrt.sv
+// fdivsqrtcycles.sv
 //
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
 // Modified: 18 April 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Determine number of cycles for divsqrt
 // 
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
@@ -26,51 +26,50 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtcycles(
-  input  logic [`FMTBITS-1:0] FmtE,
-  input  logic                SqrtE,
-  input  logic                IntDivE,
-  input  logic [`DIVBLEN:0]   nE,
-  output logic [`DURLEN-1:0]  cycles
+module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0] FmtE,
+  input  logic                 SqrtE,
+  input  logic                 IntDivE,
+  input  logic [P.DIVBLEN:0]   nE,
+  output logic [P.DURLEN-1:0]  CyclesE
 );
-  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
-  // DIVN = `NF+3
+  logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits
+  // DIVN = P.NF+3
   // NS = NF + 1
   // N = NS or NS+2 for div/sqrt.
 
   /* verilator lint_off WIDTH */
-  if (`FPSIZES == 1)
-    assign Nf = `NF;
-  else if (`FPSIZES == 2)
+  if (P.FPSIZES == 1)
+    assign Nf = P.NF;
+  else if (P.FPSIZES == 2)
     always_comb
       case (FmtE)
-        1'b0: Nf = `NF1;
-        1'b1: Nf = `NF;
+        1'b0: Nf = P.NF1;
+        1'b1: Nf = P.NF;
       endcase
-  else if (`FPSIZES == 3)
+  else if (P.FPSIZES == 3)
     always_comb
       case (FmtE)
-        `FMT:  Nf = `NF;
-        `FMT1: Nf = `NF1;
-        `FMT2: Nf = `NF2; 
+        P.FMT:   Nf = P.NF;
+        P.FMT1:  Nf = P.NF1;
+        P.FMT2:  Nf = P.NF2; 
+        default: Nf = 'x; // shouldn't happen
       endcase
-  else if (`FPSIZES == 4)  
+  else if (P.FPSIZES == 4)  
     always_comb
       case(FmtE)
-        `S_FMT: Nf = `S_NF;
-        `D_FMT: Nf = `D_NF;
-        `H_FMT: Nf = `H_NF;
-        `Q_FMT: Nf = `Q_NF;
+        P.S_FMT: Nf = P.S_NF;
+        P.D_FMT: Nf = P.D_NF;
+        P.H_FMT: Nf = P.H_NF;
+        P.Q_FMT: Nf = P.Q_NF;
       endcase 
 
   always_comb begin 
     if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
-    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
-    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    else       fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
+    if (P.IDIV_ON_FPU) CyclesE =  IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
+    else              CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
   end 
   /* verilator lint_on WIDTH */
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
index aa8ae051d..5531276df 100644
--- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
@@ -26,49 +26,47 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtexpcalc(
-  input  logic [`FMTBITS-1:0] Fmt,
-  input  logic [`NE-1:0]      Xe, Ye,
-  input  logic                Sqrt,
-  input  logic                XZero, 
-  input  logic [`DIVBLEN:0]   ell, m,
-  output logic [`NE+1:0]      Qe
+module fdivsqrtexpcalc import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0] Fmt,
+  input  logic [P.NE-1:0]      Xe, Ye,
+  input  logic                 Sqrt,
+  input  logic                 XZero, 
+  input  logic [P.DIVBLEN:0]   ell, m,
+  output logic [P.NE+1:0]      Qe
   );
-  logic [`NE-2:0] Bias;
-  logic [`NE+1:0] SXExp;
-  logic [`NE+1:0] SExp;
-  logic [`NE+1:0] DExp;
+  logic [P.NE-2:0] Bias;
+  logic [P.NE+1:0] SXExp;
+  logic [P.NE+1:0] SExp;
+  logic [P.NE+1:0] DExp;
   
-  if (`FPSIZES == 1) begin
-    assign Bias = (`NE-1)'(`BIAS); 
+  if (P.FPSIZES == 1) begin
+    assign Bias = (P.NE-1)'(P.BIAS); 
 
-  end else if (`FPSIZES == 2) begin
-    assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
+  end else if (P.FPSIZES == 2) begin
+    assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
 
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
     always_comb
       case (Fmt)
-        `FMT: Bias  =  (`NE-1)'(`BIAS);
-        `FMT1: Bias = (`NE-1)'(`BIAS1);
-        `FMT2: Bias = (`NE-1)'(`BIAS2);
+        P.FMT: Bias  =  (P.NE-1)'(P.BIAS);
+        P.FMT1: Bias = (P.NE-1)'(P.BIAS1);
+        P.FMT2: Bias = (P.NE-1)'(P.BIAS2);
         default: Bias = 'x;
       endcase
 
-  end else if (`FPSIZES == 4) begin        
+  end else if (P.FPSIZES == 4) begin        
   always_comb
     case (Fmt)
-      2'h3: Bias =  (`NE-1)'(`Q_BIAS);
-      2'h1: Bias =  (`NE-1)'(`D_BIAS);
-      2'h0: Bias =  (`NE-1)'(`S_BIAS);
-      2'h2: Bias =  (`NE-1)'(`H_BIAS);
+      2'h3: Bias =  (P.NE-1)'(P.Q_BIAS);
+      2'h1: Bias =  (P.NE-1)'(P.D_BIAS);
+      2'h0: Bias =  (P.NE-1)'(P.S_BIAS);
+      2'h2: Bias =  (P.NE-1)'(P.H_BIAS);
     endcase
   end
-  assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
-  assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
+  assign SXExp = {2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - (P.NE+2)'(P.BIAS);
+  assign SExp  = {SXExp[P.NE+1], SXExp[P.NE+1:1]} + {2'b0, Bias};
   
   // correct exponent for subnormal input's normalization shifts
-  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}); 
+  assign DExp  = ({2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(P.NE+1-P.DIVBLEN){1'b0}}, m} + {3'b0, Bias}); 
   assign Qe = Sqrt ? SExp : DExp;
 endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
index 250fb4fbd..990e3f19f 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
@@ -26,21 +26,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtfgen2 (
-  input  logic             up, uz,
-  input  logic [`DIVb+3:0] C, U, UM,
-  output logic [`DIVb+3:0] F
+module fdivsqrtfgen2 import cvw::*;  #(parameter cvw_t P) (
+  input  logic              up, uz,
+  input  logic [P.DIVb+3:0] C, U, UM,
+  output logic [P.DIVb+3:0] F
 );
-  logic [`DIVb+3:0] FP, FN, FZ;
+  logic [P.DIVb+3:0]        FP, FN, FZ;
 
   // Generate for both positive and negative bits
   assign FP = ~(U << 1) & C;
   assign FN = (UM << 1) | (C & ~(C << 2));
   assign FZ = '0;
 
-
   always_comb     // Choose which adder input will be used
     if (up)       F = FP;
     else if (uz)  F = FZ;
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index a07e504f4..fc648f5bd 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -26,14 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtfgen4 (
-  input  logic [3:0]       udigit,
-  input  logic [`DIVb+3:0] C, U, UM,
-  output logic [`DIVb+3:0] F
+module fdivsqrtfgen4 import cvw::*;  #(parameter cvw_t P) (
+  input  logic [3:0]        udigit,
+  input  logic [P.DIVb+3:0] C, U, UM,
+  output logic [P.DIVb+3:0] F
 );
-  logic [`DIVb+3:0] F2, F1, F0, FN1, FN2;
+  logic [P.DIVb+3:0]        F2, F1, F0, FN1, FN2;
   
   // Generate for both positive and negative bits
   assign F2  = (~U << 2) & (C << 2);
@@ -49,4 +47,4 @@ module fdivsqrtfgen4 (
     else if (udigit[1])  F = FN1;
     else if (udigit[0])  F = FN2;
     else                 F = F0;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 5332087ad..0e2cba90e 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -26,39 +26,37 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtfsm(
-  input  logic               clk, reset, 
-  input  logic               XInfE, YInfE, 
-  input  logic               XZeroE, YZeroE, 
-  input  logic               XNaNE, YNaNE, 
-  input  logic               FDivStartE, IDivStartE,
-  input  logic               XsE, WZeroE,
-  input  logic               SqrtE,
-  input  logic               StallM, FlushE,
-  input  logic               IntDivE,
-  input  logic               ISpecialCaseE,
-  input  logic [`DURLEN-1:0] cycles,
-  output logic               IFDivStartE,
-  output logic               FDivBusyE, FDivDoneE,
-  output logic               SpecialCaseM
+module fdivsqrtfsm import cvw::*;  #(parameter cvw_t P) (
+  input  logic                clk, reset, 
+  input  logic                XInfE, YInfE, 
+  input  logic                XZeroE, YZeroE, 
+  input  logic                XNaNE, YNaNE, 
+  input  logic                FDivStartE, IDivStartE,
+  input  logic                XsE, WZeroE,
+  input  logic                SqrtE,
+  input  logic                StallM, FlushE,
+  input  logic                IntDivE,
+  input  logic                ISpecialCaseE,
+  input  logic [P.DURLEN-1:0] CyclesE,
+  output logic                IFDivStartE,
+  output logic                FDivBusyE, FDivDoneE,
+  output logic                SpecialCaseM
 );
   
   typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
   statetype state;
 
   logic SpecialCaseE, FSpecialCaseE;
-  logic [`DURLEN-1:0] step;
+  logic [P.DURLEN-1:0] step;
 
   // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
-  assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
+  assign IFDivStartE = (FDivStartE | (IDivStartE & P.IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
   assign FDivDoneE = (state == DONE);
   assign FDivBusyE = (state == BUSY) | IFDivStartE; 
  
   // terminate immediately on special cases
-  assign FSpecialCaseE = XZeroE | | XInfE  | XNaNE |  (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
-  if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
+  assign FSpecialCaseE = XZeroE | XInfE  | XNaNE |  (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
+  if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
   else              assign SpecialCaseE = FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
 
@@ -66,8 +64,7 @@ module fdivsqrtfsm(
       if (reset | FlushE) begin
           state <= #1 IDLE; 
       end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
-//       end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
-          step <= cycles; 
+          step <= CyclesE; 
           if (SpecialCaseE) state <= #1 DONE;
           else              state <= #1 BUSY;
       end else if (state == BUSY) begin 
@@ -79,4 +76,4 @@ module fdivsqrtfsm(
       end 
   end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
index aeb4bcc4d..1d40e8d9a 100644
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -26,38 +26,36 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtiter(
-  input  logic             clk,
-  input  logic             IFDivStartE, 
-  input  logic             FDivBusyE, 
-  input  logic             SqrtE,
-  input  logic [`DIVb+3:0] X, D,
-  output logic [`DIVb:0]   FirstU, FirstUM,
-  output logic [`DIVb+1:0] FirstC,
-  output logic             Firstun,
-  output logic [`DIVb+3:0] FirstWS, FirstWC
+module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk,
+  input  logic              IFDivStartE, 
+  input  logic              FDivBusyE, 
+  input  logic              SqrtE,
+  input  logic [P.DIVb+3:0] X, D,
+  output logic [P.DIVb:0]   FirstU, FirstUM,
+  output logic [P.DIVb+1:0] FirstC,
+  output logic              Firstun,
+  output logic [P.DIVb+3:0] FirstWS, FirstWC
 );
 
   /* verilator lint_off UNOPTFLAT */
-  logic [`DIVb+3:0]      WSNext[`DIVCOPIES-1:0]; // Q4.b
-  logic [`DIVb+3:0]      WCNext[`DIVCOPIES-1:0]; // Q4.b
-  logic [`DIVb+3:0]      WS[`DIVCOPIES:0];       // Q4.b
-  logic [`DIVb+3:0]      WC[`DIVCOPIES:0];       // Q4.b
-  logic [`DIVb:0]        U[`DIVCOPIES:0];        // U1.b
-  logic [`DIVb:0]        UM[`DIVCOPIES:0];       // U1.b
-  logic [`DIVb:0]        UNext[`DIVCOPIES-1:0];  // U1.b
-  logic [`DIVb:0]        UMNext[`DIVCOPIES-1:0]; // U1.b
-  logic [`DIVb+1:0]      C[`DIVCOPIES:0];        // Q2.b
-  logic [`DIVb+1:0]      initC;                  // Q2.b
-  logic [`DIVCOPIES-1:0] un; 
+  logic [P.DIVb+3:0]      WSNext[P.DIVCOPIES-1:0]; // Q4.b
+  logic [P.DIVb+3:0]      WCNext[P.DIVCOPIES-1:0]; // Q4.b
+  logic [P.DIVb+3:0]      WS[P.DIVCOPIES:0];       // Q4.b
+  logic [P.DIVb+3:0]      WC[P.DIVCOPIES:0];       // Q4.b
+  logic [P.DIVb:0]        U[P.DIVCOPIES:0];        // U1.b
+  logic [P.DIVb:0]        UM[P.DIVCOPIES:0];       // U1.b
+  logic [P.DIVb:0]        UNext[P.DIVCOPIES-1:0];  // U1.b
+  logic [P.DIVb:0]        UMNext[P.DIVCOPIES-1:0]; // U1.b
+  logic [P.DIVb+1:0]      C[P.DIVCOPIES:0];        // Q2.b
+  logic [P.DIVb+1:0]      initC;                   // Q2.b
+  logic [P.DIVCOPIES-1:0] un; 
 
-  logic [`DIVb+3:0]      WSN, WCN;               // Q4.b
-  logic [`DIVb+3:0]      DBar, D2, DBar2;        // Q4.b
-  logic [`DIVb+1:0]      NextC;
-  logic [`DIVb:0]        UMux, UMMux;
-  logic [`DIVb:0]        initU, initUM;
+  logic [P.DIVb+3:0]      WSN, WCN;                // Q4.b
+  logic [P.DIVb+3:0]      DBar, D2, DBar2;         // Q4.b
+  logic [P.DIVb+1:0]      NextC;
+  logic [P.DIVb:0]        UMux, UMMux;
+  logic [P.DIVb:0]        initU, initUM;
   /* verilator lint_on UNOPTFLAT */
 
   // Top Muxes and Registers
@@ -65,37 +63,37 @@ module fdivsqrtiter(
   // Otherwise, the divisor is retained and the residual and result
   // are fed back for the next iteration.
  
-  // Residual WS/SC registers/initializaiton mux
-  mux2   #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, IFDivStartE, WSN);
-  mux2   #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, IFDivStartE, WCN);
-  flopen #(`DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
-  flopen #(`DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
+  // Residual WS/SC registers/initialization mux
+  mux2   #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
+  mux2   #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
+  flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
+  flopen #(P.DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
 
   // UOTFC Result U and UM registers/initialization mux
   // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
-  assign initU  = {SqrtE, {(`DIVb){1'b0}}};
-  assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
-  mux2   #(`DIVb+1)  Umux(UNext[`DIVCOPIES-1],  initU,  IFDivStartE, UMux);
-  mux2   #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
-  flopen #(`DIVb+1)  UReg(clk, FDivBusyE, UMux,  U[0]);
-  flopen #(`DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
+  assign initU  = {SqrtE, {(P.DIVb){1'b0}}};
+  assign initUM = {~SqrtE, {(P.DIVb){1'b0}}};
+  mux2   #(P.DIVb+1)  Umux(UNext[P.DIVCOPIES-1],  initU,  IFDivStartE, UMux);
+  mux2   #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
+  flopen #(P.DIVb+1)  UReg(clk, FDivBusyE, UMux,  U[0]);
+  flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
 
   // C register/initialization mux
   // Initialize C to -1 for sqrt and -R for division
   logic [1:0] initCUpper;
-  if(`RADIX == 4) begin
+  if(P.RADIX == 4) begin
     mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
   end else begin
     mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
   end
   
-  assign initC = {initCUpper, {`DIVb{1'b0}}};
-  mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
-  flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
+  assign initC = {initCUpper, {P.DIVb{1'b0}}};
+  mux2   #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC); 
+  flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
 
   // Divisor Selections
   assign DBar    = ~D;        // for -D
-  if(`RADIX == 4) begin : d2
+  if(P.RADIX == 4) begin : d2
     assign D2    = D << 1;    // for 2D,  only used in R4
     assign DBar2 = ~D2;       // for -2D, only used in R4
   end
@@ -103,15 +101,15 @@ module fdivsqrtiter(
   // k=DIVCOPIES of the recurrence logic
   genvar i;
   generate
-    for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
-      if (`RADIX == 2) begin: stage
-        fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE,
+    for(i=0; $unsigned(i)<P.DIVCOPIES; i++) begin : iterations
+      if (P.RADIX == 2) begin: stage
+        fdivsqrtstage2 #(P) fdivsqrtstage(.D, .DBar, .SqrtE,
         .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
         .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
       end else begin: stage
         logic j1;
-        assign j1 = (i == 0 & ~C[0][`DIVb-1]);
-        fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
+        assign j1 = (i == 0 & ~C[0][P.DIVb-1]);
+        fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
         .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), 
         .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
       end
diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 1009cd227..19856e932 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -26,51 +26,49 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtpostproc(
-  input  logic              clk, reset,
-  input  logic              StallM,
-  input  logic [`DIVb+3:0]  WS, WC,
-  input  logic [`DIVb+3:0]  D, 
-  input  logic [`DIVb:0]    FirstU, FirstUM, 
-  input  logic [`DIVb+1:0]  FirstC,
-  input  logic              SqrtE,
-  input  logic              Firstun, SqrtM, SpecialCaseM, NegQuotM,
-  input  logic [`XLEN-1:0]  AM,
-  input  logic              RemOpM, ALTBM, BZeroM, AsM, W64M,
-  input  logic [`DIVBLEN:0] nM, mM,
-  output logic [`DIVb:0]    QmM, 
-  output logic              WZeroE,
-  output logic              DivStickyM,
-  output logic [`XLEN-1:0]  FIntDivResultM
+module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
+  input  logic               clk, reset,
+  input  logic               StallM,
+  input  logic [P.DIVb+3:0]  WS, WC,
+  input  logic [P.DIVb+3:0]  D, 
+  input  logic [P.DIVb:0]    FirstU, FirstUM, 
+  input  logic [P.DIVb+1:0]  FirstC,
+  input  logic               SqrtE,
+  input  logic               Firstun, SqrtM, SpecialCaseM, NegQuotM,
+  input  logic [P.XLEN-1:0]  AM,
+  input  logic               RemOpM, ALTBM, BZeroM, AsM, W64M,
+  input  logic [P.DIVBLEN:0] nM, mM,
+  output logic [P.DIVb:0]    QmM, 
+  output logic               WZeroE,
+  output logic               DivStickyM,
+  output logic [P.XLEN-1:0]  FIntDivResultM
 );
   
-  logic [`DIVb+3:0]         W, Sum;
-  logic [`DIVb:0]           PreQmM;
-  logic                     NegStickyM;
-  logic                     weq0E, WZeroM;
-  logic [`XLEN-1:0]         IntDivResultM;
+  logic [P.DIVb+3:0]         W, Sum;
+  logic [P.DIVb:0]           PreQmM;
+  logic                      NegStickyM;
+  logic                      weq0E, WZeroM;
+  logic [P.XLEN-1:0]         IntDivResultM;
 
   //////////////////////////
   // Execute Stage: Detect early termination for an exact result
   //////////////////////////
 
   // check for early termination on an exact result. 
-  aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0E);
+  aplusbeq0 #(P.DIVb+4) wspluswceq0(WS, WC, weq0E);
 
-  if (`RADIX == 2) begin: R2EarlyTerm
-    logic [`DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
-    logic [`DIVb+2:0] FirstK;
+  if (P.RADIX == 2) begin: R2EarlyTerm
+    logic [P.DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
+    logic [P.DIVb+2:0] FirstK;
     logic wfeq0E;
-    logic [`DIVb+3:0] WCF, WSF;
+    logic [P.DIVb+3:0] WCF, WSF;
 
     assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
-    assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
+    assign FZeroSqrtE = {FirstUM[P.DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
     assign FZeroDivE =  D << 1;                                    // F for divide
-    mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
-    csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
-    aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
+    mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
+    csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
+    aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
     assign WZeroE = weq0E|(wfeq0E & Firstun);
   end else begin
     assign WZeroE = weq0E;
@@ -91,27 +89,27 @@ module fdivsqrtpostproc(
 
   // Determine if sticky bit is negative  // *** look for ways to optimize this.  Shift shouldn't be needed.
   assign Sum = WC + WS;
-  assign NegStickyM = Sum[`DIVb+3];
-  mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
-  mux2 #(`DIVb+1)    qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
+  assign NegStickyM = Sum[P.DIVb+3];
+  mux2 #(P.DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
+  mux2 #(P.DIVb+1)    qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
 
   // Integer quotient or remainder correctoin, normalization, and special cases
-  if (`IDIV_ON_FPU) begin:intpostproc // Int supported
-    logic [`DIVBLEN:0] NormShiftM;
-    logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
-    logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
+  if (P.IDIV_ON_FPU) begin:intpostproc // Int supported
+    logic [P.DIVBLEN:0] NormShiftM;
+    logic [P.DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
+    logic signed [P.DIVb+3:0] PreResultM, PreIntResultM;
 
-    assign W = $signed(Sum) >>> `LOGR;
+    assign W = $signed(Sum) >>> P.LOGR;
     assign UnsignedQuotM = {3'b000, PreQmM};
 
     // Integer remainder: sticky and sign correction muxes
-    mux2 #(`DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
-    mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
-    mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
+    mux2 #(P.DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
+    mux2 #(P.DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
+    mux2 #(P.DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
 
     // Select quotient or remainder and do normalization shift
-    mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
-    mux2 #(`DIVb+4)    presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
+    mux2 #(P.DIVBLEN+1) normshiftmux(((P.DIVBLEN+1)'(P.DIVb) - (nM * (P.DIVBLEN+1)'(P.LOGR))), (mM + (P.DIVBLEN+1)'(P.DIVa)), RemOpM, NormShiftM);
+    mux2 #(P.DIVb+4)    presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
     assign PreIntResultM = $signed(PreResultM >>> NormShiftM); 
 
     // special case logic
@@ -119,18 +117,18 @@ module fdivsqrtpostproc(
     always_comb
       if (BZeroM) begin         // Divide by zero
         if (RemOpM) IntDivResultM = AM;  
-        else        IntDivResultM = {(`XLEN){1'b1}};
+        else        IntDivResultM = {(P.XLEN){1'b1}};
      end else if (ALTBM) begin // Numerator is zero
         if (RemOpM) IntDivResultM = AM;
         else        IntDivResultM = '0;
-     end else       IntDivResultM = PreIntResultM[`XLEN-1:0];
+     end else       IntDivResultM = PreIntResultM[P.XLEN-1:0];
 
     // sign extend result for W64
-    if (`XLEN==64) begin
-      mux2 #(64) resmux(IntDivResultM[`XLEN-1:0], 
-        {{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
+    if (P.XLEN==64) begin
+      mux2 #(64) resmux(IntDivResultM[P.XLEN-1:0], 
+        {{(P.XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
         W64M, FIntDivResultM);
     end else 
-      assign FIntDivResultM = IntDivResultM[`XLEN-1:0];
+      assign FIntDivResultM = IntDivResultM[P.XLEN-1:0];
   end
 endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 43a5e42b2..ef14bda78 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -26,157 +26,183 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtpreproc (
-  input  logic                clk,
-  input  logic                IFDivStartE, 
-  input  logic [`NF:0]        Xm, Ym,
-  input  logic [`NE-1:0]      Xe, Ye,
-  input  logic [`FMTBITS-1:0] FmtE,
-  input  logic                SqrtE,
-  input  logic                XZeroE,
-  input  logic [2:0]          Funct3E,
-  output logic [`NE+1:0]      QeM,
-  output logic [`DIVb+3:0]    X, D,
+module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk,
+  input  logic                 IFDivStartE, 
+  input  logic [P.NF:0]        Xm, Ym,
+  input  logic [P.NE-1:0]      Xe, Ye,
+  input  logic [P.FMTBITS-1:0] FmtE,
+  input  logic                 SqrtE,
+  input  logic                 XZeroE,
+  input  logic [2:0]           Funct3E,
+  output logic [P.NE+1:0]      QeM,
+  output logic [P.DIVb+3:0]    X, D,
   // Int-specific
-  input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-  input  logic                IntDivE, W64E,
-  output logic                ISpecialCaseE,
-  output logic [`DURLEN-1:0]  cycles,
-  output logic [`DIVBLEN:0]   nM, mM,
-  output logic                NegQuotM, ALTBM, IntDivM, W64M,
-  output logic                AsM, BZeroM,
-  output logic [`XLEN-1:0]    AM
+  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+  input  logic                 IntDivE, W64E,
+  output logic                 ISpecialCaseE,
+  output logic [P.DURLEN-1:0]  CyclesE,
+  output logic [P.DIVBLEN:0]   nM, mM,
+  output logic                 NegQuotM, ALTBM, IntDivM, W64M,
+  output logic                 AsM, BZeroM,
+  output logic [P.XLEN-1:0]    AM
 );
 
-  logic [`DIVb-1:0]           XPreproc, DPreproc;
-  logic [`DIVb:0]             PreSqrtX;
-  logic [`DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
-  logic [`NE+1:0]             QeE;                                 // Quotient Exponent (FP only)
-  logic [`DIVb-1:0]           IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
-  logic [`DIVBLEN:0]          mE, nE, ell;                             // Leading zeros of inputs
-  logic                       NumerZeroE;                          // Numerator is zero (X or A)
-  logic                       AZeroE, BZeroE;                      // A or B is Zero for integer division
-  logic                       signedDiv;                           // signed division
-  logic                       NegQuotE;                            // Integer quotient is negative
-  logic                       AsE, BsE;                            // Signs of integer inputs
-  logic [`XLEN-1:0]           AE;                                  // input A after W64 adjustment
+  logic [P.DIVb-1:0]           Xfract, Dfract;
+  logic [P.DIVb:0]             PreSqrtX;
+  logic [P.DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
+  logic [P.NE+1:0]             QeE;                                 // Quotient Exponent (FP only)
+  logic [P.DIVb-1:0]           IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
+  logic [P.DIVBLEN:0]          mE, nE, ell;                         // Leading zeros of inputs
+  logic                        NumerZeroE;                          // Numerator is zero (X or A)
+  logic                        AZeroE, BZeroE;                      // A or B is Zero for integer division
+  logic                        SignedDivE;                          // signed division
+  logic                        NegQuotE;                            // Integer quotient is negative
+  logic                        AsE, BsE;                            // Signs of integer inputs
+  logic [P.XLEN-1:0]           AE;                                  // input A after W64 adjustment
+  logic  ALTBE;
 
-  if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
-    logic [`XLEN-1:0] BE, PosA, PosB;
+  //////////////////////////////////////////////////////
+  // Integer Preprocessing
+  //////////////////////////////////////////////////////
+
+  if (P.IDIV_ON_FPU) begin:intpreproc // Int Supported
+    logic [P.XLEN-1:0] BE, PosA, PosB;
 
     // Extract inputs, signs, zero, depending on W64 mode if applicable
-    assign signedDiv = ~Funct3E[0];
+    assign SignedDivE = ~Funct3E[0];
   
     // Source handling
-    if (`XLEN==64) begin // 64-bit, supports W64
-      mux2 #(64)    amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE);
-      mux2 #(64)    bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & signedDiv}}, ForwardedSrcBE[31:0]}, W64E, BE);
+    if (P.XLEN==64) begin // 64-bit, supports W64
+      mux2 #(64)    amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & SignedDivE}}, ForwardedSrcAE[31:0]}, W64E, AE);
+      mux2 #(64)    bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & SignedDivE}}, ForwardedSrcBE[31:0]}, W64E, BE);
     end else begin // 32 bits only
       assign AE = ForwardedSrcAE;
       assign BE = ForwardedSrcBE;
      end
     assign AZeroE = ~(|AE);
     assign BZeroE = ~(|BE);
-    assign AsE = AE[`XLEN-1] & signedDiv;
-    assign BsE = BE[`XLEN-1] & signedDiv; 
+    assign AsE = AE[P.XLEN-1] & SignedDivE;
+    assign BsE = BE[P.XLEN-1] & SignedDivE; 
     assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative
 
     // Force integer inputs to be postiive
-    mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
-    mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
+    mux2 #(P.XLEN) posamux(AE, -AE, AsE, PosA);
+    mux2 #(P.XLEN) posbmux(BE, -BE, BsE, PosB);
 
     // Select integer or floating point inputs
-    mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFX);
-    mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFD);
-
-
+    mux2 #(P.DIVb) ifxmux({Xm, {(P.DIVb-P.NF-1){1'b0}}}, {PosA, {(P.DIVb-P.XLEN){1'b0}}}, IntDivE, IFX);
+    mux2 #(P.DIVb) ifdmux({Ym, {(P.DIVb-P.NF-1){1'b0}}}, {PosB, {(P.DIVb-P.XLEN){1'b0}}}, IntDivE, IFD);
+    mux2 #(1)    numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
   end else begin // Int not supported
-    assign IFX = {Xm, {(`DIVb-`NF-1){1'b0}}};
-    assign IFD = {Ym, {(`DIVb-`NF-1){1'b0}}};
+    assign IFX = {Xm, {(P.DIVb-P.NF-1){1'b0}}};
+    assign IFD = {Ym, {(P.DIVb-P.NF-1){1'b0}}};
+    assign NumerZeroE = XZeroE;
   end
 
+  //////////////////////////////////////////////////////
+  // Integer & FP leading zero and normalization shift
+  //////////////////////////////////////////////////////
+
   // count leading zeros for Subnorm FP and to normalize integer inputs
-  lzc #(`DIVb) lzcX (IFX, ell);
-  lzc #(`DIVb) lzcY (IFD, mE);
+  lzc #(P.DIVb) lzcX (IFX, ell);
+  lzc #(P.DIVb) lzcY (IFD, mE);
 
   // Normalization shift: shift off leading one
-  assign XPreproc = (IFX << ell) << 1;
-  assign DPreproc = (IFD << mE)  << 1; 
+  assign Xfract = (IFX << ell) << 1;
+  assign Dfract = (IFD << mE)  << 1; 
 
-  // append leading 1 (for nonzero inputs)
-  // shift square root to be in range [1/4, 1)
-  // Normalized numbers are shifted right by 1 if the exponent is odd
-  // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
-  mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
-  assign DivX = {3'b000, ~NumerZeroE, XPreproc};
+  // *** CT: move to fdivsqrtintpreshift
 
-   // Divisior register
-  flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
+  //////////////////////////////////////////////////////
+  // Integer Right Shift to digit boundary
+  //  Determine DivXShifted (X shifted to digit boundary)
+  //  and nE (number of fractional digits)
+  //////////////////////////////////////////////////////
 
-  // ***CT: factor out fdivsqrtcycles
-  if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
-    logic [`DIVBLEN:0] ZeroDiff, p;
-    logic  ALTBE;
+  if (P.IDIV_ON_FPU) begin:intrightshift // Int Supported
+    logic [P.DIVBLEN:0] ZeroDiff, p;
 
     // calculate number of fractional bits p
     assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
-    assign ALTBE = ZeroDiff[`DIVBLEN];  // A less than B (A has more leading zeros)
-    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);              
+    assign ALTBE = ZeroDiff[P.DIVBLEN];  // A less than B (A has more leading zeros)
+    mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);              
 
     // Integer special cases (terminate immediately)
     assign ISpecialCaseE = BZeroE | ALTBE;
 
-  /* verilator lint_off WIDTH */
     // calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
 
-    if (`LOGRK > 0) begin // more than 1 bit per cycle
-      logic [`LOGRK-1:0] IntTrunc, RightShiftX;
-      logic [`DIVBLEN:0] TotalIntBits, IntSteps;
-
-      assign TotalIntBits = `LOGR + p;                            // Total number of result bits (r integer bits plus p fractional bits)
-      assign IntTrunc = TotalIntBits % `RK;                       // Truncation check for ceiling operator
-      assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc;     // Number of steps for int div
-      assign nE = (IntSteps * `DIVCOPIES) - 1;                    // Fractional digits
-      assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK);  // Right shift amount
+    if (P.LOGRK > 0) begin // more than 1 bit per cycle
+      logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
+      logic [P.DIVBLEN:0] TotalIntBits, IntSteps;
+      /* verilator lint_off WIDTH */
+      assign TotalIntBits = P.LOGR + p;                            // Total number of result bits (r integer bits plus p fractional bits)
+      assign IntTrunc = TotalIntBits % P.RK;                       // Truncation check for ceiling operator
+      assign IntSteps = (TotalIntBits >> P.LOGRK) + |IntTrunc;     // Number of steps for int div
+      assign nE = (IntSteps * P.DIVCOPIES) - 1;                    // Fractional digits
+      assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK);  // Right shift amount
       assign DivXShifted = DivX >> RightShiftX;                   // shift X by up to R*K-1 to complete in nE steps
+      /* verilator lint_on WIDTH */
     end else begin // radix 2 1 copy doesn't require shifting
       assign nE = p; 
       assign DivXShifted = DivX;
     end
-  /* verilator lint_on WIDTH */
+  end else begin
+    assign ISpecialCaseE = 0;
+  end
 
-    // Selet integer or floating-point operands
-    mux2 #(1)    numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
-    mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
+  // CT *** fdivsqrtfplead1
 
+  //////////////////////////////////////////////////////
+  // Floating-Point Preprocessing
+  // append leading 1 (for nonzero inputs)
+  // shift square root to be in range [1/4, 1)
+  // Normalized numbers are shifted right by 1 if the exponent is odd
+  // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
+  //////////////////////////////////////////////////////
+
+  assign DivX = {3'b000, ~NumerZeroE, Xfract};
+
+  // Sqrt is initialized on step one as R(X-1), so depends on Radix
+  mux2 #(P.DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[P.DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
+  if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
+  else              assign SqrtX = {2'b11, PreSqrtX, 1'b0};
+  mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
+  
+  //////////////////////////////////////////////////////
+  // Selet integer or floating-point operands
+  //////////////////////////////////////////////////////
+
+  if (P.IDIV_ON_FPU) begin
+    mux2 #(P.DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
+  end else begin
+    assign X = PreShiftX;
+  end
+
+   // Divisior register
+  flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {4'b0001, Dfract}, D);
+ 
+  // Floating-point exponent
+  fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
+  flopen #(P.NE+2) expreg(clk, IFDivStartE, QeE, QeM);
+
+  // Number of FSM cycles (to FSM)
+  fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .CyclesE);
+
+  if (P.IDIV_ON_FPU) begin:intpipelineregs
     // pipeline registers
-    flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,     IntDivM);
+    flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,  IntDivM);
     flopen #(1)       altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
     flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
     flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
     flopen #(1)      asignreg(clk, IFDivStartE, AsE,      AsM);
-    flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE,       nM); 
-    flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE,       mM);
-    flopen #(`XLEN)   srcareg(clk, IFDivStartE, AE,       AM);
-    if (`XLEN==64) 
+    flopen #(P.DIVBLEN+1) nreg(clk, IFDivStartE, nE,       nM); 
+    flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE,       mM);
+    flopen #(P.XLEN)   srcareg(clk, IFDivStartE, AE,       AM);
+    if (P.XLEN==64) 
       flopen #(1)      w64reg(clk, IFDivStartE, W64E,     W64M);
-  end else begin
-    assign NumerZeroE = XZeroE;
-    assign X = PreShiftX;
   end
 
-  // Sqrt is initialized on step one as R(X-1), so depends on Radix
-  if (`RADIX == 2)  assign SqrtX = {3'b111, PreSqrtX};
-  else              assign SqrtX = {2'b11, PreSqrtX, 1'b0};
-  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
- 
-  // Floating-point exponent
-  fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
-  flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
-
-  // Number of FSM cycles (to FSM)
-  fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .cycles);
 endmodule
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
index 18c577b97..fe32924e1 100644
--- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fdivsqrtqsel2 ( 
   input  logic [3:0] ps, pc, 
   output logic       up, uz, un
diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
index 7a0db24d8..de520bef2 100644
--- a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fdivsqrtqsel4 (
   input  logic [2:0] Dmsbs,
   input  logic [4:0] Smsbs,
diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
index e508a6d7c..8a3d535d3 100644
--- a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fdivsqrtqsel4cmp (
   input  logic [2:0] Dmsbs,
   input  logic [4:0] Smsbs,
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index be62f8aa6..bb8d87234 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -26,27 +26,26 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
 /* verilator lint_off UNOPTFLAT */
-module fdivsqrtstage2 (
-  input  logic [`DIVb+3:0] D, DBar, 
-  input  logic [`DIVb:0]   U, UM,
-  input  logic [`DIVb+3:0] WS, WC,
-  input  logic [`DIVb+1:0] C,
+module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.DIVb+3:0] D, DBar, 
+  input  logic [P.DIVb:0]   U, UM,
+  input  logic [P.DIVb+3:0] WS, WC,
+  input  logic [P.DIVb+1:0] C,
   input  logic             SqrtE,
   output logic             un,
-  output logic [`DIVb+1:0] CNext,
-  output logic [`DIVb:0]   UNext, UMNext, 
-  output logic [`DIVb+3:0] WSNext, WCNext
+  output logic [P.DIVb+1:0] CNext,
+  output logic [P.DIVb:0]   UNext, UMNext, 
+  output logic [P.DIVb+3:0] WSNext, WCNext
 );
  /* verilator lint_on UNOPTFLAT */
 
-  logic [`DIVb+3:0]        Dsel;
+  logic [P.DIVb+3:0]        Dsel;
   logic                    up, uz;
-  logic [`DIVb+3:0]        F;
-  logic [`DIVb+3:0]        AddIn;
-  logic [`DIVb+3:0]        WSA, WCA;
+  logic [P.DIVb+3:0]        F;
+  logic [P.DIVb+3:0]        AddIn;
+  logic [P.DIVb+3:0]        WSA, WCA;
 
   // Qmient Selection logic
   // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un)
@@ -56,10 +55,10 @@ module fdivsqrtstage2 (
   // 0000 =  0
   // 0010 = -1
   // 0001 = -2
-  fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
+  fdivsqrtqsel2 qsel2(WS[P.DIVb+3:P.DIVb], WC[P.DIVb+3:P.DIVb], up, uz, un);
 
   // Sqrt F generation.  Extend C, U, UM to Q4.k
-  fdivsqrtfgen2 fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
+  fdivsqrtfgen2 #(P) fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
 
   // Divisor multiple
   always_comb
@@ -69,16 +68,16 @@ module fdivsqrtstage2 (
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
-  mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
-  csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
+  mux2 #(P.DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
+  csa #(P.DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
   assign WSNext = WSA << 1;
   assign WCNext = WCA << 1;
 
   // Shift thermometer code C
-  assign CNext = {1'b1, C[`DIVb+1:1]};
+  assign CNext = {1'b1, C[P.DIVb+1:1]};
 
   // Unified On-The-Fly Converter to accumulate result
-  fdivsqrtuotfc2 uotfc2(.up, .un, .C(CNext), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc2 #(P) uotfc2(.up, .un, .C(CNext), .U, .UM, .UNext, .UMNext);
 endmodule
 
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index 9464e6a88..c6477ec68 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -26,29 +26,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtstage4 (
-  input  logic [`DIVb+3:0] D, DBar, D2, DBar2,
-  input  logic [`DIVb:0]   U,UM,
-  input  logic [`DIVb+3:0] WS, WC,
-  input  logic [`DIVb+1:0] C,
+module fdivsqrtstage4 import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.DIVb+3:0] D, DBar, D2, DBar2,
+  input  logic [P.DIVb:0]   U,UM,
+  input  logic [P.DIVb+3:0] WS, WC,
+  input  logic [P.DIVb+1:0] C,
   input  logic             SqrtE, j1,
-  output logic [`DIVb+1:0] CNext,
+  output logic [P.DIVb+1:0] CNext,
   output logic             un,
-  output logic [`DIVb:0]   UNext, UMNext, 
-  output logic [`DIVb+3:0] WSNext, WCNext
+  output logic [P.DIVb:0]   UNext, UMNext, 
+  output logic [P.DIVb+3:0] WSNext, WCNext
 );
 
-  logic [`DIVb+3:0]        Dsel;
+  logic [P.DIVb+3:0]        Dsel;
   logic [3:0]              udigit;
-  logic [`DIVb+3:0]        F;
-  logic [`DIVb+3:0]        AddIn;
+  logic [P.DIVb+3:0]        F;
+  logic [P.DIVb+3:0]        AddIn;
   logic [4:0]              Smsbs;
   logic [2:0]              Dmsbs;
   logic [7:0]              WCmsbs, WSmsbs;
   logic                    CarryIn;
-  logic [`DIVb+3:0]        WSA, WCA;
+  logic [P.DIVb+3:0]        WSA, WCA;
 
   // Digit Selection logic
   // u encoding:
@@ -57,16 +55,16 @@ module fdivsqrtstage4 (
   // 0000 =  0
   // 0010 = -1
   // 0001 = -2
-  assign Smsbs  = U[`DIVb:`DIVb-4];
-  assign Dmsbs  = D[`DIVb-1:`DIVb-3];
-  assign WCmsbs = WC[`DIVb+3:`DIVb-4];
-  assign WSmsbs = WS[`DIVb+3:`DIVb-4];
+  assign Smsbs  = U[P.DIVb:P.DIVb-4];
+  assign Dmsbs  = D[P.DIVb-1:P.DIVb-3];
+  assign WCmsbs = WC[P.DIVb+3:P.DIVb-4];
+  assign WSmsbs = WS[P.DIVb+3:P.DIVb-4];
 
   fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
   assign un = 1'b0; // unused for radix 4
 
   // F generation logic
-  fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
+  fdivsqrtfgen4 #(P) fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
 
   // Divisor multiple logic
   always_comb
@@ -83,15 +81,15 @@ module fdivsqrtstage4 (
   //  {WS, WC}}Next = (WS + WC - qD or F) << 2
   assign AddIn = SqrtE ? F : Dsel;
   assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D 
-  csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
+  csa #(P.DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
   assign WSNext = WSA << 2;
   assign WCNext = WCA << 2;
 
   // Shift thermometer code C
-  assign CNext = {2'b11, C[`DIVb+1:2]};
+  assign CNext = {2'b11, C[P.DIVb+1:2]};
  
   // On-the-fly converter to accumulate result
-  fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc4 #(P) fdivsqrtuotfc4(.udigit, .C(CNext[P.DIVb:0]), .U, .UM, .UNext, .UMNext);
 endmodule
 
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
index 33956a0fd..bde28cfba 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
@@ -26,22 +26,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 ///////////////////////////////
 // Unified OTFC, Radix 2 //
 ///////////////////////////////
-module fdivsqrtuotfc2(
+module fdivsqrtuotfc2 import cvw::*;  #(parameter cvw_t P) (
   input  logic             up, un,
-  input  logic [`DIVb+1:0] C,
-  input  logic [`DIVb:0]   U, UM,
-  output logic [`DIVb:0]   UNext, UMNext
+  input  logic [P.DIVb+1:0] C,
+  input  logic [P.DIVb:0]   U, UM,
+  output logic [P.DIVb:0]   UNext, UMNext
 );
   //  The on-the-fly converter transfers the divsqrt
   //  bits to the quotient as they come.
-  logic [`DIVb:0] K;
+  logic [P.DIVb:0] K;
 
-  assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); // Thermometer to one hot encoding
+  assign K = (C[P.DIVb:0] & ~(C[P.DIVb:0] << 1)); // Thermometer to one hot encoding
 
   always_comb begin
     if (up) begin
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
index 57298b4c8..403ccf051 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
@@ -26,19 +26,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fdivsqrtuotfc4(
+module fdivsqrtuotfc4 import cvw::*;  #(parameter cvw_t P) (
   input  logic [3:0]     udigit,
-  input  logic [`DIVb:0] U, UM,
-  input  logic [`DIVb:0] C,
-  output logic [`DIVb:0] UNext, UMNext
+  input  logic [P.DIVb:0] U, UM,
+  input  logic [P.DIVb:0] C,
+  output logic [P.DIVb:0] UNext, UMNext
 );
   //  The on-the-fly converter transfers the square root 
   //  bits to the quotient as they come.
   //  Use this otfc for division and square root.
 
-  logic [`DIVb:0] K1, K2, K3;       
+  logic [P.DIVb:0] K1, K2, K3;       
   assign K1 = (C&~(C << 1));        // K
   assign K2 = ((C << 1)&~(C << 2)); // 2K
   assign K3 = (C & ~(C << 2));      // 3K
diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
index dadbf6d4f..14f8c945f 100644
--- a/src/fpu/fhazard.sv
+++ b/src/fpu/fhazard.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fhazard(
   input  logic [4:0]  Adr1D, Adr2D, Adr3D,                // read data adresses
   input  logic [4:0]  Adr1E, Adr2E, Adr3E,                // read data adresses
@@ -58,7 +56,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
   
-
     // if the needed value is in the memory stage - input 2
     if ((Adr2E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -66,7 +63,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
 
-
     // if the needed value is in the memory stage - input 3
     if ((Adr3E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -74,5 +70,4 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
   end 
-
 endmodule
diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
index 437c698ec..80f040171 100644
--- a/src/fpu/fma/fma.sv
+++ b/src/fpu/fma/fma.sv
@@ -26,22 +26,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fma(
+module fma import cvw::*;  #(parameter cvw_t P) (
   input  logic                        Xs, Ys, Zs,             // input's signs
-  input  logic [`NE-1:0]              Xe, Ye, Ze,             // input's biased exponents in B(NE.0) format
-  input  logic [`NF:0]                Xm, Ym, Zm,             // input's significands in U(0.NF) format
+  input  logic [P.NE-1:0]              Xe, Ye, Ze,             // input's biased exponents in B(NE.0) format
+  input  logic [P.NF:0]                Xm, Ym, Zm,             // input's significands in U(0.NF) format
   input  logic                        XZero, YZero, ZZero,    // is the input zero
   input  logic [2:0]                  OpCtrl,                 // operation control
   output logic                        ASticky,                // sticky bit that is calculated during alignment
-  output logic [3*`NF+3:0]            Sm,                     // the positive sum's significand
+  output logic [3*P.NF+3:0]            Sm,                     // the positive sum's significand
   output logic                        InvA,                   // Was A inverted for effective subtraction (P-A or -P+A)
   output logic                        As,                     // the aligned addend's sign (modified Z sign for other opperations)
   output logic                        Ps,                     // the product's sign
   output logic                        Ss,                     // the sum's sign
-  output logic [`NE+1:0]              Se,                     // the sum's exponent
-  output logic [$clog2(3*`NF+5)-1:0]  SCnt                    // normalization shift count
+  output logic [P.NE+1:0]              Se,                     // the sum's exponent
+  output logic [$clog2(3*P.NF+5)-1:0]  SCnt                    // normalization shift count
 );
 
   //  OpCtrl:
@@ -54,12 +52,12 @@ module fma(
   //        110 - add
   //        111 - sub
 
-  logic [2*`NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
-  logic [3*`NF+3:0]   Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
-  logic [3*`NF+3:0]   AmInv;      // aligned addend's mantissa possibly inverted
-  logic [2*`NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
+  logic [2*P.NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
+  logic [3*P.NF+3:0]   Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
+  logic [3*P.NF+3:0]   AmInv;      // aligned addend's mantissa possibly inverted
+  logic [2*P.NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
   logic               KillProd;   // set the product to zero before addition if the product is too small to matter
-  logic [`NE+1:0]     Pe;         // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
+  logic [P.NE+1:0]     Pe;         // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
 
   ///////////////////////////////////////////////////////////////////////////////
   // Calculate the product
@@ -71,10 +69,10 @@ module fma(
   
 
   // calculate the product's exponent 
-  fmaexpadd expadd(.Xe, .Ye, .XZero, .YZero, .Pe);
+  fmaexpadd #(P) expadd(.Xe, .Ye, .XZero, .YZero, .Pe);
 
   // multiplication of the mantissa's
-  fmamult mult(.Xm, .Ym, .Pm);
+  fmamult #(P) mult(.Xm, .Ym, .Pm);
   
   // calculate the signs and take the opperation into account
   fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA);
@@ -82,15 +80,15 @@ module fma(
   ///////////////////////////////////////////////////////////////////////////////
   // Alignment shifter
   ///////////////////////////////////////////////////////////////////////////////
-  fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ASticky, .KillProd);
+  fmaalign #(P) align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ASticky, .KillProd);
                       
   // ///////////////////////////////////////////////////////////////////////////////
   // // Addition/LZA
   // ///////////////////////////////////////////////////////////////////////////////
       
-  fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
+  fmaadd #(P) add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
 
-  fmalza #(3*`NF+4) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
+  fmalza #(3*P.NF+4, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
   
 endmodule
 
diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv
index b8b61bd6e..52a2bf6cf 100644
--- a/src/fpu/fma/fmaadd.sv
+++ b/src/fpu/fma/fmaadd.sv
@@ -26,25 +26,23 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmaadd(
-  input  logic [3*`NF+3:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
-  input  logic [`NE-1:0]      Ze,         // exponent of Z
+module fmaadd import cvw::*;  #(parameter cvw_t P) (
+  input  logic [3*P.NF+3:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
+  input  logic [P.NE-1:0]      Ze,         // exponent of Z
   input  logic                Ps,         // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
-  input  logic [`NE+1:0]      Pe,         // product's exponet
-  input  logic [2*`NF+1:0]    Pm,         // the product's mantissa
+  input  logic [P.NE+1:0]      Pe,         // product's exponet
+  input  logic [2*P.NF+1:0]    Pm,         // the product's mantissa
   input  logic                InvA,       // invert the aligned addend
   input  logic                KillProd,   // should the product be set to 0
   input  logic                ASticky,    // Alighed addend's sticky bit
-  output logic [3*`NF+3:0]    AmInv,      // aligned addend possibly inverted
-  output logic [2*`NF+1:0]    PmKilled,   // the product's mantissa possibly killed
+  output logic [3*P.NF+3:0]    AmInv,      // aligned addend possibly inverted
+  output logic [2*P.NF+1:0]    PmKilled,   // the product's mantissa possibly killed
   output logic                Ss,         // sum's sign    
-  output logic [`NE+1:0]      Se,         // sum's exponent
-  output logic [3*`NF+3:0]    Sm          // the positive sum
+  output logic [P.NE+1:0]      Se,         // sum's exponent
+  output logic [3*P.NF+3:0]    Sm          // the positive sum
 );
 
-  logic [3*`NF+3:0]    PreSum, NegPreSum; // possibly negitive sum
+  logic [3*P.NF+3:0]    PreSum, NegPreSum; // possibly negitive sum
   logic                NegSum;            // was the sum negitive
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -52,9 +50,9 @@ module fmaadd(
   ///////////////////////////////////////////////////////////////////////////////
   
   // Choose an inverted or non-inverted addend.  Put carry into adder/LZA for addition
-  assign AmInv = {3*`NF+4{InvA}}^Am;
+  assign AmInv = {3*P.NF+4{InvA}}^Am;
   // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
-  assign PmKilled = {2*`NF+2{~KillProd}}&Pm;
+  assign PmKilled = {2*P.NF+2{~KillProd}}&Pm;
   // Do the addition
   //      - calculate a positive and negitive sum in parallel
   // if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum
@@ -63,8 +61,8 @@ module fmaadd(
   //      addend - prod where product is killed (and not exactly zero) then don't add +1 from negation 
   //          ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA
   //          in this case this result is only ever selected when InvA=1 so we can remove &InvA
-  assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*`NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
-  assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*`NF+2)'(0), ~ASticky|~KillProd, 1'b0};
+  assign {NegSum, PreSum} = {{P.NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*P.NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
+  assign NegPreSum = Am + {{P.NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*P.NF+2)'(0), ~ASticky|~KillProd, 1'b0};
     
   // Choose the positive sum and accompanying LZA result.
   assign Sm = NegSum ? NegPreSum : PreSum;
diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
index b51c2a7f1..06817d446 100644
--- a/src/fpu/fma/fmaalign.sv
+++ b/src/fpu/fma/fmaalign.sv
@@ -27,20 +27,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmaalign(
-  input  logic [`NE-1:0]      Xe, Ye, Ze,         // biased exponents in B(NE.0) format
-  input  logic [`NF:0]        Zm,                 // significand in U(0.NF) format]
+module fmaalign import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.NE-1:0]      Xe, Ye, Ze,         // biased exponents in B(NE.0) format
+  input  logic [P.NF:0]        Zm,                 // significand in U(0.NF) format]
   input  logic                XZero, YZero, ZZero,// is the input zero
-  output logic [3*`NF+3:0]    Am,                 // addend aligned for addition in U(NF+5.2NF+1)
+  output logic [3*P.NF+3:0]    Am,                 // addend aligned for addition in U(NF+5.2NF+1)
   output logic                ASticky,            // Sticky bit calculated from the aliged addend
   output logic                KillProd            // should the product be set to zero
 );
 
-  logic [`NE+1:0]             ACnt;           // how far to shift the addend to align with the product in Q(NE+2.0) format
-  logic [4*`NF+3:0]           ZmShifted;      // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
-  logic [4*`NF+3:0]           ZmPreshifted;   // input to the alignment shifter U(NF+5.3NF+1)
+  logic [P.NE+1:0]             ACnt;           // how far to shift the addend to align with the product in Q(NE+2.0) format
+  logic [4*P.NF+3:0]           ZmShifted;      // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
+  logic [4*P.NF+3:0]           ZmPreshifted;   // input to the alignment shifter U(NF+5.3NF+1)
   logic                       KillZ;          // should the addend be killed
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -51,16 +49,16 @@ module fmaalign(
   //      - negitive means Z is larger, so shift Z left
   //      - positive means the product is larger, so shift Z right
   // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
-  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+2) - {2'b0, Ze};
+  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze};
 
   // Defualt Addition with only inital left shift
   //          |   53'b0    |  106'b(product)  | 1'b0 |
   //          | addnend |
 
-  assign ZmPreshifted = {Zm,(3*`NF+3)'(0)};
+  assign ZmPreshifted = {Zm,(3*P.NF+3)'(0)};
   
-  assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
-  assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(3));
+  assign KillProd = (ACnt[P.NE+1]&~ZZero)|XZero|YZero;
+  assign KillZ = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(3));
 
   always_comb begin
     // If the product is too small to effect the sum, kill the product
@@ -68,7 +66,7 @@ module fmaalign(
     //          |   53'b0    |  106'b(product)  | 1'b0 |
     //  | addnend |
     if (KillProd) begin
-        ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+1)'(0)};
+        ZmShifted = {(P.NF+2)'(0), Zm, (2*P.NF+1)'(0)};
         ASticky = ~(XZero|YZero);
 
     // If the addend is too small to effect the addition        
@@ -86,12 +84,12 @@ module fmaalign(
     //                                    | addnend |
     end else begin
         ZmShifted = ZmPreshifted >> ACnt;
-        ASticky = |(ZmShifted[`NF-1:0]); 
+        ASticky = |(ZmShifted[P.NF-1:0]); 
 
     end
   end
 
-  assign Am = ZmShifted[4*`NF+3:`NF];
+  assign Am = ZmShifted[4*P.NF+3:P.NF];
 
 endmodule
 
diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv
index 3c615274f..d6ef8844c 100644
--- a/src/fpu/fma/fmaexpadd.sv
+++ b/src/fpu/fma/fmaexpadd.sv
@@ -26,18 +26,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmaexpadd(    
-  input  logic [`NE-1:0]      Xe, Ye,         // input's exponents
+module fmaexpadd import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.NE-1:0]      Xe, Ye,         // input's exponents
   input  logic                XZero, YZero,   // are the inputs zero
-  output logic [`NE+1:0]      Pe              // product's exponent B^(1023)NE+2
+  output logic [P.NE+1:0]      Pe              // product's exponent B^(1023)NE+2
 );
 
   logic                       PZero;          // is the product zero?
   
   // kill the exponent if the product is zero - either X or Y is 0
   assign PZero = XZero | YZero;
-  assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)});
+  assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)});
 
 endmodule
diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv
index 59fb3fc3e..b7ccbef8e 100644
--- a/src/fpu/fma/fmalza.sv
+++ b/src/fpu/fma/fmalza.sv
@@ -27,11 +27,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmalza #(WIDTH) ( 
+module fmalza #(WIDTH, NF) ( 
   input logic [WIDTH-1:0]             A,      // addend
-  input logic [2*`NF+1:0]             Pm,     // product
+  input logic [2*NF+1:0]             Pm,     // product
   input logic                         Cin,    // carry in
   input logic                         sub,    // subtraction
   output logic [$clog2(WIDTH+1)-1:0]  SCnt    // normalization shift count for the positive result
@@ -42,7 +40,7 @@ module fmalza #(WIDTH) (
   logic [WIDTH-1:0]                   P, G, K;        // propagate, generate, kill for each column
   logic [WIDTH-1:0]                   Pp1, Gm1, Km1;  // propagate shifted right by 1, generate/kill shifted left 1
 
-  assign B = {{(`NF+1){1'b0}}, Pm, 1'b0}; // Zero extend product
+  assign B = {{(NF+1){1'b0}}, Pm, 1'b0}; // Zero extend product
 
   assign P = A^B;
   assign G = A&B;
diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv
index 541ba3687..7d01a22d6 100644
--- a/src/fpu/fma/fmamult.sv
+++ b/src/fpu/fma/fmamult.sv
@@ -26,11 +26,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmamult(
-  input  logic [`NF:0]     Xm, Ym, // x and y significand
-  output logic [2*`NF+1:0] Pm      // product's significand
+module fmamult import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.NF:0]     Xm, Ym, // x and y significand
+  output logic [2*P.NF+1:0] Pm      // product's significand
 );
 
   assign Pm = Xm * Ym;
diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv
index a2308da7f..0091778ee 100644
--- a/src/fpu/fma/fmasign.sv
+++ b/src/fpu/fma/fmasign.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fmasign(    
   input  logic [2:0]  OpCtrl,     // opperation contol
   input  logic        Xs, Ys, Zs, // sign of the inputs
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index 32bdfc1ca..f71999471 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -26,43 +26,41 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fpu (
-  input  logic             clk,
-  input  logic             reset,
+module fpu import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk,
+  input  logic                 reset,
   // Hazards
-  input  logic             StallE, StallM, StallW,         // stall signals (from HZU)
-  input  logic             FlushE, FlushM, FlushW,         // flush signals (from HZU)
-  output logic             FPUStallD,                      // Stall the decode stage (To HZU)
-  output logic             FDivBusyE,                      // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
+  input  logic                 StallE, StallM, StallW,             // stall signals (from HZU)
+  input  logic                 FlushE, FlushM, FlushW,             // flush signals (from HZU)
+  output logic                 FPUStallD,                          // Stall the decode stage (To HZU)
+  output logic                 FDivBusyE,                          // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
   // CSRs                                                  
-  input  logic [1:0]       STATUS_FS,                      // Is floating-point enabled? (From privileged unit)
-  input  logic [2:0]       FRM_REGW,                       // Rounding mode (from CSR)
+  input  logic [1:0]           STATUS_FS,                          // Is floating-point enabled? (From privileged unit)
+  input  logic [2:0]           FRM_REGW,                           // Rounding mode (from CSR)
   // Decode stage                                          
-  input  logic [31:0]      InstrD,                         // instruction (from IFU)
+  input  logic [31:0]          InstrD,                             // instruction (from IFU)
   // Execute stage                                         
-  input  logic [2:0]       Funct3E,                        // Funct fields of instruction specify type of operations
-  input  logic             IntDivE, W64E,                  // Integer division on FPU
-  input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
-  input  logic [4:0]       RdE,                            // which FP register to write to (from IEU)
-  output logic             FWriteIntE,                     // integer register write enable (to IEU)
-  output logic             FCvtIntE,                       // Convert to int (to IEU)
+  input  logic [2:0]           Funct3E,                            // Funct fields of instruction specify type of operations
+  input  logic                 IntDivE, W64E,                      // Integer division on FPU
+  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE,     // Integer input for convert, move, and int div (from IEU)
+  input  logic [4:0]           RdE,                                // which FP register to write to (from IEU)
+  output logic                 FWriteIntE,                         // integer register write enable (to IEU)
+  output logic                 FCvtIntE,                           // Convert to int (to IEU)
   // Memory stage                                          
-  input  logic [2:0]       Funct3M,                        // Funct fields of instruction specify type of operations
-  input  logic [4:0]       RdM,                            // which FP register to write to (from IEU)
-  output logic             FRegWriteM,                     // FP register write enable (to privileged unit)
-  output logic             FpLoadStoreM,                   // Fp load instruction? (to LSU)
-  output logic [`FLEN-1:0] FWriteDataM,                    // Data to be written to memory (to LSU) 
-  output logic [`XLEN-1:0] FIntResM,                       // data to be written to integer register (to IEU)
-  output logic             IllegalFPUInstrD,               // Is the instruction an illegal fpu instruction (to IFU)
-  output logic [4:0]       SetFflagsM,                     // FPU flags (to privileged unit)
+  input  logic [2:0]           Funct3M,                            // Funct fields of instruction specify type of operations
+  input  logic [4:0]           RdM,                                // which FP register to write to (from IEU)
+  output logic                 FRegWriteM,                         // FP register write enable (to privileged unit)
+  output logic                 FpLoadStoreM,                       // Fp load instruction? (to LSU)
+  output logic [P.FLEN-1:0]    FWriteDataM,                        // Data to be written to memory (to LSU) 
+  output logic [P.XLEN-1:0]    FIntResM,                           // data to be written to integer register (to IEU)
+  output logic                 IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction (to IFU)
+  output logic [4:0]           SetFflagsM,                         // FPU flags (to privileged unit)
   // Writeback stage                                       
-  input  logic [4:0]       RdW,                            // which FP register to write to (from IEU)
-  input  logic [`FLEN-1:0] ReadDataW,                      // Read data (from LSU)
-  output logic [`XLEN-1:0] FCvtIntResW,                    // convert result to to be written to integer register (to IEU)
-  output logic             FCvtIntW,                       // select FCvtIntRes (to IEU)
-  output logic [`XLEN-1:0] FIntDivResultW                  // Result from integer division (to IEU)
+  input  logic [4:0]           RdW,                                // which FP register to write to (from IEU)
+  input  logic [P.FLEN-1:0]    ReadDataW,                          // Read data (from LSU)
+  output logic [P.XLEN-1:0]    FCvtIntResW,                        // convert result to to be written to integer register (to IEU)
+  output logic                 FCvtIntW,                           // select FCvtIntRes (to IEU)
+  output logic [P.XLEN-1:0]    FIntDivResultW                      // Result from integer division (to IEU)
 );
 
   // RISC-V FPU specifics:
@@ -70,122 +68,123 @@ module fpu (
   //    - RISC-V detects underflow after rounding
 
   // control signals
-  logic                    FRegWriteW;                        // FP register write enable
-  logic [2:0]              FrmM;                              // FP rounding mode
-  logic [`FMTBITS-1:0]     FmtE, FmtM;                        // FP precision 0-single 1-double
-  logic                    FDivStartE, IDivStartE;            // Start division or squareroot
-  logic                    FWriteIntM;                        // Write to integer register
-  logic [1:0]              ForwardXE, ForwardYE, ForwardZE;   // forwarding mux control signals
-  logic [2:0]              OpCtrlE, OpCtrlM;                  // Select which opperation to do in each component
-  logic [1:0]              FResSelE, FResSelM, FResSelW;      // Select one of the results that finish in the memory stage
-  logic [1:0]              PostProcSelE, PostProcSelM;        // select result in the post processing unit
-  logic [4:0]              Adr1D, Adr2D, Adr3D;               // register adresses of each input
-  logic [4:0]              Adr1E, Adr2E, Adr3E;               // register adresses of each input
-  logic                    XEnD, YEnD, ZEnD;                  // X, Y, Z inputs used for current operation
-  logic                    XEnE, YEnE, ZEnE;                  // X, Y, Z inputs used for current operation
-  logic                    FRegWriteE;                        // Write floating-point register
+  logic                        FRegWriteW;                         // FP register write enable
+  logic [2:0]                  FrmM;                               // FP rounding mode
+  logic [P.FMTBITS-1:0]        FmtE, FmtM;                         // FP precision 0-single 1-double
+  logic                        FDivStartE, IDivStartE;             // Start division or squareroot
+  logic                        FWriteIntM;                         // Write to integer register
+  logic [1:0]                  ForwardXE, ForwardYE, ForwardZE;    // forwarding mux control signals
+  logic [2:0]                  OpCtrlE, OpCtrlM;                   // Select which opperation to do in each component
+  logic [1:0]                  FResSelE, FResSelM, FResSelW;       // Select one of the results that finish in the memory stage
+  logic [1:0]                  PostProcSelE, PostProcSelM;         // select result in the post processing unit
+  logic [4:0]                  Adr1D, Adr2D, Adr3D;                // register adresses of each input
+  logic [4:0]                  Adr1E, Adr2E, Adr3E;                // register adresses of each input
+  logic                        XEnD, YEnD, ZEnD;                   // X, Y, Z inputs used for current operation
+  logic                        XEnE, YEnE, ZEnE;                   // X, Y, Z inputs used for current operation
+  logic                        FRegWriteE;                         // Write floating-point register
+  logic                        FPUActiveE;                         // FP instruction being executed
 
   // regfile signals
-  logic [`FLEN-1:0]        FRD1D, FRD2D, FRD3D;                  // Read Data from FP register - decode stage
-  logic [`FLEN-1:0]        FRD1E, FRD2E, FRD3E;                  // Read Data from FP register - execute stage
-  logic [`FLEN-1:0]        XE;                                   // Input 1 to the various units (after forwarding)
-  logic [`XLEN-1:0]        IntSrcXE;                             // Input 1 to the various units (after forwarding)
-  logic [`FLEN-1:0]        PreYE, YE;                            // Input 2 to the various units (after forwarding)
-  logic [`FLEN-1:0]        PreZE, ZE;                            // Input 3 to the various units (after forwarding)
+  logic [P.FLEN-1:0]           FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
+  logic [P.FLEN-1:0]           FRD1E, FRD2E, FRD3E;                // Read Data from FP register - execute stage
+  logic [P.FLEN-1:0]           XE;                                 // Input 1 to the various units (after forwarding)
+  logic [P.XLEN-1:0]           IntSrcXE;                           // Input 1 to the various units (after forwarding)
+  logic [P.FLEN-1:0]           PreYE, YE;                          // Input 2 to the various units (after forwarding)
+  logic [P.FLEN-1:0]           PreZE, ZE;                          // Input 3 to the various units (after forwarding)
 
   // unpacking signals
-  logic                    XsE, YsE, ZsE;                        // input's sign - execute stage
-  logic                    XsM, YsM;                             // input's sign - memory stage
-  logic [`NE-1:0]          XeE, YeE, ZeE;                        // input's exponent - execute stage
-  logic [`NE-1:0]          ZeM;                                  // input's exponent - memory stage
-  logic [`NF:0]            XmE, YmE, ZmE;                        // input's significand - execute stage
-  logic [`NF:0]            XmM, YmM, ZmM;                        // input's significand - memory stage
-  logic                    XNaNE, YNaNE, ZNaNE;                  // is the input a NaN - execute stage
-  logic                    XNaNM, YNaNM, ZNaNM;                  // is the input a NaN - memory stage
-  logic                    XSNaNE, YSNaNE, ZSNaNE;               // is the input a signaling NaN - execute stage
-  logic                    XSNaNM, YSNaNM, ZSNaNM;               // is the input a signaling NaN - memory stage
-  logic                    XSubnormE;                            // is the input subnormal
-  logic                    XZeroE, YZeroE, ZZeroE;               // is the input zero - execute stage
-  logic                    XZeroM, YZeroM;                       // is the input zero - memory stage
-  logic                    XInfE, YInfE, ZInfE;                  // is the input infinity - execute stage
-  logic                    XInfM, YInfM, ZInfM;                  // is the input infinity - memory stage
-  logic                    XExpMaxE;                             // is the exponent all ones (max value)
-  logic [`FLEN-1:0]        XPostBoxE;                            // X after fixing bad NaN box.  Needed for 1-input operations
+  logic                        XsE, YsE, ZsE;                      // input's sign - execute stage
+  logic                        XsM, YsM;                           // input's sign - memory stage
+  logic [P.NE-1:0]             XeE, YeE, ZeE;                      // input's exponent - execute stage
+  logic [P.NE-1:0]             ZeM;                                // input's exponent - memory stage
+  logic [P.NF:0]               XmE, YmE, ZmE;                      // input's significand - execute stage
+  logic [P.NF:0]               XmM, YmM, ZmM;                      // input's significand - memory stage
+  logic                        XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
+  logic                        XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
+  logic                        XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
+  logic                        XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
+  logic                        XSubnormE;                          // is the input subnormal
+  logic                        XZeroE, YZeroE, ZZeroE;             // is the input zero - execute stage
+  logic                        XZeroM, YZeroM;                     // is the input zero - memory stage
+  logic                        XInfE, YInfE, ZInfE;                // is the input infinity - execute stage
+  logic                        XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
+  logic                        XExpMaxE;                           // is the exponent all ones (max value)
+  logic [P.FLEN-1:0]           XPostBoxE;                          // X after fixing bad NaN box.  Needed for 1-input operations
 
   // Fma Signals
-  logic                    FmaAddSubE;                           // Multiply by 1.0 when adding or subtracting
-  logic [1:0]              FmaZSelE;                             // Select Z = Y when adding or subtracting, 0 when multiplying
-  logic [3*`NF+3:0]        SmE, SmM;                             // Sum significand
-  logic                    FmaAStickyE, FmaAStickyM;             // FMA addend sticky bit output
-  logic [`NE+1:0]          SeE,SeM;                              // Sum exponent
-  logic                    InvAE, InvAM;                         // Invert addend
-  logic                    AsE, AsM;                             // Addend sign
-  logic                    PsE, PsM;                             // Product sign
-  logic                    SsE, SsM;                             // Sum sign
-  logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;                      // LZA sum leading zero count
+  logic                        FmaAddSubE;                         // Multiply by 1.0 when adding or subtracting
+  logic [1:0]                  FmaZSelE;                           // Select Z = Y when adding or subtracting, 0 when multiplying
+  logic [3*P.NF+3:0]           SmE, SmM;                           // Sum significand
+  logic                        FmaAStickyE, FmaAStickyM;           // FMA addend sticky bit output
+  logic [P.NE+1:0]             SeE,SeM;                            // Sum exponent
+  logic                        InvAE, InvAM;                       // Invert addend
+  logic                        AsE, AsM;                           // Addend sign
+  logic                        PsE, PsM;                           // Product sign
+  logic                        SsE, SsM;                           // Sum sign
+  logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM;                       // LZA sum leading zero count
   
   // Cvt Signals
-  logic [`NE:0]               CeE, CeM;                           // convert intermediate expoent
-  logic [`LOGCVTLEN-1:0]      CvtShiftAmtE, CvtShiftAmtM;         // how much to shift by
-  logic                       CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
-  logic                       CsE, CsM;                           // convert result sign
-  logic                       IntZeroE, IntZeroM;                 // is the integer zero?
-  logic [`CVTLEN-1:0]         CvtLzcInE, CvtLzcInM;               // input to the Leading Zero Counter (priority encoder)
-  logic [`XLEN-1:0]           FCvtIntResM;                        // fcvt integer result (for IEU)
+  logic [P.NE:0]               CeE, CeM;                           // convert intermediate expoent
+  logic [P.LOGCVTLEN-1:0]      CvtShiftAmtE, CvtShiftAmtM;         // how much to shift by
+  logic                        CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
+  logic                        CsE, CsM;                           // convert result sign
+  logic                        IntZeroE, IntZeroM;                 // is the integer zero?
+  logic [P.CVTLEN-1:0]         CvtLzcInE, CvtLzcInM;               // input to the Leading Zero Counter (priority encoder)
+  logic [P.XLEN-1:0]           FCvtIntResM;                        // fcvt integer result (for IEU)
   
   // divide signals
-  logic [`DIVb:0]             QmM;                                // fdivsqrt signifcand
-  logic [`NE+1:0]             QeM;                                // fdivsqrt exponent
-  logic                       DivStickyM;                         // fdivsqrt sticky bit
-  logic                       FDivDoneE, IFDivStartE;             // fdivsqrt control signals
-  logic [`XLEN-1:0]           FIntDivResultM;                     // fdivsqrt integer division result (for IEU)
+  logic [P.DIVb:0]             QmM;                                // fdivsqrt signifcand
+  logic [P.NE+1:0]             QeM;                                // fdivsqrt exponent
+  logic                        DivStickyM;                         // fdivsqrt sticky bit
+  logic                        FDivDoneE, IFDivStartE;             // fdivsqrt control signals
+  logic [P.XLEN-1:0]           FIntDivResultM;                     // fdivsqrt integer division result (for IEU)
 
   // result and flag signals
-  logic [`XLEN-1:0]           ClassResE;                          // classify result
-  logic [`FLEN-1:0]           CmpFpResE;                          // compare result to FPU (min/max)
-  logic [`XLEN-1:0]           CmpIntResE;                         // compare result to IEU (eq/lt/le)
-  logic                       CmpNVE;                             // compare invalid flag (Not Valid)     
-  logic [`FLEN-1:0]           SgnResE;                            // sign injection result
-  logic [`XLEN-1:0]           FIntResE;                           // FPU to IEU E-stage result (classify, compare, move)
-  logic [`FLEN-1:0]           PostProcResM;                       // Postprocessor output
-  logic [4:0]                 PostProcFlgM;                       // Postprocessor flags
-  logic                       PreNVE, PreNVM;                     // selected flag that is ready in the memory stage     
-  logic [`FLEN-1:0]           FpResM, FpResW;                     // FPU preliminary result
-  logic [`FLEN-1:0]           PreFpResE, PreFpResM;               // selected result that is ready in the memory stage
-  logic [`FLEN-1:0]           FResultW;                           // final FP result being written to the FP register   
+  logic [P.XLEN-1:0]           ClassResE;                          // classify result
+  logic [P.FLEN-1:0]           CmpFpResE;                          // compare result to FPU (min/max)
+  logic [P.XLEN-1:0]           CmpIntResE;                         // compare result to IEU (eq/lt/le)
+  logic                        CmpNVE;                             // compare invalid flag (Not Valid)     
+  logic [P.FLEN-1:0]           SgnResE;                            // sign injection result
+  logic [P.XLEN-1:0]           FIntResE;                           // FPU to IEU E-stage result (classify, compare, move)
+  logic [P.FLEN-1:0]           PostProcResM;                       // Postprocessor output
+  logic [4:0]                  PostProcFlgM;                       // Postprocessor flags
+  logic                        PreNVE, PreNVM;                     // selected flag that is ready in the memory stage     
+  logic [P.FLEN-1:0]           FpResM, FpResW;                     // FPU preliminary result
+  logic [P.FLEN-1:0]           PreFpResE, PreFpResM;               // selected result that is ready in the memory stage
+  logic [P.FLEN-1:0]           FResultW;                           // final FP result being written to the FP register   
 
   // other signals
-  logic [`FLEN-1:0]           AlignedSrcAE;                       // align SrcA from IEU to the floating point format for fmv
-  logic [`FLEN-1:0]           BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
-  logic [`FLEN-1:0]           BoxedOneE;                          // One value for Z for multiplication, with NaN boxing if needed
-  logic                       StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
-  logic [`FLEN-1:0]           SgnExtXE;                           // Sign-extended X input for move to integer
-  logic                       mvsgn;                              // sign bit for extending move
+  logic [P.FLEN-1:0]           AlignedSrcAE;                       // align SrcA from IEU to the floating point format for fmv
+  logic [P.FLEN-1:0]           BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
+  logic [P.FLEN-1:0]           BoxedOneE;                          // One value for Z for multiplication, with NaN boxing if needed
+  logic                        StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
+  logic [P.FLEN-1:0]           SgnExtXE;                           // Sign-extended X input for move to integer
+  logic                        mvsgn;                              // sign bit for extending move
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Decode Stage: fctrl decoder, read register file
   //////////////////////////////////////////////////////////////////////////////////////////
 
   // calculate FP control signals
-  fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
+  fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
               .Funct3E, .IntDivE, .InstrD,
               .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
               .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
               .IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
-              .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
+              .FResSelE, .FResSelM, .FResSelW, .FPUActiveE, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
               .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
 
   // FP register file
-  fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
+  fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
     .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
     .a4(RdW), .wd4(FResultW),
     .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));  
 
   // D/E pipeline registers  
-  flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
-  flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
-  flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
+  flopenrc #(P.FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
+  flopenrc #(P.FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
+  flopenrc #(P.FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Execute Stage: hazards, forwarding, unpacking, execution units
@@ -197,137 +196,136 @@ module fpu (
     .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
 
   // forwarding muxs
-  mux3  #(`FLEN)  fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
-  mux3  #(`FLEN)  fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
-  mux3  #(`FLEN)  fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
+  mux3  #(P.FLEN)  fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
+  mux3  #(P.FLEN)  fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
+  mux3  #(P.FLEN)  fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
 
   // Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z
-  if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
-  else if(`FPSIZES == 2) 
-      mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
-  else if(`FPSIZES == 3 | `FPSIZES == 4) 
-      mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}, 
-                          {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}, 
-                          {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, 
-                          {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
+  if(P.FPSIZES == 1) assign BoxedOneE = {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)};
+  else if(P.FPSIZES == 2) 
+      mux2 #(P.FLEN) fonemux ({{P.FLEN-P.LEN1{1'b1}}, 2'b0, {P.NE1-1{1'b1}}, (P.NF1)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
+  else if(P.FPSIZES == 3 | P.FPSIZES == 4) 
+      mux4 #(P.FLEN) fonemux ({{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)}, 
+                              {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}, 
+                              {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, 
+                              {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
   assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
-  mux2  #(`FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
+  mux2  #(P.FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
   
   // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
   // For add and subtract, Z comes from second source operand
- if(`FPSIZES == 1) assign BoxedZeroE = 0;
-  else if(`FPSIZES == 2) 
-    mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
-  else if(`FPSIZES == 3 | `FPSIZES == 4)
-    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}, 
-                                {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, 
-                                {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, 
-                                (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
+  if(P.FPSIZES == 1) assign BoxedZeroE = 0;
+  else if(P.FPSIZES == 2) 
+    mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
+  else if(P.FPSIZES == 3 | P.FPSIZES == 4)
+    mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}, 
+                                {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}, 
+                                {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}, 
+                                (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
   assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]};
-  mux3  #(`FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
+  mux3  #(P.FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
 
   // unpack unit: splits FP inputs into their parts and classifies SNaN, NaN, Subnorm, Norm, Zero, Infifnity
-  unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), 
-    .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
+  unpack #(P) unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), 
+    .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE), .FPUActive(FPUActiveE),
     .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
     .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
     .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
     .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE));
   
   // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
-  fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
+  fma #(P) fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
     .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), 
     .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), .ASticky(FmaAStickyE)); 
 
   // divide and square root: fdiv, fsqrt, optionally integer division
-  fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
+  fdivsqrt #(P) fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
     .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
     .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
     .QmM, .FIntDivResultM);
 
   // compare: fmin/fmax, flt/fle/feq
-  fcmp fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), 
+  fcmp #(P) fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), 
     .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), 
     .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), 
     .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
 
   // sign injection: fsgnj/fsgnjx/fsgnjn
-  fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XPostBoxE), .Fmt(FmtE), .SgnRes(SgnResE));
+  fsgninj #(P) fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XPostBoxE), .Fmt(FmtE), .SgnRes(SgnResE));
 
   // classify: fclass
-  fclassify fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), 
+  fclassify #(P) fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), 
     .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
 
   // convert: fcvt.*.*
-  fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
+  fcvt #(P) fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
     .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
     .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
 
-
   // NaN Box SrcA to convert integer to requested FP size
-  if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
-  else if(`FPSIZES == 2) 
-    mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
-  else if(`FPSIZES == 3 | `FPSIZES == 4)
-    mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]}, 
-                            {{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]}, 
-                            {{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]}, 
-                            {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
+  if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
+  else if(P.FPSIZES == 2) 
+    mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
+  else if(P.FPSIZES == 3 | P.FPSIZES == 4)
+    mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, 
+                            {{P.FLEN-P.D_LEN{1'b1}}, ForwardedSrcAE[P.D_LEN-1:0]}, 
+                            {{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]}, 
+                            {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
 
   // select a result that may be written to the FP register
-  mux3  #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
+  mux3  #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
   assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
 
   // select the result that may be written to the integer register with fmv - to IEU
-  if(`FPSIZES == 1) begin
-    assign mvsgn = XE[`FLEN-1];
+  if(P.FPSIZES == 1) begin
+    assign mvsgn = XE[P.FLEN-1];
     assign SgnExtXE = XE;
-  end else if(`FPSIZES == 2) begin
-    mux2 #(1)     sgnmux (XE[`LEN1-1], XE[`FLEN-1],FmtE, mvsgn);
-    mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{mvsgn}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
-  end else if(`FPSIZES == 3 | `FPSIZES == 4) begin
-    mux4 #(1)     sgnmux (XE[`H_LEN-1], XE[`S_LEN-1], XE[`D_LEN-1], XE[`LLEN-1], FmtE, mvsgn);
-    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{mvsgn}}, XE[`H_LEN-1:0]}, 
-                                {{`FLEN-`S_LEN{mvsgn}}, XE[`S_LEN-1:0]}, 
-                                {{`FLEN-`D_LEN{mvsgn}}, XE[`D_LEN-1:0]}, 
+  end else if(P.FPSIZES == 2) begin
+    mux2 #(1)     sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
+    mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE);
+  end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
+    mux4 #(1)     sgnmux (XE[P.H_LEN-1], XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
+    mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]}, 
+                                {{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, 
+                                {{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]}, 
                                 XE, FmtE, SgnExtXE); 
   end
 
-  if (`FLEN>`XLEN)
-    assign IntSrcXE = SgnExtXE[`XLEN-1:0];
+  if (P.FLEN>P.XLEN)
+    assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
   else 
-    assign IntSrcXE = {{`XLEN-`FLEN{mvsgn}}, SgnExtXE};
-  mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
+    assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
+  mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
 
   // E/M pipe registers
 
   // Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
   assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE); 
 
-  flopenrc #(`NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
-  flopenrc #(`NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
-  flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
-  flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
-  flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
+  flopenrc #(P.NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
+  flopenrc #(P.NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
+  flopenrc #(P.FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
+  flopenrc #(P.XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
+  flopenrc #(P.FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
   flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM, 
     {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
     {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
   flopenrc #(1)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);      
-  flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
-  flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
+  flopenrc #(3*P.NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
+  flopenrc #($clog2(3*P.NF+5)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
     {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
     {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
-  flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
+  flopenrc #(P.NE+P.LOGCVTLEN+P.CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
     {CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
     {CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
-  flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
+  flopenrc #(P.FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Memory Stage: postprocessor and result muxes
   //////////////////////////////////////////////////////////////////////////////////////////
 
-  postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
+  postprocess #(P) postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
     .FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
     .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), 
     .FmaSm(SmM), .DivQe(QeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
@@ -336,19 +334,19 @@ module fpu (
     .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
 
   // FPU flag selection - to privileged
-  mux2  #(5)      FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
-  mux2  #(`FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
+  mux2  #(5)       FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
+  mux2  #(P.FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
 
   // M/W pipe registers
-  flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); 
-  flopenrc #(`XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); 
-  flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); 
+  flopenrc #(P.FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); 
+  flopenrc #(P.XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); 
+  flopenrc #(P.XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); 
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Writeback Stage: result mux
   //////////////////////////////////////////////////////////////////////////////////////////
 
   // select the result to be written to the FP register
-  mux2  #(`FLEN)  FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
+  mux2  #(P.FLEN)  FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
 
 endmodule // fpu
diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
index 69961a847..6ab14df20 100644
--- a/src/fpu/fregfile.sv
+++ b/src/fpu/fregfile.sv
@@ -26,17 +26,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fregfile (
+module fregfile #(parameter FLEN) (
   input logic              clk, reset,
   input logic              we4,             // write enable
   input logic [4:0]        a1, a2, a3, a4,  // adresses
-  input logic [`FLEN-1:0]  wd4,             // write data
-  output logic [`FLEN-1:0] rd1, rd2, rd3    // read data
+  input logic [FLEN-1:0]   wd4,             // write data
+  output logic [FLEN-1:0]  rd1, rd2, rd3    // read data
 );
    
-   logic [`FLEN-1:0] rf[31:0];
+   logic [FLEN-1:0] rf[31:0];
    integer i;
    
    // three ported register file
@@ -53,4 +51,3 @@ module fregfile (
    assign #2 rd3 = rf[a3];
    
 endmodule // regfile
-
diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
index f85206b41..cee13f4f9 100755
--- a/src/fpu/fsgninj.sv
+++ b/src/fpu/fsgninj.sv
@@ -26,14 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fsgninj (  
-  input  logic                Xs, Ys, // X and Y sign bits
-  input  logic [`FLEN-1:0]    X,      // X
-  input  logic [`FMTBITS-1:0] Fmt,    // format
-  input  logic [1:0]          OpCtrl, // operation control
-  output logic [`FLEN-1:0]    SgnRes  // result
+module fsgninj import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 Xs, Ys, // X and Y sign bits
+  input  logic [P.FLEN-1:0]    X,      // X
+  input  logic [P.FMTBITS-1:0] Fmt,    // format
+  input  logic [1:0]           OpCtrl, // operation control
+  output logic [P.FLEN-1:0]    SgnRes  // result
 );
 
   logic ResSgn;  // result sign
@@ -50,30 +48,29 @@ module fsgninj (
   //    - uses NaN-blocking format
   //        - if there are any unused bits the most significant bits are filled with 1s
   
-  if (`FPSIZES == 1)
-    assign SgnRes = {ResSgn, X[`FLEN-2:0]};
-  else if (`FPSIZES == 2)
-    assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
-  else if (`FPSIZES ==  3) begin
+  if (P.FPSIZES == 1)
+    assign SgnRes = {ResSgn, X[P.FLEN-2:0]};
+  else if (P.FPSIZES == 2)
+    assign SgnRes = {~Fmt|ResSgn, X[P.FLEN-2:P.LEN1], Fmt ? X[P.LEN1-1] : ResSgn, X[P.LEN1-2:0]};
+  else if (P.FPSIZES ==  3) begin
     logic [2:0] SgnBits;
     always_comb
       case (Fmt)
-        `FMT:    SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
-        `FMT1:   SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
-        `FMT2:   SgnBits = {2'b11, ResSgn};
+        P.FMT:    SgnBits = {ResSgn, X[P.LEN1-1], X[P.LEN2-1]};
+        P.FMT1:   SgnBits = {1'b1, ResSgn, X[P.LEN2-1]};
+        P.FMT2:   SgnBits = {2'b11, ResSgn};
         default: SgnBits = {3{1'bx}};
       endcase
-    assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
-  end else if (`FPSIZES == 4) begin
+    assign SgnRes = {SgnBits[2], X[P.FLEN-2:P.LEN1], SgnBits[1], X[P.LEN1-2:P.LEN2], SgnBits[0], X[P.LEN2-2:0]};
+  end else if (P.FPSIZES == 4) begin
     logic [3:0] SgnBits;
     always_comb
       case (Fmt)
-        `Q_FMT: SgnBits = {ResSgn, X[`D_LEN-1], X[`S_LEN-1], X[`H_LEN-1]};
-        `D_FMT: SgnBits = {1'b1, ResSgn, X[`S_LEN-1], X[`H_LEN-1]};
-        `S_FMT: SgnBits = {2'b11, ResSgn, X[`H_LEN-1]};
-        `H_FMT: SgnBits = {3'b111, ResSgn};
+        P.Q_FMT: SgnBits = {ResSgn, X[P.D_LEN-1], X[P.S_LEN-1], X[P.H_LEN-1]};
+        P.D_FMT: SgnBits = {1'b1, ResSgn, X[P.S_LEN-1], X[P.H_LEN-1]};
+        P.S_FMT: SgnBits = {2'b11, ResSgn, X[P.H_LEN-1]};
+        P.H_FMT: SgnBits = {3'b111, ResSgn};
       endcase
-    assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]};
+    assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
   end
-
 endmodule
diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
index 7297824f3..2cc42e54d 100644
--- a/src/fpu/postproc/cvtshiftcalc.sv
+++ b/src/fpu/postproc/cvtshiftcalc.sv
@@ -26,22 +26,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module cvtshiftcalc(
+module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
   input  logic                    XZero,              // is the input zero?
   input  logic                    ToInt,              // to integer conversion?
   input  logic                    IntToFp,            // interger to floating point conversion?
-  input  logic [`FMTBITS-1:0]     OutFmt,             // output format
-  input  logic [`NE:0]            CvtCe,              // the calculated expoent
-  input  logic [`NF:0]            Xm,                 // input mantissas
-  input  logic [`CVTLEN-1:0]      CvtLzcIn,           // input to the Leading Zero Counter (without msb)
+  input  logic [P.FMTBITS-1:0]     OutFmt,             // output format
+  input  logic [P.NE:0]            CvtCe,              // the calculated expoent
+  input  logic [P.NF:0]            Xm,                 // input mantissas
+  input  logic [P.CVTLEN-1:0]      CvtLzcIn,           // input to the Leading Zero Counter (without msb)
   input  logic                    CvtResSubnormUf,    // is the conversion result subnormal or underlows
   output logic                    CvtResUf,           // does the cvt result unerflow
-  output logic [`CVTLEN+`NF:0]    CvtShiftIn          // number to be shifted
+  output logic [P.CVTLEN+P.NF:0]    CvtShiftIn          // number to be shifted
 );
 
-  logic [$clog2(`NF):0]           ResNegNF;           // the result's fraction length negated (-NF)
+  logic [$clog2(P.NF):0]           ResNegNF;           // the result's fraction length negated (-NF)
 
   ///////////////////////////////////////////////////////////////////////////
   // shifter
@@ -49,7 +47,7 @@ module cvtshiftcalc(
 
   // seclect the input to the shifter
   //      fp  -> int:
-  //          |  `XLEN  zeros |     mantissa      | 0's if nessisary |
+  //          |  P.XLEN  zeros |     mantissa      | 0's if nessisary |
   //                          .
   //          Other problems:
   //              - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding)
@@ -57,7 +55,7 @@ module cvtshiftcalc(
   //                  - ex: for the case 0010000.... (double)
   //      ??? -> fp:
   //          - if result is subnormal or underflowed then we want to shift right i.e. shift right then shift left:
-  //              |  `NF-1  zeros   |     mantissa      | 0's if nessisary | 
+  //              |  P.NF-1  zeros   |     mantissa      | 0's if nessisary | 
   //              .
   //          - otherwise:
   //              |     LzcInM      | 0's if nessisary | 
@@ -67,33 +65,33 @@ module cvtshiftcalc(
   //                                                        get rid of round bit if needed
   //                                                        |                    add sticky bit if needed
   //                                                        |                    |
-      if (ToInt)               CvtShiftIn = {{`XLEN{1'b0}}, Xm[`NF]&~CvtCe[`NE], Xm[`NF-1]|(CvtCe[`NE]&Xm[`NF]), Xm[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}};
-      else if (CvtResSubnormUf) CvtShiftIn = {{`NF-1{1'b0}}, Xm, {`CVTLEN-`NF+1{1'b0}}};
-      else                     CvtShiftIn = {CvtLzcIn, {`NF+1{1'b0}}};
+      if (ToInt)               CvtShiftIn = {{P.XLEN{1'b0}}, Xm[P.NF]&~CvtCe[P.NE], Xm[P.NF-1]|(CvtCe[P.NE]&Xm[P.NF]), Xm[P.NF-2:0], {P.CVTLEN-P.XLEN{1'b0}}};
+      else if (CvtResSubnormUf) CvtShiftIn = {{P.NF-1{1'b0}}, Xm, {P.CVTLEN-P.NF+1{1'b0}}};
+      else                     CvtShiftIn = {CvtLzcIn, {P.NF+1{1'b0}}};
   
   // choose the negative of the fraction size
-  if (`FPSIZES == 1) begin
-      assign ResNegNF = -($clog2(`NF)+1)'(`NF); 
+  if (P.FPSIZES == 1) begin
+      assign ResNegNF = -($clog2(P.NF)+1)'(P.NF); 
 
-  end else if (`FPSIZES == 2) begin
-      assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1);
+  end else if (P.FPSIZES == 2) begin
+      assign ResNegNF = OutFmt ? -($clog2(P.NF)+1)'(P.NF) : -($clog2(P.NF)+1)'(P.NF1);
 
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              `FMT:  ResNegNF = -($clog2(`NF)+1)'(`NF);
-              `FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1);
-              `FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2);
-              default: ResNegNF = 1'bx;
+              P.FMT:  ResNegNF = -($clog2(P.NF)+1)'(P.NF);
+              P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
+              P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
+              default: ResNegNF = 'x;
           endcase
 
-  end else if (`FPSIZES == 4) begin        
+  end else if (P.FPSIZES == 4) begin        
       always_comb
           case (OutFmt)
-              2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF);
-              2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF);
-              2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF);
-              2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF);
+              2'h3: ResNegNF = -($clog2(P.NF)+1)'(P.Q_NF);
+              2'h1: ResNegNF = -($clog2(P.NF)+1)'(P.D_NF);
+              2'h0: ResNegNF = -($clog2(P.NF)+1)'(P.S_NF);
+              2'h2: ResNegNF = -($clog2(P.NF)+1)'(P.H_NF);
           endcase
   end
 
@@ -102,6 +100,6 @@ module cvtshiftcalc(
   // determine if the result underflows ??? -> fp
   //      - if the first 1 is shifted out of the result then the result underflows
   //      - can't underflow an integer to fp conversions
-  assign CvtResUf = ($signed(CvtCe) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp;
+  assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp;
   
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
index 76668516c..8ac85b992 100644
--- a/src/fpu/postproc/divshiftcalc.sv
+++ b/src/fpu/postproc/divshiftcalc.sv
@@ -26,24 +26,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh"
 
-`include "wally-config.vh"
-
-module divshiftcalc(
-  input  logic [`DIVb:0]              DivQm,              // divsqrt significand
-  input  logic [`NE+1:0]              DivQe,              // divsqrt exponent
-  output logic [`LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
-  output logic [`NORMSHIFTSZ-1:0]     DivShiftIn,         // divsqrt shift input
+module divshiftcalc import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.DIVb:0]              DivQm,              // divsqrt significand
+  input  logic [P.NE+1:0]              DivQe,              // divsqrt exponent
+  output logic [P.LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
+  output logic [P.NORMSHIFTSZ-1:0]     DivShiftIn,         // divsqrt shift input
   output logic                        DivResSubnorm,      // is the divsqrt result subnormal
   output logic                        DivSubnormShiftPos  // is the subnormal shift amount positive
 );
 
-  logic [`LOGNORMSHIFTSZ-1:0]         NormShift;          // normalized result shift amount
-  logic [`LOGNORMSHIFTSZ-1:0]         DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
-  logic [`NE+1:0]                     DivSubnormShift;    // subnormal result shift amount
+  logic [P.LOGNORMSHIFTSZ-1:0]         NormShift;          // normalized result shift amount
+  logic [P.LOGNORMSHIFTSZ-1:0]         DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
+  logic [P.NE+1:0]                     DivSubnormShift;    // subnormal result shift amount
 
   // is the result subnormal
   // if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
-  assign DivResSubnorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
+  assign DivResSubnorm = DivQe[P.NE+1]|(~|DivQe[P.NE+1:0]);
 
   // if the result is subnormal
   //  00000000x.xxxxxx...                     Exp = DivQe
@@ -51,8 +49,8 @@ module divshiftcalc(
   //  .00xxxxxxxxxxxxx... << DivQe+NF+1  Exp = +1
   //  .0000xxxxxxxxxxx... >> 1                Exp = 1
   // Left shift amount  = DivQe+NF+1-1
-  assign DivSubnormShift = (`NE+2)'(`NF)+DivQe;
-  assign DivSubnormShiftPos = ~DivSubnormShift[`NE+1];
+  assign DivSubnormShift = (P.NE+2)'(P.NF)+DivQe;
+  assign DivSubnormShiftPos = ~DivSubnormShift[P.NE+1];
 
   // if the result is normalized
   //  00000000x.xxxxxx...                     Exp = DivQe
@@ -62,13 +60,13 @@ module divshiftcalc(
   //  00000000xx.xxxxx... << 1?               Exp = DivQe-1 (determined after)
   // inital Left shift amount  = NF
   // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
-  assign NormShift = (`LOGNORMSHIFTSZ)'(`NF);
+  assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
 
   // if the shift amount is negitive then don't shift (keep sticky bit)
   // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[`LOGNORMSHIFTSZ-1:0] : '0;
+  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
   assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
 
   // pre-shift the divider result for normalization
-  assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb-1-`NF{1'b0}}};
+  assign DivShiftIn = {{P.NF{1'b0}}, DivQm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
 endmodule
diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv
index 701cf0524..d5745391f 100644
--- a/src/fpu/postproc/flags.sv
+++ b/src/fpu/postproc/flags.sv
@@ -25,18 +25,17 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module flags(
+module flags import cvw::*;  #(parameter cvw_t P) (
   input  logic                Xs,                     // X sign
-  input  logic [`FMTBITS-1:0] OutFmt,                 // output format
+  input  logic [P.FMTBITS-1:0] OutFmt,                 // output format
   input  logic                InfIn,                  // is a Inf input being used
   input  logic                XInf, YInf, ZInf,       // inputs are infinity
   input  logic                NaNIn,                  // is a NaN input being used
   input  logic                XSNaN, YSNaN, ZSNaN,    // inputs are signaling NaNs
   input  logic                XZero, YZero,           // inputs are zero
-  input  logic [`NE+1:0]      FullRe,                 // Re with bits to determine sign and overflow
-  input  logic [`NE+1:0]      Me,                     // exponent of the normalized sum
+  input  logic [P.NE+1:0]      FullRe,                 // Re with bits to determine sign and overflow
+  input  logic [P.NE+1:0]      Me,                     // exponent of the normalized sum
   // rounding
   input  logic                Plus1,                  // do you add one for rounding
   input  logic                Round, Guard, Sticky,   // bits used to determine rounding
@@ -47,7 +46,7 @@ module flags(
   input  logic                IntToFp,                // convert integer to floating point
   input  logic                Int64,                  // convert to 64 bit integer
   input  logic                Signed,                 // convert to a signed integer
-  input  logic [`NE:0]        CvtCe,                  // the calculated expoent - Cvt
+  input  logic [P.NE:0]        CvtCe,                  // the calculated expoent - Cvt
   input  logic [1:0]          CvtNegResMsbs,          // the negitive integer result's most significant bits
   // divsqrt
   input  logic                DivOp,                  // conversion opperation?
@@ -92,33 +91,33 @@ module flags(
   //          - any of the bits after the most significan 1 is one
   //          - the most signifcant in 65 or 33 is still a one in the number and
   //            one of the later bits is one
-  if (`FPSIZES == 1) begin
-      assign ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE];
-      assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+  if (P.FPSIZES == 1) begin
+      assign ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE];
+      assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
 
-  end else if (`FPSIZES == 2) begin    
-      assign ResExpGteMax = OutFmt ? &FullRe[`NE-1:0] | FullRe[`NE] : &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]);
+  end else if (P.FPSIZES == 2) begin    
+      assign ResExpGteMax = OutFmt ? &FullRe[P.NE-1:0] | FullRe[P.NE] : &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
 
-      assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
-  end else if (`FPSIZES == 3) begin
+      assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+  end else if (P.FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              `FMT: ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE];
-              `FMT1: ResExpGteMax = &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]);
-              `FMT2: ResExpGteMax = &FullRe[`NE2-1:0] | (|FullRe[`NE:`NE2]);
+              P.FMT: ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE];
+              P.FMT1: ResExpGteMax = &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
+              P.FMT2: ResExpGteMax = &FullRe[P.NE2-1:0] | (|FullRe[P.NE:P.NE2]);
               default: ResExpGteMax = 1'bx;
           endcase
-          assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+          assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
 
-  end else if (`FPSIZES == 4) begin        
+  end else if (P.FPSIZES == 4) begin        
       always_comb
           case (OutFmt)
-              `Q_FMT: ResExpGteMax = &FullRe[`Q_NE-1:0] | FullRe[`Q_NE];
-              `D_FMT: ResExpGteMax = &FullRe[`D_NE-1:0] | (|FullRe[`Q_NE:`D_NE]);
-              `S_FMT: ResExpGteMax = &FullRe[`S_NE-1:0] | (|FullRe[`Q_NE:`S_NE]);
-              `H_FMT: ResExpGteMax = &FullRe[`H_NE-1:0] | (|FullRe[`Q_NE:`H_NE]);
+              P.Q_FMT: ResExpGteMax = &FullRe[P.Q_NE-1:0] | FullRe[P.Q_NE];
+              P.D_FMT: ResExpGteMax = &FullRe[P.D_NE-1:0] | (|FullRe[P.Q_NE:P.D_NE]);
+              P.S_FMT: ResExpGteMax = &FullRe[P.S_NE-1:0] | (|FullRe[P.Q_NE:P.S_NE]);
+              P.H_FMT: ResExpGteMax = &FullRe[P.H_NE-1:0] | (|FullRe[P.Q_NE:P.H_NE]);
           endcase
-          assign ShiftGtIntSz = (|FullRe[`Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+          assign ShiftGtIntSz = (|FullRe[P.Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
   end
 
 
@@ -127,7 +126,7 @@ module flags(
   //                 |           and the exponent isn't negitive
   //                 |           |                   if the input isnt infinity or NaN
   //                 |           |                   |            
-  assign Overflow = ResExpGteMax & ~FullRe[`NE+1]&~(InfIn|NaNIn|DivByZero);
+  assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero);
 
   ///////////////////////////////////////////////////////////////////////////////
   // Underflow
@@ -141,7 +140,7 @@ module flags(
   //                  |                    |                    |                                      |                     and if the result is not exact
   //                  |                    |                    |                                      |                     |               and if the input isnt infinity or NaN
   //                  |                    |                    |                                      |                     |               |
-  assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
+  assign Underflow = ((FullRe[P.NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
 
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -156,7 +155,7 @@ module flags(
   //                  if the res is too small to be represented and not 0
   //                  |                                     and if the res is not invalid (outside the integer bounds)
   //                  |                                     |
-  assign IntInexact = ((CvtCe[`NE]&~XZero)|Sticky|Round|Guard)&~IntInvalid;
+  assign IntInexact = ((CvtCe[P.NE]&~XZero)|Sticky|Round|Guard)&~IntInvalid;
 
   // select the inexact flag to output
   assign Inexact = ToInt ? IntInexact : FpInexact;
@@ -178,7 +177,7 @@ module flags(
   //                  |           |                                  |                    |               or the res rounds up out of bounds
   //                  |           |                                  |                    |                       and the res didn't underflow
   //                  |           |                                  |                    |                       |
-  assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
+  assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[P.NE+1])|((Xs&~Signed)&(~((CvtCe[P.NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
   //                                                                                                     |
   //                                                                                                     or when the positive res rounds up out of range
   
diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
index dabf0dfde..41fb84309 100644
--- a/src/fpu/postproc/fmashiftcalc.sv
+++ b/src/fpu/postproc/fmashiftcalc.sv
@@ -26,21 +26,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module fmashiftcalc(
-  input  logic [`FMTBITS-1:0]         Fmt,            // precision 1 = double 0 = single
-  input  logic [`NE+1:0]              FmaSe,          // sum's exponent
-  input  logic [3*`NF+3:0]            FmaSm,          // the positive sum
-  input  logic [$clog2(3*`NF+5)-1:0]  FmaSCnt,        // normalization shift count
-  output logic [`NE+1:0]              NormSumExp,     // exponent of the normalized sum not taking into account Subnormal or zero results
+module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0]         Fmt,            // precision 1 = double 0 = single
+  input  logic [P.NE+1:0]              FmaSe,          // sum's exponent
+  input  logic [3*P.NF+3:0]            FmaSm,          // the positive sum
+  input  logic [$clog2(3*P.NF+5)-1:0]  FmaSCnt,        // normalization shift count
+  output logic [P.NE+1:0]              NormSumExp,     // exponent of the normalized sum not taking into account Subnormal or zero results
   output logic                        FmaSZero,       // is the result subnormal - calculated before LZA corection
   output logic                        FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
-  output logic [$clog2(3*`NF+5)-1:0]  FmaShiftAmt,    // normalization shift count
-  output logic [3*`NF+5:0]            FmaShiftIn      // is the sum zero
+  output logic [$clog2(3*P.NF+5)-1:0]  FmaShiftAmt,    // normalization shift count
+  output logic [3*P.NF+5:0]            FmaShiftIn      // is the sum zero
 );
-  logic [`NE+1:0] PreNormSumExp;  // the exponent of the normalized sum with the `FLEN bias
-  logic [`NE+1:0] BiasCorr;       // correction for bias
+  logic [P.NE+1:0] PreNormSumExp;  // the exponent of the normalized sum with the P.FLEN bias
+  logic [P.NE+1:0] BiasCorr;       // correction for bias
 
   ///////////////////////////////////////////////////////////////////////////////
   // Normalization
@@ -50,75 +48,75 @@ module fmashiftcalc(
   assign FmaSZero = ~(|FmaSm);
 
   // calculate the sum's exponent
-  assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+5)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);
+  assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(3*P.NF+5)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+3);
 
   //convert the sum's exponent into the proper percision
-  if (`FPSIZES == 1) begin
+  if (P.FPSIZES == 1) begin
     assign NormSumExp = PreNormSumExp;
-  end else if (`FPSIZES == 2) begin
-    assign BiasCorr = Fmt ? (`NE+2)'(0) : (`NE+2)'(`BIAS1-`BIAS);
+  end else if (P.FPSIZES == 2) begin
+    assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS);
     assign NormSumExp = PreNormSumExp+BiasCorr;
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
     always_comb begin
         case (Fmt)
-            `FMT: BiasCorr =  '0;
-            `FMT1: BiasCorr = (`NE+2)'(`BIAS1-`BIAS);
-            `FMT2: BiasCorr = (`NE+2)'(`BIAS2-`BIAS);
+            P.FMT: BiasCorr =  '0;
+            P.FMT1: BiasCorr = (P.NE+2)'(P.BIAS1-P.BIAS);
+            P.FMT2: BiasCorr = (P.NE+2)'(P.BIAS2-P.BIAS);
             default: BiasCorr = 'x;
         endcase
     end
     assign NormSumExp = PreNormSumExp+BiasCorr;
-  end else if (`FPSIZES == 4) begin
+  end else if (P.FPSIZES == 4) begin
     always_comb begin
         case (Fmt)
             2'h3: BiasCorr = '0;
-            2'h1: BiasCorr = (`NE+2)'(`D_BIAS-`Q_BIAS);
-            2'h0: BiasCorr = (`NE+2)'(`S_BIAS-`Q_BIAS);
-            2'h2: BiasCorr = (`NE+2)'(`H_BIAS-`Q_BIAS);
+            2'h1: BiasCorr = (P.NE+2)'(P.D_BIAS-P.Q_BIAS);
+            2'h0: BiasCorr = (P.NE+2)'(P.S_BIAS-P.Q_BIAS);
+            2'h2: BiasCorr = (P.NE+2)'(P.H_BIAS-P.Q_BIAS);
         endcase
     end
     assign NormSumExp = PreNormSumExp+BiasCorr;
   end
   
   // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero
-  if (`FPSIZES == 1) begin
+  if (P.FPSIZES == 1) begin
     logic Sum0LEZ, Sum0GEFL;
-    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
+    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
     assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
-  end else if (`FPSIZES == 2) begin
+  end else if (P.FPSIZES == 2) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
-    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp;
+    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
     assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
-    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp;
-    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS2));
-    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF2-2+`BIAS-`BIAS2)) | ~|PreNormSumExp;
+    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
+    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
+    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
     always_comb begin
       case (Fmt)
-        `FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
-        `FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero;
-        `FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero;
+        P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
+        P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero;
+        P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero;
         default: FmaPreResultSubnorm = 1'bx;
       endcase
     end
-  end else if (`FPSIZES == 4) begin
+  end else if (P.FPSIZES == 4) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
-    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`D_BIAS));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`D_NF-2+`BIAS-`D_BIAS)) | ~|PreNormSumExp;
-    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`S_BIAS));
-    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`S_NF-2+`BIAS-`S_BIAS)) | ~|PreNormSumExp;
-    assign Sum3LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`H_BIAS));
-    assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`H_NF-2+`BIAS-`H_BIAS)) | ~|PreNormSumExp;
+    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-2+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
+    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
+    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-2+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
+    assign Sum3LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
+    assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-2+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
     always_comb begin
       case (Fmt)
         2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
@@ -132,6 +130,6 @@ module fmashiftcalc(
   // set and calculate the shift input and amount
   //  - shift once if killing a product and the result is subnormal
   assign FmaShiftIn = {2'b0, FmaSm};
-  if (`FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;
-  else               assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2)+BiasCorr[$clog2(3*`NF+5)-1:0]: FmaSCnt+1;
+  if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+2): FmaSCnt+1;
+  else               assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+2)+BiasCorr[$clog2(3*P.NF+5)-1:0]: FmaSCnt+1;
 endmodule
diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv
index 939bcc335..069a1a2b9 100644
--- a/src/fpu/postproc/negateintres.sv
+++ b/src/fpu/postproc/negateintres.sv
@@ -25,26 +25,25 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module negateintres(
+module negateintres import cvw::*;  #(parameter cvw_t P) (
   input  logic                    Signed,         // is the integer input signed
   input  logic                    Int64,          // is the integer input 64-bits
   input  logic                    Plus1,          // should one be added for rounding?
   input  logic                    Xs,             // X sign
-  input  logic [`NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
+  input  logic [P.NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
   output logic [1:0]              CvtNegResMsbs,  // most signigficant bits of possibly negated result
-  output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
+  output logic [P.XLEN+1:0]        CvtNegRes       // possibly negated integer result
 );
 
-  logic [`XLEN+1:0]               CvtPreRes;      // integer result with rounding
+  logic [P.XLEN+1:0]               CvtPreRes;      // integer result with rounding
   logic [2:0]                     CvtNegResMsbs3; // first three msbs of possibly negated result
     
   // round and negate the positive res if needed
-  assign CvtPreRes =  {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
-  mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
+  assign CvtPreRes =  {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
+  mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
     
   // select 2 most significant bits
-  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
+  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[P.XLEN+1:P.XLEN-1], Int64, CvtNegResMsbs3);
   mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv
index 44469e316..f80230219 100644
--- a/src/fpu/postproc/normshift.sv
+++ b/src/fpu/postproc/normshift.sv
@@ -25,8 +25,6 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
-
 
     // convert shift
     //      fp -> int: |  `XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
@@ -72,11 +70,11 @@
     //      | Nf 0's |      Qm       | << calculated shift amount
     //        .
 
-module normshift(
-  input  logic [`LOGNORMSHIFTSZ-1:0]  ShiftAmt,   // shift amount
-  input  logic [`NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
-  output logic [`NORMSHIFTSZ-1:0]     Shifted     // shifted result
+module normshift import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.LOGNORMSHIFTSZ-1:0]  ShiftAmt,   // shift amount
+  input  logic [P.NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
+  output logic [P.NORMSHIFTSZ-1:0]     Shifted     // shifted result
 );
    
   assign Shifted = ShiftIn << ShiftAmt;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
index 07723d7f1..be06fbdd3 100644
--- a/src/fpu/postproc/postprocess.sv
+++ b/src/fpu/postproc/postprocess.sv
@@ -26,14 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module postprocess (
+module postprocess import cvw::*;  #(parameter cvw_t P) (
   // general signals
   input logic                             Xs, Ys,     // input signs
-  input logic  [`NF:0]                    Xm, Ym, Zm, // input mantissas
+  input logic  [P.NF:0]                    Xm, Ym, Zm, // input mantissas
   input logic  [2:0]                      Frm,        // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
-  input logic  [`FMTBITS-1:0]             Fmt,        // precision 1 = double 0 = single
+  input logic  [P.FMTBITS-1:0]             Fmt,        // precision 1 = double 0 = single
   input logic  [2:0]                      OpCtrl,     // choose which opperation (look below for values)
   input logic                             XZero, YZero,        // inputs are zero
   input logic                             XInf, YInf, ZInf,    // inputs are infinity
@@ -44,63 +42,63 @@ module postprocess (
   input logic                             FmaAs,      // the modified Z sign - depends on instruction
   input logic                             FmaPs,      // the product's sign
   input logic                             FmaSs,      // Sum sign
-  input logic  [`NE+1:0]                  FmaSe,      // the sum's exponent
-  input logic  [3*`NF+3:0]                FmaSm,      // the positive sum
+  input logic  [P.NE+1:0]                  FmaSe,      // the sum's exponent
+  input logic  [3*P.NF+3:0]                FmaSm,      // the positive sum
   input logic                             FmaASticky, // sticky bit that is calculated during alignment
-  input logic  [$clog2(3*`NF+5)-1:0]      FmaSCnt,    // the normalization shift count
+  input logic  [$clog2(3*P.NF+5)-1:0]      FmaSCnt,    // the normalization shift count
   //divide signals
   input logic                             DivSticky,  // divider sticky bit
-  input logic  [`NE+1:0]                  DivQe,      // divsqrt exponent
-  input logic  [`DIVb:0]                  DivQm,      // divsqrt significand
+  input logic  [P.NE+1:0]                  DivQe,      // divsqrt exponent
+  input logic  [P.DIVb:0]                  DivQm,      // divsqrt significand
   // conversion signals
   input logic                             CvtCs,      // the result's sign
-  input logic  [`NE:0]                    CvtCe,      // the calculated expoent
+  input logic  [P.NE:0]                    CvtCe,      // the calculated expoent
   input logic                             CvtResSubnormUf, // the convert result is subnormal or underflows
-  input logic  [`LOGCVTLEN-1:0]           CvtShiftAmt,// how much to shift by
+  input logic  [P.LOGCVTLEN-1:0]           CvtShiftAmt,// how much to shift by
   input logic                             ToInt,      // is fp->int (since it's writting to the integer register)
-  input logic  [`CVTLEN-1:0]              CvtLzcIn,   // input to the Leading Zero Counter (without msb)
+  input logic  [P.CVTLEN-1:0]              CvtLzcIn,   // input to the Leading Zero Counter (without msb)
   input logic                             IntZero,    // is the integer input zero
   // final results
-  output logic [`FLEN-1:0]                PostProcRes,// postprocessor final result
+  output logic [P.FLEN-1:0]                PostProcRes,// postprocessor final result
   output logic [4:0]                      PostProcFlg,// postprocesser flags
-  output logic [`XLEN-1:0]                FCvtIntRes  // the integer conversion result
+  output logic [P.XLEN-1:0]                FCvtIntRes  // the integer conversion result
   );
   
   // general signals
   logic                       Rs;         // result sign
-  logic [`NF-1:0]             Rf;         // Result fraction
-  logic [`NE-1:0]             Re;         // Result exponent
+  logic [P.NF-1:0]             Rf;         // Result fraction
+  logic [P.NE-1:0]             Re;         // Result exponent
   logic                       Ms;         // norMalized sign
-  logic [`CORRSHIFTSZ-1:0]    Mf;         // norMalized fraction
-  logic [`NE+1:0]             Me;         // normalized exponent
-  logic [`NE+1:0]             FullRe;     // Re with bits to determine sign and overflow
+  logic [P.CORRSHIFTSZ-1:0]    Mf;         // norMalized fraction
+  logic [P.NE+1:0]             Me;         // normalized exponent
+  logic [P.NE+1:0]             FullRe;     // Re with bits to determine sign and overflow
   logic                       UfPlus1;    // do you add one (for determining underflow flag)
-  logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift amount
-  logic [`NORMSHIFTSZ-1:0]    ShiftIn;    // input to normalization shift
-  logic [`NORMSHIFTSZ-1:0]    Shifted;    // the ouput of the normalized shifter (before shift correction)
+  logic [P.LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift amount
+  logic [P.NORMSHIFTSZ-1:0]    ShiftIn;    // input to normalization shift
+  logic [P.NORMSHIFTSZ-1:0]    Shifted;    // the ouput of the normalized shifter (before shift correction)
   logic                       Plus1;      // add one to the final result?
   logic                       Overflow;   // overflow flag used to select results
   logic                       Invalid;    // invalid flag used to select results
   logic                       Guard, Round, Sticky; // bits needed to determine rounding
-  logic [`FMTBITS-1:0]        OutFmt;     // output format
+  logic [P.FMTBITS-1:0]        OutFmt;     // output format
   // fma signals
-  logic [`NE+1:0]             FmaMe;      // exponent of the normalized sum
+  logic [P.NE+1:0]             FmaMe;      // exponent of the normalized sum
   logic                       FmaSZero;   // is the sum zero
-  logic [3*`NF+5:0]           FmaShiftIn; // fma shift input
-  logic [`NE+1:0]             NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
+  logic [3*P.NF+5:0]           FmaShiftIn; // fma shift input
+  logic [P.NE+1:0]             NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
   logic                       FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
-  logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
+  logic [$clog2(3*P.NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
   // division singals
-  logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;        // divsqrt shif amount
-  logic [`NORMSHIFTSZ-1:0]    DivShiftIn;         // divsqrt shift input
-  logic [`NE+1:0]             Qe;                 // divsqrt corrected exponent after corretion shift
+  logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt;        // divsqrt shif amount
+  logic [P.NORMSHIFTSZ-1:0]    DivShiftIn;         // divsqrt shift input
+  logic [P.NE+1:0]             Qe;                 // divsqrt corrected exponent after corretion shift
   logic                       DivByZero;          // divide by zero flag
   logic                       DivResSubnorm;      // is the divsqrt result subnormal
   logic                       DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
   // conversion signals
-  logic [`CVTLEN+`NF:0]       CvtShiftIn;         // number to be shifted for converter
+  logic [P.CVTLEN+P.NF:0]       CvtShiftIn;         // number to be shifted for converter
   logic [1:0]                 CvtNegResMsbs;      // most significant bits of possibly negated int result
-  logic [`XLEN+1:0]           CvtNegRes;          // possibly negated integer result
+  logic [P.XLEN+1:0]           CvtNegRes;          // possibly negated integer result
   logic                       CvtResUf;           // did the convert result underflow
   logic                       IntInvalid;         // invalid integer flag
   // readability signals
@@ -132,9 +130,9 @@ module postprocess (
   // choose the ouptut format depending on the opperation
   //      - fp -> fp: OpCtrl contains the percision of the output
   //      - otherwise: Fmt contains the percision of the output
-  if (`FPSIZES == 2) 
-      assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == `FMT); 
-  else if (`FPSIZES == 3 | `FPSIZES == 4) 
+  if (P.FPSIZES == 2) 
+      assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT); 
+  else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
       assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; 
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -142,40 +140,40 @@ module postprocess (
   ///////////////////////////////////////////////////////////////////////////////
 
   // final claulations before shifting
-  cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
+  cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
       .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
 
-  fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
+  fmashiftcalc #(P) fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
       .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
 
-  divshiftcalc divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
+  divshiftcalc #(P) divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
 
   // select which unit's output to shift
   always_comb
     case(PostProcSel)
       2'b10: begin // fma
-        ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+5){1'b0}}, FmaShiftAmt};
-        ShiftIn =  {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+6){1'b0}}};
+        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(3*P.NF+5){1'b0}}, FmaShiftAmt};
+        ShiftIn =  {FmaShiftIn, {P.NORMSHIFTSZ-(3*P.NF+6){1'b0}}};
       end
       2'b00: begin // cvt
-        ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
-        ShiftIn =  {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}};
+        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
+        ShiftIn =  {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}};
       end
       2'b01: begin //divsqrt
         ShiftAmt = DivShiftAmt;
         ShiftIn =  DivShiftIn;
       end
       default: begin 
-        ShiftAmt = {`LOGNORMSHIFTSZ{1'bx}}; 
-        ShiftIn = {`NORMSHIFTSZ{1'bx}}; 
+        ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; 
+        ShiftIn = {P.NORMSHIFTSZ{1'bx}}; 
       end
     endcase
   
   // main normalization shift
-  normshift normshift (.ShiftIn, .ShiftAmt, .Shifted);
+  normshift #(P) normshift (.ShiftIn, .ShiftAmt, .Shifted);
 
   // correct for LZA/divsqrt error
-  shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
+  shiftcorrection #(P) shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
       .DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivQe, .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -191,7 +189,7 @@ module postprocess (
   // calulate result sign used in rounding unit
   roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
 
-  round round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
+  round #(P) round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
       .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt,  .CvtResUf,
       .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
 
@@ -206,7 +204,7 @@ module postprocess (
   // Flags
   ///////////////////////////////////////////////////////////////////////////////
 
-  flags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero, 
+  flags #(P) flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero, 
               .Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
               .NaNIn, .FmaAs, .FmaPs, .Round, .IntInvalid, .DivByZero,
               .Guard, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
@@ -216,9 +214,9 @@ module postprocess (
   // Select the result
   ///////////////////////////////////////////////////////////////////////////////
 
-  negateintres negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
+  negateintres #(P) negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
 
-  specialcase specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid,
+  specialcase #(P) specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid,
       .IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf, 
       .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes,
       .XInf, .YInf, .DivOp, .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv
index 7eeba9e8a..9701cb7a6 100644
--- a/src/fpu/postproc/resultsign.sv
+++ b/src/fpu/postproc/resultsign.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module resultsign(
   input  logic [2:0]  Frm,        // rounding mode
   input  logic        FmaOp,      // is the operation an Fma
@@ -77,4 +75,4 @@ module resultsign(
     else if(FmaSZero&FmaOp) Rs = Zeros;
     else                    Rs = Ms;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
index c1914bb53..4f6ea819d 100644
--- a/src/fpu/postproc/round.sv
+++ b/src/fpu/postproc/round.sv
@@ -26,42 +26,32 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-// what position is XLEN in?
-//  options: 
-//     1: XLEN > NF   > NF1
-//     2: NF   > XLEN > NF1
-//     3: NF   > NF1  > XLEN
-//  single and double will always be smaller than XLEN
-`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
-
-module round(
-  input  logic [`FMTBITS-1:0]     OutFmt,             // output format
+module round import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0]     OutFmt,             // output format
   input  logic [2:0]              Frm,                // rounding mode
   input  logic [1:0]              PostProcSel,        // select the postprocessor output
   input  logic                    Ms,                 // normalized sign
-  input  logic [`CORRSHIFTSZ-1:0] Mf,                 // normalized fraction
+  input  logic [P.CORRSHIFTSZ-1:0] Mf,                 // normalized fraction
   // fma
   input  logic                    FmaOp,              // is an fma opperation being done?
-  input  logic [`NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
+  input  logic [P.NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
   input  logic                    FmaASticky,         // addend's sticky bit
   // divsqrt
   input  logic                    DivOp,              // is a division opperation being done
   input  logic                    DivSticky,          // divsqrt sticky bit
-  input  logic [`NE+1:0]          Qe,                 // the divsqrt calculated expoent
+  input  logic [P.NE+1:0]          Qe,                 // the divsqrt calculated expoent
   // cvt
   input  logic                    CvtOp,              // is a convert opperation being done
   input  logic                    ToInt,              // is the cvt op a cvt to integer
   input  logic                    CvtResSubnormUf,    // is the cvt result subnormal or underflow
   input  logic                    CvtResUf,           // does the cvt result underflow
-  input  logic [`NE:0]            CvtCe,              // the cvt calculated expoent
+  input  logic [P.NE:0]            CvtCe,              // the cvt calculated expoent
   // outputs
-  output logic [`NE+1:0]          Me,                 // normalied fraction
+  output logic [P.NE+1:0]          Me,                 // normalied fraction
   output logic                    UfPlus1,            // do you add one to the result if given an unbounded exponent
-  output logic [`NE+1:0]          FullRe,             // Re with bits to determine sign and overflow
-  output logic [`NE-1:0]          Re,                 // Result exponent
-  output logic [`NF-1:0]          Rf,                 // Result fractionNormS
+  output logic [P.NE+1:0]          FullRe,             // Re with bits to determine sign and overflow
+  output logic [P.NE-1:0]          Re,                 // Result exponent
+  output logic [P.NF-1:0]          Rf,                 // Result fractionNormS
   output logic                    Sticky,             // sticky bit
   output logic                    Plus1,              // do you add one to the final result
   output logic                    Round, Guard        // bits needed to calculate rounding
@@ -69,7 +59,7 @@ module round(
 
   logic           UfCalcPlus1;        // calculated plus one for unbounded exponent
   logic           NormSticky;         // normalized sum's sticky bit
-  logic [`NF-1:0] RoundFrac;          // rounded fraction
+  logic [P.NF-1:0] RoundFrac;          // rounded fraction
   logic           FpRes;              // is the result a floating point
   logic           IntRes;             // is the result an integer
   logic           FpGuard, FpRound;   // floating point round/guard bits
@@ -77,8 +67,17 @@ module round(
   logic           LsbRes;             // lsb of result
   logic           CalcPlus1;          // calculated plus1
   logic           FpPlus1;            // do you add one to the fp result 
-  logic [`FLEN:0] RoundAdd;           // how much to add to the result
+  logic [P.FLEN:0] RoundAdd;           // how much to add to the result
 
+// what position is XLEN in?
+//  options: 
+//     1: XLEN > NF   > NF1
+//     2: NF   > XLEN > NF1
+//     3: NF   > NF1  > XLEN
+//  single and double will always be smaller than XLEN
+//`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
+  localparam XLENPOS = P.XLEN > P.NF ? 1 : P.XLEN > P.NF1 ? 2 : 3;
+  
   ///////////////////////////////////////////////////////////////////////////////
   // Rounding
   ///////////////////////////////////////////////////////////////////////////////
@@ -115,68 +114,68 @@ module round(
   assign FpRes = ~IntRes;
 
   // sticky bit calculation
-  if (`FPSIZES == 1) begin
+  if (P.FPSIZES == 1) begin
 
       //     1: XLEN > NF
       //      |         XLEN          |
       //      |    NF     |1|1|
       //                     ^    ^ if floating point result
       //                     ^ if not an FMA result
-      if (`XLENPOS == 1)assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      if (XLENPOS == 1)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
       //     2: NF > XLEN
-      if (`XLENPOS == 2)assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&IntRes) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      if (XLENPOS == 2)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&IntRes) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
 
-  end else if (`FPSIZES == 2) begin
+  end else if (P.FPSIZES == 2) begin
       // XLEN is either 64 or 32
       // so half and single are always smaller then XLEN
 
       // 1: XLEN > NF   > NF1
-      if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~OutFmt) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
       // 2: NF   > XLEN > NF1
-      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~OutFmt) | 
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~OutFmt)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) | 
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
       // 3: NF   > NF1  > XLEN
-      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&IntRes) |
-                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~OutFmt|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&IntRes) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
 
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
       // 1: XLEN > NF   > NF1
-      if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~(OutFmt==`FMT)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
       // 2: NF   > XLEN > NF1
-      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`FMT)) | 
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~(OutFmt==`FMT))) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | 
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
       // 3: NF   > NF1  > XLEN
-      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&(OutFmt==`FMT1)) |
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&((OutFmt==`FMT1)|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~(OutFmt==`FMT)|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT1)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT1)|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
 
-  end else if (`FPSIZES == 4) begin
+  end else if (P.FPSIZES == 4) begin
       // Quad precision will always be greater than XLEN
       // 2: NF   > XLEN > NF1
-      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
-                                                (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`D_NF-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) | 
-                                                (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`Q_FMT)) | 
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) | 
+                                                (|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) | 
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
       // 3: NF   > NF1  > XLEN
       // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
-      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
-                                                (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) |
-                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`D_NF-1]&((OutFmt==`S_FMT)|(OutFmt==`H_FMT)|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
-                                                (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
+                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
+                                                (|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
 
   end
   
@@ -184,40 +183,40 @@ module round(
 
   // only add the Addend sticky if doing an FMA opperation
   //      - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
-  assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivSticky&DivOp;
+  assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[P.NE+1]&FmaOp | DivSticky&DivOp;
   
 
 
 
   // determine round and LSB of the rounded value
   //      - underflow round bit is used to determint the underflow flag
-  if (`FPSIZES == 1) begin
-      assign FpGuard = Mf[`CORRSHIFTSZ-`NF-1];
-      assign FpLsbRes = Mf[`CORRSHIFTSZ-`NF];
-      assign FpRound = Mf[`CORRSHIFTSZ-`NF-2];
+  if (P.FPSIZES == 1) begin
+      assign FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
+      assign FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
+      assign FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
 
-  end else if (`FPSIZES == 2) begin
-      assign FpGuard = OutFmt ? Mf[`CORRSHIFTSZ-`NF-1] : Mf[`CORRSHIFTSZ-`NF1-1];
-      assign FpLsbRes = OutFmt ? Mf[`CORRSHIFTSZ-`NF] : Mf[`CORRSHIFTSZ-`NF1];
-      assign FpRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-2] : Mf[`CORRSHIFTSZ-`NF1-2];
+  end else if (P.FPSIZES == 2) begin
+      assign FpGuard = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-1] : Mf[P.CORRSHIFTSZ-P.NF1-1];
+      assign FpLsbRes = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF] : Mf[P.CORRSHIFTSZ-P.NF1];
+      assign FpRound = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-2] : Mf[P.CORRSHIFTSZ-P.NF1-2];
 
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              `FMT: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`NF-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF];
-                  FpRound = Mf[`CORRSHIFTSZ-`NF-2];
+              P.FMT: begin
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
               end
-              `FMT1: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`NF1-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF1];
-                  FpRound = Mf[`CORRSHIFTSZ-`NF1-2];
+              P.FMT1: begin
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.NF1-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF1];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.NF1-2];
               end
-              `FMT2: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`NF2-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF2];
-                  FpRound = Mf[`CORRSHIFTSZ-`NF2-2];
+              P.FMT2: begin
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.NF2-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF2];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.NF2-2];
               end
               default: begin
                   FpGuard = 1'bx;
@@ -225,35 +224,35 @@ module round(
                   FpRound = 1'bx;
               end
           endcase
-  end else if (`FPSIZES == 4) begin
+  end else if (P.FPSIZES == 4) begin
       always_comb
           case (OutFmt)
               2'h3: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`Q_NF-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`Q_NF];
-                  FpRound = Mf[`CORRSHIFTSZ-`Q_NF-2];
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.Q_NF-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.Q_NF];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.Q_NF-2];
               end
               2'h1: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`D_NF-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`D_NF];
-                  FpRound = Mf[`CORRSHIFTSZ-`D_NF-2];
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.D_NF-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.D_NF];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.D_NF-2];
               end
               2'h0: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`S_NF-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`S_NF];
-                  FpRound = Mf[`CORRSHIFTSZ-`S_NF-2];
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.S_NF-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.S_NF];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.S_NF-2];
               end
               2'h2: begin
-                  FpGuard = Mf[`CORRSHIFTSZ-`H_NF-1];
-                  FpLsbRes = Mf[`CORRSHIFTSZ-`H_NF];
-                  FpRound = Mf[`CORRSHIFTSZ-`H_NF-2];
+                  FpGuard = Mf[P.CORRSHIFTSZ-P.H_NF-1];
+                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.H_NF];
+                  FpRound = Mf[P.CORRSHIFTSZ-P.H_NF-2];
               end
           endcase
   end
 
-  assign Guard = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-1] : FpGuard;
-  assign LsbRes = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN] : FpLsbRes;
-  assign Round = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-2] : FpRound;
+  assign Guard = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard;
+  assign LsbRes = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes;
+  assign Round = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound;
 
 
   always_comb begin
@@ -287,26 +286,26 @@ module round(
 
 
   // place Plus1 into the proper position for the format
-  if (`FPSIZES == 1) begin
-      assign RoundAdd = {{`FLEN{1'b0}}, FpPlus1};
+  if (P.FPSIZES == 1) begin
+      assign RoundAdd = {{P.FLEN{1'b0}}, FpPlus1};
 
-  end else if (`FPSIZES == 2) begin
+  end else if (P.FPSIZES == 2) begin
       // \/FLEN+1
       //  | NE+2 |        NF      |
       //  '-NE+2-^----NF1----^
-      // `FLEN+1-`NE-2-`NF1 = FLEN-1-NE-NF1
-      assign RoundAdd = {(`NE+1+`NF1)'(0), FpPlus1&~OutFmt, (`NF-`NF1-1)'(0), FpPlus1&OutFmt};
+      // P.FLEN+1-P.NE-2-P.NF1 = FLEN-1-NE-NF1
+      assign RoundAdd = {(P.NE+1+P.NF1)'(0), FpPlus1&~OutFmt, (P.NF-P.NF1-1)'(0), FpPlus1&OutFmt};
 
-  end else if (`FPSIZES == 3) begin
-      assign RoundAdd = {(`NE+1+`NF2)'(0), FpPlus1&(OutFmt==`FMT2), (`NF1-`NF2-1)'(0), FpPlus1&(OutFmt==`FMT1), (`NF-`NF1-1)'(0), FpPlus1&(OutFmt==`FMT)};
+  end else if (P.FPSIZES == 3) begin
+      assign RoundAdd = {(P.NE+1+P.NF2)'(0), FpPlus1&(OutFmt==P.FMT2), (P.NF1-P.NF2-1)'(0), FpPlus1&(OutFmt==P.FMT1), (P.NF-P.NF1-1)'(0), FpPlus1&(OutFmt==P.FMT)};
 
-  end else if (`FPSIZES == 4)      
-      assign RoundAdd = {(`Q_NE+1+`H_NF)'(0), FpPlus1&(OutFmt==`H_FMT), (`S_NF-`H_NF-1)'(0), FpPlus1&(OutFmt==`S_FMT), (`D_NF-`S_NF-1)'(0), FpPlus1&(OutFmt==`D_FMT), (`Q_NF-`D_NF-1)'(0), FpPlus1&(OutFmt==`Q_FMT)};
+  end else if (P.FPSIZES == 4)      
+      assign RoundAdd = {(P.Q_NE+1+P.H_NF)'(0), FpPlus1&(OutFmt==P.H_FMT), (P.S_NF-P.H_NF-1)'(0), FpPlus1&(OutFmt==P.S_FMT), (P.D_NF-P.S_NF-1)'(0), FpPlus1&(OutFmt==P.D_FMT), (P.Q_NF-P.D_NF-1)'(0), FpPlus1&(OutFmt==P.Q_FMT)};
 
 
 
   // trim unneeded bits from fraction
-  assign RoundFrac = Mf[`CORRSHIFTSZ-1:`CORRSHIFTSZ-`NF];
+  assign RoundFrac = Mf[P.CORRSHIFTSZ-1:P.CORRSHIFTSZ-P.NF];
   
 
 
@@ -314,7 +313,7 @@ module round(
   always_comb
       case(PostProcSel)
           2'b10: Me = FmaMe; // fma
-          2'b00: Me = {CvtCe[`NE], CvtCe}&{`NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
+          2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
           // 2'b01: Me = DivDone ? Qe : '0; // divide
           2'b01: Me = Qe; // divide
           default: Me = '0; 
@@ -325,7 +324,7 @@ module round(
   // round the result
   //      - if the fraction overflows one should be added to the exponent
   assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd;
-  assign Re = FullRe[`NE-1:0];
+  assign Re = FullRe[P.NE-1:0];
 
 
 endmodule
diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv
index 8809f0a4b..6c1135602 100644
--- a/src/fpu/postproc/roundsign.sv
+++ b/src/fpu/postproc/roundsign.sv
@@ -25,7 +25,6 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
 module roundsign(
   input logic         Xs,     // x sign
@@ -47,4 +46,4 @@ module roundsign(
   // Select sign for rounding calulation
   assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
index 2fb0b5d7e..1a4613d5f 100644
--- a/src/fpu/postproc/shiftcorrection.sv
+++ b/src/fpu/postproc/shiftcorrection.sv
@@ -26,53 +26,51 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module shiftcorrection(
-  input logic  [`NORMSHIFTSZ-1:0] Shifted,                // the shifted sum before LZA correction
+module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
+  input logic  [P.NORMSHIFTSZ-1:0] Shifted,                // the shifted sum before LZA correction
   // divsqrt
   input logic                     DivOp,                  // is it a divsqrt opperation
   input logic                     DivResSubnorm,          // is the divsqrt result subnormal
-  input logic  [`NE+1:0]          DivQe,                  // the divsqrt result's exponent
+  input logic  [P.NE+1:0]          DivQe,                  // the divsqrt result's exponent
   input logic                     DivSubnormShiftPos,     // is the subnorm divider shift amount positive (ie not underflowed)
   //fma
   input logic                     FmaOp,                  // is it an fma opperation
-  input logic  [`NE+1:0]          NormSumExp,             // exponent of the normalized sum not taking into account Subnormal or zero results
+  input logic  [P.NE+1:0]          NormSumExp,             // exponent of the normalized sum not taking into account Subnormal or zero results
   input logic                     FmaPreResultSubnorm,    // is the result subnormal - calculated before LZA corection
   input logic                     FmaSZero,
   // output
-  output logic [`NE+1:0]          FmaMe,                  // exponent of the normalized sum
-  output logic [`CORRSHIFTSZ-1:0] Mf,                     // the shifted sum before LZA correction
-  output logic [`NE+1:0]          Qe                      // corrected exponent for divider
+  output logic [P.NE+1:0]          FmaMe,                  // exponent of the normalized sum
+  output logic [P.CORRSHIFTSZ-1:0] Mf,                     // the shifted sum before LZA correction
+  output logic [P.NE+1:0]          Qe                      // corrected exponent for divider
 );
 
-  logic [3*`NF+3:0]           CorrSumShifted;             // the shifted sum after LZA correction
-  logic [`CORRSHIFTSZ-1:0]    CorrQm0, CorrQm1;           // portions of Shifted to select for CorrQmShifted
-  logic [`CORRSHIFTSZ-1:0]    CorrQmShifted;              // the shifted divsqrt result after one bit shift
+  logic [3*P.NF+3:0]           CorrSumShifted;             // the shifted sum after LZA correction
+  logic [P.CORRSHIFTSZ-1:0]    CorrQm0, CorrQm1;           // portions of Shifted to select for CorrQmShifted
+  logic [P.CORRSHIFTSZ-1:0]    CorrQmShifted;              // the shifted divsqrt result after one bit shift
   logic                       ResSubnorm;                 // is the result Subnormal
   logic                       LZAPlus1;                   // add one or two to the sum's exponent due to LZA correction
   logic                       LeftShiftQm;                // should the divsqrt result be shifted one to the left
 
   // LZA correction
-  assign LZAPlus1 = Shifted[`NORMSHIFTSZ-1];
+  assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1];
 
   // correct the shifting error caused by the LZA
   //  - the only possible mantissa for a plus two is all zeroes 
   //      - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
-  mux2 #(`NORMSHIFTSZ-2) lzacorrmux(Shifted[`NORMSHIFTSZ-3:0], Shifted[`NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
+  mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
 
   // correct the shifting of the divsqrt caused by producing a result in (2, .5] range
   //    condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
   assign LeftShiftQm = (LZAPlus1|(DivQe==1&~LZAPlus1));
-  assign CorrQm0 = Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
-  assign CorrQm1 = Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1];
-  mux2 #(`CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
+  assign CorrQm0 = Shifted[P.NORMSHIFTSZ-3:P.NORMSHIFTSZ-P.CORRSHIFTSZ-2];
+  assign CorrQm1 = Shifted[P.NORMSHIFTSZ-2:P.NORMSHIFTSZ-P.CORRSHIFTSZ-1];
+  mux2 #(P.CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
   
   // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
   always_comb
-    if(FmaOp)                       Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+4){1'b0}}};
+    if(FmaOp)                       Mf = {CorrSumShifted, {P.CORRSHIFTSZ-(3*P.NF+4){1'b0}}};
     else if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
-    else                            Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
+    else                            Mf = Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.CORRSHIFTSZ];
     
   // Determine sum's exponent
   //  main exponent issues: 
@@ -82,12 +80,12 @@ module shiftcorrection(
   //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 2
   //                          if plus1                    If plus2                               kill if the result Zero or actually subnormal
   //                          |                           |                                      |
-  assign FmaMe = (NormSumExp+{{`NE+1{1'b0}}, LZAPlus1} +{{`NE+1{1'b0}}, FmaPreResultSubnorm}) & {`NE+2{~(FmaSZero|ResSubnorm)}};
+  assign FmaMe = (NormSumExp+{{P.NE+1{1'b0}}, LZAPlus1} +{{P.NE+1{1'b0}}, FmaPreResultSubnorm}) & {P.NE+2{~(FmaSZero|ResSubnorm)}};
   
   // recalculate if the result is subnormal after LZA correction
-  assign ResSubnorm = FmaPreResultSubnorm&~Shifted[`NORMSHIFTSZ-2]&~Shifted[`NORMSHIFTSZ-1];
+  assign ResSubnorm = FmaPreResultSubnorm&~Shifted[P.NORMSHIFTSZ-2]&~Shifted[P.NORMSHIFTSZ-1];
 
   // the quotent is in the range [.5,2) if there is no early termination
   // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
-  assign Qe = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivQe - {(`NE+1)'(0), ~LZAPlus1};
-endmodule
\ No newline at end of file
+  assign Qe = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivQe - {(P.NE+1)'(0), ~LZAPlus1};
+endmodule
diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
index 6b2985c07..3825a0f78 100644
--- a/src/fpu/postproc/specialcase.sv
+++ b/src/fpu/postproc/specialcase.sv
@@ -26,14 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module specialcase(
+module specialcase import cvw::*;  #(parameter cvw_t P) (
   input  logic                Xs,         // X sign
-  input  logic [`NF:0]        Xm, Ym, Zm, // input significand's
+  input  logic [P.NF:0]        Xm, Ym, Zm, // input significand's
   input  logic                XNaN, YNaN, ZNaN, // are the inputs NaN
   input  logic [2:0]          Frm,        // rounding mode
-  input  logic [`FMTBITS-1:0] OutFmt,     // output format
+  input  logic [P.FMTBITS-1:0] OutFmt,     // output format
   input  logic                InfIn,      // are any inputs infinity
   input  logic                NaNIn,      // are any input NaNs
   input  logic                XInf, YInf, // are X or Y inifnity
@@ -41,9 +39,9 @@ module specialcase(
   input  logic                Plus1,      // do you add one for rounding
   input  logic                Rs,         // the result's sign
   input  logic                Invalid, Overflow,  // flags to choose the result
-  input  logic [`NE-1:0]      Re,         // Result exponent
-  input  logic [`NE+1:0]      FullRe,     // Result full exponent
-  input  logic [`NF-1:0]      Rf,         // Result fraction
+  input  logic [P.NE-1:0]      Re,         // Result exponent
+  input  logic [P.NE+1:0]      FullRe,     // Result full exponent
+  input  logic [P.NF-1:0]      Rf,         // Result fraction
   // fma
   input  logic                FmaOp,      // is it a fma opperation
   // divsqrt
@@ -55,23 +53,23 @@ module specialcase(
   input  logic                IntToFp,    // is cvt int -> fp opperation
   input  logic                Int64,      // is the integer 64 bits
   input  logic                Signed,     // is the integer signed
-  input  logic [`NE:0]        CvtCe,      // the calculated expoent for cvt
+  input  logic [P.NE:0]        CvtCe,      // the calculated expoent for cvt
   input  logic                IntInvalid, // integer invalid flag to choose the result
   input  logic                CvtResUf,   // does the convert result underflow
-  input  logic [`XLEN+1:0]    CvtNegRes,  // the possibly negated of the integer result
+  input  logic [P.XLEN+1:0]    CvtNegRes,  // the possibly negated of the integer result
   // outputs
-  output logic [`FLEN-1:0]    PostProcRes,// final result
-  output logic [`XLEN-1:0]    FCvtIntRes  // final integer result
+  output logic [P.FLEN-1:0]    PostProcRes,// final result
+  output logic [P.XLEN-1:0]    FCvtIntRes  // final integer result
 );
 
-  logic [`FLEN-1:0]   XNaNRes;    // X is NaN result
-  logic [`FLEN-1:0]   YNaNRes;    // Y is NaN result
-  logic [`FLEN-1:0]   ZNaNRes;    // Z is NaN result
-  logic [`FLEN-1:0]   InvalidRes; // Invalid result result
-  logic [`FLEN-1:0]   UfRes;      // underflowed result result
-  logic [`FLEN-1:0]   OfRes;      // overflowed result result
-  logic [`FLEN-1:0]   NormRes;    // normal result
-  logic [`XLEN-1:0]   OfIntRes;   // the overflow result for integer output
+  logic [P.FLEN-1:0]   XNaNRes;    // X is NaN result
+  logic [P.FLEN-1:0]   YNaNRes;    // Y is NaN result
+  logic [P.FLEN-1:0]   ZNaNRes;    // Z is NaN result
+  logic [P.FLEN-1:0]   InvalidRes; // Invalid result result
+  logic [P.FLEN-1:0]   UfRes;      // underflowed result result
+  logic [P.FLEN-1:0]   OfRes;      // overflowed result result
+  logic [P.FLEN-1:0]   NormRes;    // normal result
+  logic [P.XLEN-1:0]   OfIntRes;   // the overflow result for integer output
   logic               OfResMax;   // does the of result output maximum norm fp number
   logic               KillRes;    // kill the result for underflow
   logic               SelOfRes;   // should the overflow result be selected
@@ -82,158 +80,158 @@ module specialcase(
   assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Rs) | (Frm[1:0]==2'b11&Rs));
 
   // select correct outputs for special cases
-  if (`FPSIZES == 1) begin
+  if (P.FPSIZES == 1) begin
       //NaN res selection depending on standard
-      if(`IEEE754) begin
-          assign XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-          assign YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
-          assign ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
-          assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+      if(P.IEEE754) begin
+          assign XNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+          assign YNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
+          assign ZNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
+          assign InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
       end else begin
-          assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+          assign InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
       end
 
-      assign OfRes =  OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
-      assign UfRes = {Rs, {`FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)};
+      assign OfRes =  OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
+      assign UfRes = {Rs, {P.FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)};
       assign NormRes = {Rs, Re, Rf};
 
-  end else if (`FPSIZES == 2) begin
-      if(`IEEE754) begin
-          assign XNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
-          assign YNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
-          assign ZNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
-          assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+  end else if (P.FPSIZES == 2) begin
+      if(P.IEEE754) begin
+          assign XNaNRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
+          assign YNaNRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF1]};
+          assign ZNaNRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF1]};
+          assign InvalidRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
       end else begin 
-          assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+          assign InvalidRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
       end
 
       always_comb
           if(OutFmt)
-              if(OfResMax)    OfRes = {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}};
-              else            OfRes = {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
+              if(OfResMax)    OfRes = {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}};
+              else            OfRes = {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
           else
-              if(OfResMax)    OfRes = {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}};
-              else            OfRes = {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1{1'b1}}, (`NF1)'(0)};
-      assign UfRes = OutFmt ? {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)} : {{`FLEN-`LEN1{1'b1}}, Rs, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-      assign NormRes = OutFmt ? {Rs, Re, Rf} : {{`FLEN-`LEN1{1'b1}}, Rs, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]};
+              if(OfResMax)    OfRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1-1{1'b1}}, 1'b0, {P.NF1{1'b1}}};
+              else            OfRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1{1'b1}}, (P.NF1)'(0)};
+      assign UfRes = OutFmt ? {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)} : {{P.FLEN-P.LEN1{1'b1}}, Rs, (P.LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+      assign NormRes = OutFmt ? {Rs, Re, Rf} : {{P.FLEN-P.LEN1{1'b1}}, Rs, Re[P.NE1-1:0], Rf[P.NF-1:P.NF-P.NF1]};
 
-  end else if (`FPSIZES == 3) begin
+  end else if (P.FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              `FMT: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-                      YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
-                      ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
-                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+              P.FMT: begin  
+                  if(P.IEEE754) begin
+                      XNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+                      YNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
+                      ZNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
+                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
                   end else begin 
-                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
                   end
                   
-                  OfRes = OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
-                  UfRes = {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  OfRes = OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
+                  UfRes = {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
                   NormRes = {Rs, Re, Rf};
               end
-              `FMT1: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
-                      YNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
-                      ZNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
-                      InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+              P.FMT1: begin  
+                  if(P.IEEE754) begin
+                      XNaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
+                      YNaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF1]};
+                      ZNaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF1]};
+                      InvalidRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
                   end else begin 
-                      InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+                      InvalidRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
                   end
-                  OfRes = OfResMax ? {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1{1'b1}}, (`NF1)'(0)};
-                  UfRes = {{`FLEN-`LEN1{1'b1}}, Rs, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{`FLEN-`LEN1{1'b1}}, Rs, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]};
+                  OfRes = OfResMax ? {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1-1{1'b1}}, 1'b0, {P.NF1{1'b1}}} : {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1{1'b1}}, (P.NF1)'(0)};
+                  UfRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, (P.LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, Re[P.NE1-1:0], Rf[P.NF-1:P.NF-P.NF1]};
               end
-              `FMT2: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
-                      YNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF2]};
-                      ZNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF2]};
-                      InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
+              P.FMT2: begin  
+                  if(P.IEEE754) begin
+                      XNaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
+                      YNaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF2]};
+                      ZNaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF2]};
+                      InvalidRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
                   end else begin 
-                      InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
+                      InvalidRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
                   end
                   
-                  OfRes = OfResMax ? {{`FLEN-`LEN2{1'b1}}, Rs, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, Rs, {`NE2{1'b1}}, (`NF2)'(0)};
-                  UfRes = {{`FLEN-`LEN2{1'b1}}, Rs, (`LEN2-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{`FLEN-`LEN2{1'b1}}, Rs, Re[`NE2-1:0], Rf[`NF-1:`NF-`NF2]};
+                  OfRes = OfResMax ? {{P.FLEN-P.LEN2{1'b1}}, Rs, {P.NE2-1{1'b1}}, 1'b0, {P.NF2{1'b1}}} : {{P.FLEN-P.LEN2{1'b1}}, Rs, {P.NE2{1'b1}}, (P.NF2)'(0)};
+                  UfRes = {{P.FLEN-P.LEN2{1'b1}}, Rs, (P.LEN2-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{P.FLEN-P.LEN2{1'b1}}, Rs, Re[P.NE2-1:0], Rf[P.NF-1:P.NF-P.NF2]};
               end
               default: begin
-                  if(`IEEE754) begin
-                      XNaNRes = (`FLEN)'(0);
-                      YNaNRes = (`FLEN)'(0);
-                      ZNaNRes = (`FLEN)'(0);
-                      InvalidRes = (`FLEN)'(0);
+                  if(P.IEEE754) begin
+                      XNaNRes = (P.FLEN)'(0);
+                      YNaNRes = (P.FLEN)'(0);
+                      ZNaNRes = (P.FLEN)'(0);
+                      InvalidRes = (P.FLEN)'(0);
                   end else begin 
-                      InvalidRes = (`FLEN)'(0);
+                      InvalidRes = (P.FLEN)'(0);
                   end
-                  OfRes = (`FLEN)'(0);
-                  UfRes = (`FLEN)'(0);
-                  NormRes = (`FLEN)'(0);
+                  OfRes = (P.FLEN)'(0);
+                  UfRes = (P.FLEN)'(0);
+                  NormRes = (P.FLEN)'(0);
               end
           endcase
 
-  end else if (`FPSIZES == 4) begin 
+  end else if (P.FPSIZES == 4) begin 
       always_comb
           case (OutFmt)
               2'h3: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
-                      YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
-                      ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
-                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                  if(P.IEEE754) begin
+                      XNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
+                      YNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
+                      ZNaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
+                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
                   end else begin 
-                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
                   end
                   
-                  OfRes = OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
-                  UfRes = {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  OfRes = OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
+                  UfRes = {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
                   NormRes = {Rs, Re, Rf};
               end
               2'h1: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
-                      YNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`D_NF]};
-                      ZNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`D_NF]};
-                      InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+                  if(P.IEEE754) begin
+                      XNaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
+                      YNaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.D_NF]};
+                      ZNaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.D_NF]};
+                      InvalidRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
                   end else begin 
-                      InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+                      InvalidRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
                   end
-                  OfRes = OfResMax ? {{`FLEN-`D_LEN{1'b1}}, Rs, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, Rs, {`D_NE{1'b1}}, (`D_NF)'(0)};
-                  UfRes = {{`FLEN-`D_LEN{1'b1}}, Rs, (`D_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{`FLEN-`D_LEN{1'b1}}, Rs, Re[`D_NE-1:0], Rf[`NF-1:`NF-`D_NF]};
+                  OfRes = OfResMax ? {{P.FLEN-P.D_LEN{1'b1}}, Rs, {P.D_NE-1{1'b1}}, 1'b0, {P.D_NF{1'b1}}} : {{P.FLEN-P.D_LEN{1'b1}}, Rs, {P.D_NE{1'b1}}, (P.D_NF)'(0)};
+                  UfRes = {{P.FLEN-P.D_LEN{1'b1}}, Rs, (P.D_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{P.FLEN-P.D_LEN{1'b1}}, Rs, Re[P.D_NE-1:0], Rf[P.NF-1:P.NF-P.D_NF]};
               end
               2'h0: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
-                      YNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`S_NF]};
-                      ZNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`S_NF]};
-                      InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+                  if(P.IEEE754) begin
+                      XNaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
+                      YNaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.S_NF]};
+                      ZNaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.S_NF]};
+                      InvalidRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
                   end else begin 
-                      InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+                      InvalidRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
                   end
                   
-                  OfRes = OfResMax ? {{`FLEN-`S_LEN{1'b1}}, Rs, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, Rs, {`S_NE{1'b1}}, (`S_NF)'(0)};
-                  UfRes = {{`FLEN-`S_LEN{1'b1}}, Rs, (`S_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{`FLEN-`S_LEN{1'b1}}, Rs, Re[`S_NE-1:0], Rf[`NF-1:`NF-`S_NF]};
+                  OfRes = OfResMax ? {{P.FLEN-P.S_LEN{1'b1}}, Rs, {P.S_NE-1{1'b1}}, 1'b0, {P.S_NF{1'b1}}} : {{P.FLEN-P.S_LEN{1'b1}}, Rs, {P.S_NE{1'b1}}, (P.S_NF)'(0)};
+                  UfRes = {{P.FLEN-P.S_LEN{1'b1}}, Rs, (P.S_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{P.FLEN-P.S_LEN{1'b1}}, Rs, Re[P.S_NE-1:0], Rf[P.NF-1:P.NF-P.S_NF]};
               end
               2'h2: begin  
-                  if(`IEEE754) begin
-                      XNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
-                      YNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`H_NF]};
-                      ZNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`H_NF]};
-                      InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+                  if(P.IEEE754) begin
+                      XNaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
+                      YNaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.H_NF]};
+                      ZNaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.H_NF]};
+                      InvalidRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
                   end else begin 
-                      InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+                      InvalidRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
                   end
                   
-                  OfRes = OfResMax ? {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE{1'b1}}, (`H_NF)'(0)};      
+                  OfRes = OfResMax ? {{P.FLEN-P.H_LEN{1'b1}}, Rs, {P.H_NE-1{1'b1}}, 1'b0, {P.H_NF{1'b1}}} : {{P.FLEN-P.H_LEN{1'b1}}, Rs, {P.H_NE{1'b1}}, (P.H_NF)'(0)};      
                 // zero is exact if dividing by infinity so don't add 1
-                  UfRes = {{`FLEN-`H_LEN{1'b1}}, Rs, (`H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{`FLEN-`H_LEN{1'b1}}, Rs, Re[`H_NE-1:0], Rf[`NF-1:`NF-`H_NF]};
+                  UfRes = {{P.FLEN-P.H_LEN{1'b1}}, Rs, (P.H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{P.FLEN-P.H_LEN{1'b1}}, Rs, Re[P.H_NE-1:0], Rf[P.NF-1:P.NF-P.H_NF]};
               end
           endcase
   end
@@ -242,13 +240,13 @@ module specialcase(
   //      - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0
   //      - dont set to zero if fp input is zero but not using the fp input
   //      - dont set to zero if int input is zero but not using the int input
-  assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[`NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResSubnorm & (Re!=1);
+  assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[P.NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResSubnorm & (Re!=1);
   
   // calculate if the overflow result should be selected
   assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp));
   
   // output infinity with result sign if divide by zero
-  if(`IEEE754)
+  if(P.IEEE754)
     always_comb
       if(XNaN&~(IntToFp&CvtOp))   PostProcRes = XNaNRes;
       else if(YNaN&~CvtOp)        PostProcRes = YNaNRes;
@@ -283,14 +281,14 @@ module specialcase(
   always_comb
     if(Signed)
       if(Xs&~NaNIn) // signed negitive
-        if(Int64)   OfIntRes = {1'b1, {`XLEN-1{1'b0}}};
-        else        OfIntRes = {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
+        if(Int64)   OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
+        else        OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
       else          // signed positive
-        if(Int64)   OfIntRes = {1'b0, {`XLEN-1{1'b1}}};
-        else        OfIntRes = {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
+        if(Int64)   OfIntRes = {1'b0, {P.XLEN-1{1'b1}}};
+        else        OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
     else
-      if(Xs&~NaNIn) OfIntRes = {`XLEN{1'b0}}; // unsigned negitive
-      else          OfIntRes = {`XLEN{1'b1}}; // unsigned positive
+      if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive
+      else          OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
 
 
   // select the integer output
@@ -301,9 +299,9 @@ module specialcase(
   //      - otherwise output the normal res (trmined and sign extended if nessisary)
   always_comb
     if(IntInvalid)          FCvtIntRes = OfIntRes;
-    else if(CvtCe[`NE]) 
-      if(Xs&Signed&Plus1)   FCvtIntRes = {{`XLEN{1'b1}}};
-      else                  FCvtIntRes = {{`XLEN-1{1'b0}}, Plus1};
-    else if(Int64)          FCvtIntRes = CvtNegRes[`XLEN-1:0];
-    else                    FCvtIntRes = {{`XLEN-32{CvtNegRes[31]}}, CvtNegRes[31:0]};
-endmodule
\ No newline at end of file
+    else if(CvtCe[P.NE]) 
+      if(Xs&Signed&Plus1)   FCvtIntRes = {{P.XLEN{1'b1}}};
+      else                  FCvtIntRes = {{P.XLEN-1{1'b0}}, Plus1};
+    else if(Int64)          FCvtIntRes = CvtNegRes[P.XLEN-1:0];
+    else                    FCvtIntRes = {{P.XLEN-32{CvtNegRes[31]}}, CvtNegRes[31:0]};
+endmodule
diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv
index d52b454ea..145d6a701 100644
--- a/src/fpu/unpack.sv
+++ b/src/fpu/unpack.sv
@@ -25,41 +25,41 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module unpack ( 
-  input  logic [`FLEN-1:0]        X, Y, Z,              // inputs from register file
-  input  logic [`FMTBITS-1:0]     Fmt,                  // format signal 00 - single 01 - double 11 - quad 10 - half
+module unpack import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FLEN-1:0]       X, Y, Z,              // inputs from register file
+  input  logic [P.FMTBITS-1:0]    Fmt,                  // format signal 00 - single 01 - double 11 - quad 10 - half
   input  logic                    XEn, YEn, ZEn,        // input enables
+  input  logic                    FPUActive,            // Kill inputs when FPU is not active
   output logic                    Xs, Ys, Zs,           // sign bits of XYZ
-  output logic [`NE-1:0]          Xe, Ye, Ze,           // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]            Xm, Ym, Zm,           // mantissas of XYZ (converted to largest supported precision)
+  output logic [P.NE-1:0]         Xe, Ye, Ze,           // exponents of XYZ (converted to largest supported precision)
+  output logic [P.NF:0]           Xm, Ym, Zm,           // mantissas of XYZ (converted to largest supported precision)
   output logic                    XNaN, YNaN, ZNaN,     // is XYZ a NaN
   output logic                    XSNaN, YSNaN, ZSNaN,  // is XYZ a signaling NaN
   output logic                    XSubnorm,             // is X subnormal
   output logic                    XZero, YZero, ZZero,  // is XYZ zero
   output logic                    XInf, YInf, ZInf,     // is XYZ infinity
   output logic                    XExpMax,              // does X have the maximum exponent (NaN or Inf)
-  output logic [`FLEN-1:0]        XPostBox              // X after being properly NaN-boxed
+  output logic [P.FLEN-1:0]       XPostBox              // X after being properly NaN-boxed
 );
 
   logic XExpNonZero, YExpNonZero, ZExpNonZero;          // is the exponent of XYZ non-zero
   logic XFracZero, YFracZero, ZFracZero;                // is the fraction zero
   logic YExpMax, ZExpMax;                               // is the exponent all 1s
   
-  unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
+  unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive,
                           .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
                           .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), 
                           .Subnorm(XSubnorm), .PostBox(XPostBox));
 
-  unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
+  unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive,
                           .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
                           .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), 
                           .Subnorm(), .PostBox());
 
-  unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
+  unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive,
                           .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
                           .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), 
                           .Subnorm(), .PostBox());
  
- endmodule
\ No newline at end of file
+ endmodule
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index 82a2eb8f1..c551e8173 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -25,46 +25,50 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
-module unpackinput ( 
-  input  logic [`FLEN-1:0]        In,         // inputs from register file
-  input  logic                    En,         // enable the input
-  input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-  output logic                    Sgn,        // sign bits of the number 
-  output logic [`NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
-  output logic [`NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
-  output logic                    NaN,        // is the number a NaN
-  output logic                    SNaN,       // is the number a signaling NaN
-  output logic                    Zero,       // is the number zero
-  output logic                    Inf,        // is the number infinity
-  output logic                    ExpNonZero, // is the exponent not zero
-  output logic                    FracZero,   // is the fraction zero
-  output logic                    ExpMax,     // does In have the maximum exponent (NaN or Inf)
-  output logic                    Subnorm,    // is the number subnormal
-  output logic [`FLEN-1:0]        PostBox     // Number reboxed correctly as a NaN
+module unpackinput import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FLEN-1:0]        A,          // inputs from register file
+  input  logic                     En,         // enable the input
+  input  logic [P.FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
+  input  logic                     FPUActive,  // Kill inputs when FPU is not active
+  output logic                     Sgn,        // sign bits of the number 
+  output logic [P.NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
+  output logic [P.NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
+  output logic                     NaN,        // is the number a NaN
+  output logic                     SNaN,       // is the number a signaling NaN
+  output logic                     Zero,       // is the number zero
+  output logic                     Inf,        // is the number infinity
+  output logic                     ExpNonZero, // is the exponent not zero
+  output logic                     FracZero,   // is the fraction zero
+  output logic                     ExpMax,     // does In have the maximum exponent (NaN or Inf)
+  output logic                     Subnorm,    // is the number subnormal
+  output logic [P.FLEN-1:0]        PostBox     // Number reboxed correctly as a NaN
 );
 
-  logic [`NF-1:0] Frac;       // Fraction of XYZ
-  logic           BadNaNBox;  // incorrectly NaN Boxed
+  logic [P.NF-1:0] Frac;        // Fraction of XYZ
+  logic            BadNaNBox;   // incorrectly NaN Boxed
+  logic [P.FLEN-1:0] In;
 
-  if (`FPSIZES == 1) begin        // if there is only one floating point format supported
+  // Gate input when FPU is not active to save power and simulation
+  assign In = A & {P.FLEN{FPUActive}};
+
+  if (P.FPSIZES == 1) begin        // if there is only one floating point format supported
       assign BadNaNBox = 0;
-      assign Sgn = In[`FLEN-1];  // sign bit
-      assign Frac = In[`NF-1:0];  // fraction (no assumed 1)
-      assign ExpNonZero = |In[`FLEN-2:`NF];  // is the exponent non-zero
-      assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};  // exponent.  subnormal numbers have effective biased exponent of 1
-      assign ExpMax = &In[`FLEN-2:`NF];  // is the exponent all 1's
+      assign Sgn = In[P.FLEN-1];  // sign bit
+      assign Frac = In[P.NF-1:0];  // fraction (no assumed 1)
+      assign ExpNonZero = |In[P.FLEN-2:P.NF];  // is the exponent non-zero
+      assign Exp = {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero};  // exponent.  subnormal numbers have effective biased exponent of 1
+      assign ExpMax = &In[P.FLEN-2:P.NF];  // is the exponent all 1's
       assign PostBox = In;
   
-  end else if (`FPSIZES == 2) begin   // if there are 2 floating point formats supported
+  end else if (P.FPSIZES == 2) begin   // if there are 2 floating point formats supported
       // largest format | smaller format
       //----------------------------------
-      //      `FLEN     |     `LEN1       length of floating point number
-      //      `NE       |     `NE1        length of exponent
-      //      `NF       |     `NF1        length of fraction
-      //      `BIAS     |     `BIAS1      exponent's bias value
-      //      `FMT      |     `FMT1       precision's format value - Q=11 D=01 Sticky=00 H=10
+      //      P.FLEN     |     P.LEN1       length of floating point number
+      //      P.NE       |     P.NE1        length of exponent
+      //      P.NF       |     P.NF1        length of fraction
+      //      P.BIAS     |     P.BIAS1      exponent's bias value
+      //      P.FMT      |     P.FMT1       precision's format value - Q=11 D=01 Sticky=00 H=10
 
       // Possible combinantions specified by spec:
       //      double and single
@@ -76,22 +80,22 @@ module unpackinput (
       //      quad   and half
       //      double and half
 
-      assign BadNaNBox = ~(Fmt|(&In[`FLEN-1:`LEN1])); // Check NaN boxing
+      assign BadNaNBox = ~(Fmt|(&In[P.FLEN-1:P.LEN1])); // Check NaN boxing
       always_comb
         if (BadNaNBox) begin
-//          PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]};
-          PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, {(`LEN1-`NE1-2){1'b0}}};
+//          PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
+          PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
         end else 
           PostBox = In;
 
       // choose sign bit depending on format - 1=larger precsion 0=smaller precision
-      assign Sgn = Fmt ? In[`FLEN-1] : (BadNaNBox ? 0 : In[`LEN1-1]); // improperly boxed NaNs are treated as positive
+      assign Sgn = Fmt ? In[P.FLEN-1] : (BadNaNBox ? 0 : In[P.LEN1-1]); // improperly boxed NaNs are treated as positive
 
       // extract the fraction, add trailing zeroes to the mantissa if nessisary
-      assign Frac = Fmt ? In[`NF-1:0] : {In[`NF1-1:0], (`NF-`NF1)'(0)};
+      assign Frac = Fmt ? In[P.NF-1:0] : {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
 
       // is the exponent non-zero
-      assign ExpNonZero = Fmt ? |In[`FLEN-2:`NF] : |In[`LEN1-2:`NF1]; 
+      assign ExpNonZero = Fmt ? |In[P.FLEN-2:P.NF] : |In[P.LEN1-2:P.NF1]; 
 
       // example double to single conversion:
       // 1023 = 0011 1111 1111
@@ -103,21 +107,20 @@ module unpackinput (
 
       // extract the exponent, converting the smaller exponent into the larger precision if nessisary
       //      - if the original precision had a Subnormal number convert the exponent value 1
-      assign Exp = Fmt ? {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero} : {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; 
+      assign Exp = Fmt ? {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero} : {In[P.LEN1-2], {P.NE-P.NE1{~In[P.LEN1-2]}}, In[P.LEN1-3:P.NF1+1], In[P.NF1]|~ExpNonZero}; 
 
       // is the exponent all 1's
-      assign ExpMax = Fmt ? &In[`FLEN-2:`NF] : &In[`LEN1-2:`NF1];
+      assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
   
-
-  end else if (`FPSIZES == 3) begin       // three floating point precsions supported
+  end else if (P.FPSIZES == 3) begin       // three floating point precsions supported
 
       // largest format | larger format  | smallest format
       //---------------------------------------------------
-      //      `FLEN     |     `LEN1      |    `LEN2       length of floating point number
-      //      `NE       |     `NE1       |    `NE2        length of exponent
-      //      `NF       |     `NF1       |    `NF2        length of fraction
-      //      `BIAS     |     `BIAS1     |    `BIAS2      exponent's bias value
-      //      `FMT      |     `FMT1      |    `FMT2       precision's format value - Q=11 D=01 Sticky=00 H=10
+      //      P.FLEN     |     P.LEN1      |    P.LEN2       length of floating point number
+      //      P.NE       |     P.NE1       |    P.NE2        length of exponent
+      //      P.NF       |     P.NF1       |    P.NF2        length of fraction
+      //      P.BIAS     |     P.BIAS1     |    P.BIAS2      exponent's bias value
+      //      P.FMT      |     P.FMT1      |    P.FMT2       precision's format value - Q=11 D=01 Sticky=00 H=10
 
       // Possible combinantions specified by spec:
       //      quad   and double and single
@@ -130,20 +133,20 @@ module unpackinput (
       // Check NaN boxing
       always_comb
           case (Fmt)
-              `FMT:  BadNaNBox = 0;
-              `FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1];
-              `FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2];
+              P.FMT:  BadNaNBox = 0;
+              P.FMT1: BadNaNBox = ~&In[P.FLEN-1:P.LEN1];
+              P.FMT2: BadNaNBox = ~&In[P.FLEN-1:P.LEN2];
               default: BadNaNBox = 1'bx;
           endcase
 
       always_comb
         if (BadNaNBox) begin
           case (Fmt)
-            `FMT: PostBox = In;
-//            `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]};
-//            `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, In[`LEN2-`NE2-3:0]};
-            `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, {(`LEN1-`NE1-2){1'b0}}};
-            `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, {(`LEN2-`NE2-2){1'b0}}};
+            P.FMT: PostBox = In;
+//            P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
+//            P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, In[P.LEN2-P.NE2-3:0]};
+            P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
+            P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
             default: PostBox = 'x;
           endcase
         end else 
@@ -154,27 +157,27 @@ module unpackinput (
         if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive
         else
           case (Fmt)
-              `FMT:  Sgn = In[`FLEN-1];
-              `FMT1: Sgn = In[`LEN1-1];
-              `FMT2: Sgn = In[`LEN2-1];
+              P.FMT:  Sgn = In[P.FLEN-1];
+              P.FMT1: Sgn = In[P.LEN1-1];
+              P.FMT2: Sgn = In[P.LEN2-1];
               default: Sgn = 1'bx;
           endcase
 
        // extract the fraction
       always_comb
           case (Fmt)
-              `FMT: Frac = In[`NF-1:0];
-              `FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)};
-              `FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)};
-              default: Frac = {`NF{1'bx}};
+              P.FMT: Frac = In[P.NF-1:0];
+              P.FMT1: Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
+              P.FMT2: Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)};
+              default: Frac = {P.NF{1'bx}};
           endcase
 
       // is the exponent non-zero
       always_comb
           case (Fmt)
-              `FMT:  ExpNonZero = |In[`FLEN-2:`NF];     // if input is largest precision (`FLEN - ie quad or double)
-              `FMT1: ExpNonZero = |In[`LEN1-2:`NF1];  // if input is larger precsion (`LEN1 - double or single)
-              `FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half)
+              P.FMT:  ExpNonZero = |In[P.FLEN-2:P.NF];     // if input is largest precision (P.FLEN - ie quad or double)
+              P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1];  // if input is larger precsion (P.LEN1 - double or single)
+              P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precsion (P.LEN2 - single or half)
               default: ExpNonZero = 1'bx; 
           endcase
           
@@ -189,50 +192,50 @@ module unpackinput (
       // convert the larger precision's exponent to use the largest precision's bias
       always_comb 
           case (Fmt)
-              `FMT:  Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};
-              `FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; 
-              `FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero}; 
-              default: Exp = {`NE{1'bx}};
+              P.FMT:  Exp = {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero};
+              P.FMT1: Exp = {In[P.LEN1-2], {P.NE-P.NE1{~In[P.LEN1-2]}}, In[P.LEN1-3:P.NF1+1], In[P.NF1]|~ExpNonZero}; 
+              P.FMT2: Exp = {In[P.LEN2-2], {P.NE-P.NE2{~In[P.LEN2-2]}}, In[P.LEN2-3:P.NF2+1], In[P.NF2]|~ExpNonZero}; 
+              default: Exp = {P.NE{1'bx}};
           endcase
 
       // is the exponent all 1's
       always_comb
           case (Fmt)
-              `FMT:  ExpMax = &In[`FLEN-2:`NF];
-              `FMT1: ExpMax = &In[`LEN1-2:`NF1];
-              `FMT2: ExpMax = &In[`LEN2-2:`NF2];
+              P.FMT:  ExpMax = &In[P.FLEN-2:P.NF];
+              P.FMT1: ExpMax = &In[P.LEN1-2:P.NF1];
+              P.FMT2: ExpMax = &In[P.LEN2-2:P.NF2];
               default: ExpMax = 1'bx;
           endcase
 
-  end else if (`FPSIZES == 4) begin      // if all precsisons are supported - quad, double, single, and half
+  end else if (P.FPSIZES == 4) begin      // if all precsisons are supported - quad, double, single, and half
   
       //    quad   |  double  |  single  |  half    
       //-------------------------------------------------------------------
-      //   `Q_LEN  |  `D_LEN  |  `S_LEN  |  `H_LEN     length of floating point number
-      //   `Q_NE   |  `D_NE   |  `S_NE   |  `H_NE      length of exponent
-      //   `Q_NF   |  `D_NF   |  `S_NF   |  `H_NF      length of fraction
-      //   `Q_BIAS |  `D_BIAS |  `S_BIAS |  `H_BIAS    exponent's bias value
-      //   `Q_FMT  |  `D_FMT  |  `S_FMT  |  `H_FMT     precision's format value - Q=11 D=01 Sticky=00 H=10
+      //   P.Q_LEN  |  P.D_LEN  |  P.S_LEN  |  P.H_LEN     length of floating point number
+      //   P.Q_NE   |  P.D_NE   |  P.S_NE   |  P.H_NE      length of exponent
+      //   P.Q_NF   |  P.D_NF   |  P.S_NF   |  P.H_NF      length of fraction
+      //   P.Q_BIAS |  P.D_BIAS |  P.S_BIAS |  P.H_BIAS    exponent's bias value
+      //   P.Q_FMT  |  P.D_FMT  |  P.S_FMT  |  P.H_FMT     precision's format value - Q=11 D=01 Sticky=00 H=10
 
       // Check NaN boxing
       always_comb
           case (Fmt)
               2'b11: BadNaNBox = 0;
-              2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN];
-              2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN];
-              2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN];
+              2'b01: BadNaNBox = ~&In[P.Q_LEN-1:P.D_LEN];
+              2'b00: BadNaNBox = ~&In[P.Q_LEN-1:P.S_LEN];
+              2'b10: BadNaNBox = ~&In[P.Q_LEN-1:P.H_LEN];
           endcase
 
       always_comb
         if (BadNaNBox) begin
           case (Fmt)
             2'b11: PostBox = In;
-//            2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, In[`D_LEN-`D_NE-3:0]};
-//            2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, In[`S_LEN-`S_NE-3:0]};
-//            2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, In[`H_LEN-`H_NE-3:0]};
-            2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, {(`D_LEN-`D_NE-2){1'b0}}};
-            2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, {(`S_LEN-`S_NE-2){1'b0}}};
-            2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, {(`H_LEN-`H_NE-2){1'b0}}};
+//            2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, In[P.D_LEN-P.D_NE-3:0]};
+//            2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, In[P.S_LEN-P.S_NE-3:0]};
+//            2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, In[P.H_LEN-P.H_NE-3:0]};
+            2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, {(P.D_LEN-P.D_NE-2){1'b0}}};
+            2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, {(P.S_LEN-P.S_NE-2){1'b0}}};
+            2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, {(P.H_LEN-P.H_NE-2){1'b0}}};
           endcase
         end else 
           PostBox = In;
@@ -242,32 +245,30 @@ module unpackinput (
         if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive
         else
           case (Fmt)
-              2'b11: Sgn = In[`Q_LEN-1];
-              2'b01: Sgn = In[`D_LEN-1];
-              2'b00: Sgn = In[`S_LEN-1];
-              2'b10: Sgn = In[`H_LEN-1];
+              2'b11: Sgn = In[P.Q_LEN-1];
+              2'b01: Sgn = In[P.D_LEN-1];
+              2'b00: Sgn = In[P.S_LEN-1];
+              2'b10: Sgn = In[P.H_LEN-1];
           endcase
-          
 
       // extract the fraction
       always_comb
           case (Fmt)
-              2'b11: Frac = In[`Q_NF-1:0];
-              2'b01: Frac = {In[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
-              2'b00: Frac = {In[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
-              2'b10: Frac = {In[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
+              2'b11: Frac = In[P.Q_NF-1:0];
+              2'b01: Frac = {In[P.D_NF-1:0], (P.Q_NF-P.D_NF)'(0)};
+              2'b00: Frac = {In[P.S_NF-1:0], (P.Q_NF-P.S_NF)'(0)};
+              2'b10: Frac = {In[P.H_NF-1:0], (P.Q_NF-P.H_NF)'(0)};
           endcase
 
       // is the exponent non-zero
       always_comb
           case (Fmt)
-              2'b11: ExpNonZero = |In[`Q_LEN-2:`Q_NF];
-              2'b01: ExpNonZero = |In[`D_LEN-2:`D_NF];
-              2'b00: ExpNonZero = |In[`S_LEN-2:`S_NF]; 
-              2'b10: ExpNonZero = |In[`H_LEN-2:`H_NF]; 
+              2'b11: ExpNonZero = |In[P.Q_LEN-2:P.Q_NF];
+              2'b01: ExpNonZero = |In[P.D_LEN-2:P.D_NF];
+              2'b00: ExpNonZero = |In[P.S_LEN-2:P.S_NF]; 
+              2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF]; 
           endcase
 
-
       // example double to single conversion:
       // 1023 = 0011 1111 1111
       // 127  = 0000 0111 1111 (subtract this)
@@ -280,20 +281,19 @@ module unpackinput (
       // 1 is added to the exponent if the input is zero or subnormal
       always_comb
           case (Fmt)
-              2'b11: Exp = {In[`Q_LEN-2:`Q_NF+1], In[`Q_NF]|~ExpNonZero};
-              2'b01: Exp = {In[`D_LEN-2], {`Q_NE-`D_NE{~In[`D_LEN-2]}}, In[`D_LEN-3:`D_NF+1], In[`D_NF]|~ExpNonZero};
-              2'b00: Exp = {In[`S_LEN-2], {`Q_NE-`S_NE{~In[`S_LEN-2]}}, In[`S_LEN-3:`S_NF+1], In[`S_NF]|~ExpNonZero};
-              2'b10: Exp = {In[`H_LEN-2], {`Q_NE-`H_NE{~In[`H_LEN-2]}}, In[`H_LEN-3:`H_NF+1], In[`H_NF]|~ExpNonZero}; 
+              2'b11: Exp = {In[P.Q_LEN-2:P.Q_NF+1], In[P.Q_NF]|~ExpNonZero};
+              2'b01: Exp = {In[P.D_LEN-2], {P.Q_NE-P.D_NE{~In[P.D_LEN-2]}}, In[P.D_LEN-3:P.D_NF+1], In[P.D_NF]|~ExpNonZero};
+              2'b00: Exp = {In[P.S_LEN-2], {P.Q_NE-P.S_NE{~In[P.S_LEN-2]}}, In[P.S_LEN-3:P.S_NF+1], In[P.S_NF]|~ExpNonZero};
+              2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero}; 
           endcase
-
-
+  
       // is the exponent all 1's
       always_comb 
           case (Fmt)
-              2'b11: ExpMax = &In[`Q_LEN-2:`Q_NF];
-              2'b01: ExpMax = &In[`D_LEN-2:`D_NF];
-              2'b00: ExpMax = &In[`S_LEN-2:`S_NF];
-              2'b10: ExpMax = &In[`H_LEN-2:`H_NF];
+              2'b11: ExpMax = &In[P.Q_LEN-2:P.Q_NF];
+              2'b01: ExpMax = &In[P.D_LEN-2:P.D_NF];
+              2'b00: ExpMax = &In[P.S_LEN-2:P.S_NF];
+              2'b10: ExpMax = &In[P.H_LEN-2:P.H_NF];
           endcase
 
   end
@@ -302,9 +302,9 @@ module unpackinput (
   assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero?
   assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
   assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
-  assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
+  assign SNaN = NaN&~Frac[P.NF-1]&~BadNaNBox; // is the input a singnaling NaN?
+  assign Inf = ExpMax & FracZero & En; // is the input infinity?
+  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
   assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/generic/adder.sv b/src/generic/adder.sv
index 7acd20df0..4d341d6c1 100644
--- a/src/generic/adder.sv
+++ b/src/generic/adder.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module adder #(parameter WIDTH=8) (
   input  logic [WIDTH-1:0] a, b,
   output logic [WIDTH-1:0] y
@@ -33,5 +31,3 @@ module adder #(parameter WIDTH=8) (
 
   assign y = a + b;
 endmodule 
-
-
diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
index d322216b3..f8d675b33 100644
--- a/src/generic/aplusbeq0.sv
+++ b/src/generic/aplusbeq0.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module aplusbeq0 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a, b,
   output logic             zero
@@ -40,4 +38,4 @@ module aplusbeq0 #(parameter WIDTH = 8) (
   assign x = a ^ b;
   assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};
   assign zero = (x == orshift);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv
index 5a9cf21f0..dd473b307 100644
--- a/src/generic/arrs.sv
+++ b/src/generic/arrs.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module arrs(
   input  logic  clk,
   input  logic  areset,
diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv
index c09f98f2c..c0150133c 100644
--- a/src/generic/clockgater.sv
+++ b/src/generic/clockgater.sv
@@ -24,16 +24,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module clockgater (
+module clockgater #(parameter FPGA) (
   input  logic E,
   input  logic SE,
   input  logic CLK,
   output logic ECLK
 );
 
-  if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
+  if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
   else begin
     // *** BUG 
     // VERY IMPORTANT.
diff --git a/src/generic/counter.sv b/src/generic/counter.sv
index 1480dc929..faba2e5e5 100644
--- a/src/generic/counter.sv
+++ b/src/generic/counter.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module counter #(parameter WIDTH=8) (
   input  logic             clk, reset, en,
   output logic [WIDTH-1:0] q
@@ -36,5 +34,3 @@ module counter #(parameter WIDTH=8) (
   assign qnext = q + 1;
   flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
 endmodule 
-
-
diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv
index 807a6d6ca..6284a454c 100644
--- a/src/generic/decoder.sv
+++ b/src/generic/decoder.sv
@@ -23,8 +23,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module decoder #(parameter BINARY_BITS = 3) (
   input  logic [BINARY_BITS-1:0]      binary,
   output logic [(2**BINARY_BITS)-1:0] onehot
diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv
index 1e906dca8..97e0ac7e4 100644
--- a/src/generic/flop/flop.sv
+++ b/src/generic/flop/flop.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv
index 32e0d7dd3..2e6432519 100644
--- a/src/generic/flop/flopen.sv
+++ b/src/generic/flop/flopen.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv
index 094779c74..562c4565a 100644
--- a/src/generic/flop/flopenl.sv
+++ b/src/generic/flop/flopenl.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,
diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
index 3b8129e40..2c2144ab8 100644
--- a/src/generic/flop/flopenr.sv
+++ b/src/generic/flop/flopenr.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
index b3d5a1e8e..94b2b3cb0 100644
--- a/src/generic/flop/flopenrc.sv
+++ b/src/generic/flop/flopenrc.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv
index 1f4c18051..c4fc5d01b 100644
--- a/src/generic/flop/flopens.sv
+++ b/src/generic/flop/flopens.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
index b2f99b3cd..2e39ee8d6 100644
--- a/src/generic/flop/flopr.sv
+++ b/src/generic/flop/flopr.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv
index 8275a8f96..b35e9ccce 100644
--- a/src/generic/flop/floprc.sv
+++ b/src/generic/flop/floprc.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,
diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv
index f10efaeaf..f99088af4 100644
--- a/src/generic/flop/synchronizer.sv
+++ b/src/generic/flop/synchronizer.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module synchronizer ( 
   input  logic clk,
   input  logic d, 
diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 8905cc551..56637c0ce 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -32,9 +32,7 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
+module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=44) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
@@ -49,7 +47,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
   // ***************************************************************************
   // TRUE SRAM macro
   // ***************************************************************************
-  if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
+  if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     genvar index;
     // 64 x 128-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
@@ -59,7 +57,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
       .A(addr), .D(din), 
       .BWEB(~BitWriteMask), .Q(dout));
     
-  end else if ((`USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     genvar index;
     // 64 x 44-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
@@ -69,7 +67,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
       .A(addr), .D(din), 
       .BWEB(~BitWriteMask), .Q(dout));
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     genvar index;
     // 64 x 22-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index f3a8a2248..24d92ff7f 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -30,9 +30,8 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
+module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
+                   parameter DEPTH=64, WIDTH=44) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
@@ -46,21 +45,21 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
   // ***************************************************************************
   // TRUE SRAM macro
   // ***************************************************************************
-  if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
+  if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     // 64 x 128-bit SRAM
     ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));
     
-  end else if ((`USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     // 64 x 44-bit SRAM
     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     // 64 x 22-bit SRAM
-    ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+    ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));     
     
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 51e2871b4..202d0432b 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -31,9 +31,8 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
+module ram2p1r1wbe import cvw::*; #(parameter cvw_t P,
+                                    parameter DEPTH=1024, WIDTH=68) (
   input  logic                     clk,
   input  logic                     ce1, ce2,
   input  logic [$clog2(DEPTH)-1:0] ra1,
@@ -52,7 +51,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
   // TRUE Smem macro
   // ***************************************************************************
 
-  if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
+  if ((P.USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
     
     ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
@@ -64,7 +63,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
       .QA(rd1),
       .QB());
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
     
     ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
@@ -76,7 +75,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
       .QA(rd1),
       .QB());      
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
 
     logic [SRAMWIDTH-1:0]     SRAMReadData;      
     logic [SRAMWIDTH-1:0]     SRAMWriteData;      
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index ef9c6da37..91133b272 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -25,8 +25,6 @@
 
 // This model actually works correctly with vivado.
 
-`include "wally-config.vh"
-
 module rom1p1r #(parameter ADDR_WIDTH = 8,
      parameter DATA_WIDTH = 32, 
      parameter PRELOAD_ENABLED = 0)
@@ -51,50 +49,51 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
    
    // for FPGA, initialize with zero-stage bootloader
    if(PRELOAD_ENABLED) 
-      initial begin
-   ROM[0] =  64'h9581819300002197; 
-   ROM[1] =  64'h4281420141014081; 
-   ROM[2] =  64'h4481440143814301; 
-   ROM[3] =  64'h4681460145814501; 
-   ROM[4] =  64'h4881480147814701; 
-   ROM[5] =  64'h4a814a0149814901; 
-   ROM[6] =  64'h4c814c014b814b01; 
-   ROM[7] =  64'h4e814e014d814d01; 
-   ROM[8] =  64'h0110011b4f814f01; 
-   ROM[9] =  64'h059b45011161016e; 
-   ROM[10] = 64'h0004063705fe0010; 
-   ROM[11] = 64'h05a000ef8006061b; 
-   ROM[12] = 64'h0ff003930000100f; 
-   ROM[13] = 64'h4e952e3110060e37; 
-   ROM[14] = 64'hc602829b0053f2b7; 
-   ROM[15] = 64'h2023fe02dfe312fd; 
-   ROM[16] = 64'h829b0053f2b7007e; 
-   ROM[17] = 64'hfe02dfe312fdc602; 
-   ROM[18] = 64'h4de31efd000e2023; 
-   ROM[19] = 64'h059bf1402573fdd0; 
-   ROM[20] = 64'h0000061705e20870; 
-   ROM[21] = 64'h0010029b01260613; 
-   ROM[22] = 64'h11010002806702fe; 
-   ROM[23] = 64'h84b2842ae426e822; 
-   ROM[24] = 64'h892ee04aec064511; 
-   ROM[25] = 64'h06e000ef07e000ef; 
-   ROM[26] = 64'h979334fd02905563; 
-   ROM[27] = 64'h07930177d4930204; 
-   ROM[28] = 64'h4089093394be2004; 
-   ROM[29] = 64'h04138522008905b3; 
-   ROM[30] = 64'h19e3014000ef2004; 
-   ROM[31] = 64'h64a2644260e2fe94; 
-   ROM[32] = 64'h6749808261056902; 
-   ROM[33] = 64'hdfed8b8510472783; 
-   ROM[34] = 64'h2423479110a73823; 
-   ROM[35] = 64'h10472783674910f7; 
-   ROM[36] = 64'h20058693ffed8b89; 
-   ROM[37] = 64'h05a1118737836749; 
-   ROM[38] = 64'hfed59be3fef5bc23; 
-   ROM[39] = 64'h1047278367498082; 
-   ROM[40] = 64'h47858082dfed8b85; 
-   ROM[41] = 64'h40a7853b4015551b;   
-   ROM[42] = 64'h808210a7a02367c9;
-      end 
+     initial begin
+       ROM[0] =  64'h95c1819300002197; 
+       ROM[1] =  64'h4281420141014081; 
+       ROM[2] =  64'h4481440143814301; 
+       ROM[3] =  64'h4681460145814501; 
+       ROM[4] =  64'h4881480147814701; 
+       ROM[5] =  64'h4a814a0149814901; 
+       ROM[6] =  64'h4c814c014b814b01; 
+       ROM[7] =  64'h4e814e014d814d01; 
+       ROM[8] =  64'h0110011b4f814f01; 
+       ROM[9] =  64'h059b45011161016e; 
+       ROM[10] = 64'h0004063705fe0010; 
+       ROM[11] = 64'h05a000ef8006061b; 
+       ROM[12] = 64'h0ff003930000100f; 
+       ROM[13] = 64'h4e952e3110060e37; 
+       ROM[14] = 64'hc602829b0053f2b7; 
+       ROM[15] = 64'h2023fe02dfe312fd; 
+       ROM[16] = 64'h829b0053f2b7007e; 
+       ROM[17] = 64'hfe02dfe312fdc602; 
+       ROM[18] = 64'h4de31efd000e2023; 
+       ROM[19] = 64'h059bf1402573fdd0; 
+       ROM[20] = 64'h0000061705e20870; 
+       ROM[21] = 64'h0010029b01260613; 
+       ROM[22] = 64'h71790002806702fe; 
+       ROM[23] = 64'h89aa84b2e44eec26; 
+       ROM[24] = 64'h892ee84af4064511; 
+       ROM[25] = 64'h072000ef084000ef; 
+       ROM[26] = 64'hf02204a602905263; 
+       ROM[27] = 64'h41390933844e94ce; 
+       ROM[28] = 64'h04138522008905b3; 
+       ROM[29] = 64'h19e3016000ef2004; 
+       ROM[30] = 64'h64e270a27402fe94; 
+       ROM[31] = 64'h8082614569a26942; 
+       ROM[32] = 64'h431c104707136749; 
+       ROM[33] = 64'hb82366c9dff58b85; 
+       ROM[34] = 64'h4691674967c910a6; 
+       ROM[35] = 64'h1047071310d7a423; 
+       ROM[36] = 64'h6749fff58b89431c; 
+       ROM[37] = 64'h1187071320058693; 
+       ROM[38] = 64'hfef5bc2305a1631c; 
+       ROM[39] = 64'h67498082fed59ce3; 
+       ROM[40] = 64'h8b85431c10470713; 
+       ROM[41] = 64'h4015551b8082dff5;   
+       ROM[42] = 64'ha0239f0967c94705;
+       ROM[43] = 64'h00000000808210e7;
+     end 
 
 endmodule 
diff --git a/src/generic/mux.sv b/src/generic/mux.sv
index 223d41afc..9c1dfe335 100644
--- a/src/generic/mux.sv
+++ b/src/generic/mux.sv
@@ -24,7 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 /* verilator lint_off DECLFILENAME */
 
 module mux2 #(parameter WIDTH = 8) (
diff --git a/src/generic/neg.sv b/src/generic/neg.sv
index 66be9e073..e971fc232 100644
--- a/src/generic/neg.sv
+++ b/src/generic/neg.sv
@@ -24,12 +24,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module neg #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a,
   output logic [WIDTH-1:0] y);
 
   assign y = ~a + 1;
 endmodule
-
diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
index 5e8f01c26..b672a08e5 100644
--- a/src/generic/onehotdecoder.sv
+++ b/src/generic/onehotdecoder.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module onehotdecoder #(parameter WIDTH = 2) (
   input  logic [WIDTH-1:0]    bin,
   output logic [2**WIDTH-1:0] decoded
diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv
index 160bc7447..476b62586 100644
--- a/src/generic/or_rows.sv
+++ b/src/generic/or_rows.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // perform an OR of all the rows in an array, producing one output for each column
 // equivalent to assign y = a.or
 module or_rows #(parameter ROWS = 8, COLS=2) (
@@ -48,5 +46,3 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
     /* verilator lint_on UNOPTFLAT */
   end
 endmodule
-
-
diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv
index ba5ebb90f..1cddb2bfc 100644
--- a/src/generic/priorityonehot.sv
+++ b/src/generic/priorityonehot.sv
@@ -33,8 +33,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module priorityonehot #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv
index d1970a805..f779d4748 100644
--- a/src/generic/prioritythermometer.sv
+++ b/src/generic/prioritythermometer.sv
@@ -29,8 +29,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module prioritythermometer #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
@@ -48,6 +46,3 @@ module prioritythermometer #(parameter N = 8) (
   end
   /* verilator lint_on UNOPTFLAT */
 endmodule
-
-
-
diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv
index 51f2ccf40..8efa454d9 100644
--- a/src/hazard/hazard.sv
+++ b/src/hazard/hazard.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module hazard (
   // Detect hazards
   input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 43df83b60..1906c85e5 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -27,9 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module alu #(parameter WIDTH=32) (
+module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
   input  logic [WIDTH-1:0] A, B,        // Operands
   input  logic             W64,         // W64-type instruction
   input  logic             SubArith,    // Subtraction or arithmetic shift
@@ -38,6 +36,7 @@ module alu #(parameter WIDTH=32) (
   input  logic [2:0]       ZBBSelect,   // ZBB mux select signal
   input  logic [2:0]       Funct3,      // For BMU decoding
   input  logic [2:0]       BALUControl, // ALU Control signals for B instructions in Execute Stage
+  input  logic             BMUActiveE,  // Bit manipulation instruction being executed
   output logic [WIDTH-1:0] ALUResult,   // ALU result
   output logic [WIDTH-1:0] Sum);        // Sum of operands
 
@@ -56,7 +55,7 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts (configurable for rotation)
-  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
+  shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
 
   // Condition code flags are based on subtraction output Sum = A-B.
   // Overflow occurs when the numbers being subtracted have the opposite sign 
@@ -76,7 +75,7 @@ module alu #(parameter WIDTH=32) (
       3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT};       // slt
       3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU};      // sltu
       3'b100: FullResult = A ^ CondMaskInvB;              // xor, xnor, binv
-      3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
+      3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
       3'b110: FullResult = A | CondMaskInvB;              // or, orn, bset
       3'b111: FullResult = A & CondMaskInvB;              // and, bclr
     endcase
@@ -87,8 +86,8 @@ module alu #(parameter WIDTH=32) (
   else              assign PreALUResult = FullResult;
 
   // Final Result B instruction select mux
-  if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
-    bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, 
+  if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu
+    bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE,
       .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
       .CondMaskB, .CondShiftA, .ALUResult);
   end else begin
@@ -96,4 +95,4 @@ module alu #(parameter WIDTH=32) (
     assign CondMaskB = B;
     assign CondShiftA = A;
   end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv
index 228b23132..706ebdb21 100644
--- a/src/ieu/bmu/bitmanipalu.sv
+++ b/src/ieu/bmu/bitmanipalu.sv
@@ -27,9 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module bitmanipalu #(parameter WIDTH=32) (
+module bitmanipalu import cvw::*; #(parameter cvw_t P, 
+                     parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, B,                    // Operands
   input  logic             W64,                     // W64-type instruction
   input  logic [1:0]       BSelect,                 // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
@@ -38,6 +37,7 @@ module bitmanipalu #(parameter WIDTH=32) (
   input  logic             LT,                      // less than flag
   input  logic             LTU,                     // less than unsigned flag
   input  logic [2:0]       BALUControl,             // ALU Control signals for B instructions in Execute Stage
+  input  logic             BMUActiveE,              // Bit manipulation instruction being executed
   input  logic [WIDTH-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
   output logic [WIDTH-1:0] CondMaskB,               // B is conditionally masked for ZBS instructions
   output logic [WIDTH-1:0] CondShiftA,              // A is conditionally shifted for ShAdd instructions
@@ -51,18 +51,23 @@ module bitmanipalu #(parameter WIDTH=32) (
   logic             PreShift;                       // Inidicates if it is sh1add, sh2add, sh3add instruction
   logic [1:0]       PreShiftAmt;                    // Amount to Pre-Shift A 
   logic [WIDTH-1:0] CondZextA;                      // A Conditional Extend Intermediary Signal
+  logic [WIDTH-1:0] ABMU, BBMU;                     // Gated data inputs to reduce BMU activity
+
+  // gate data inputs to BMU to only operate when BMU is active
+  assign ABMU = A & {WIDTH{BMUActiveE}};
+  assign BBMU = B & {WIDTH{BMUActiveE}};
 
   // Extract control signals from bitmanip ALUControl.
   assign {Mask, PreShift} = BALUControl[1:0];
 
   // Mask Generation Mux
-  if (`ZBS_SUPPORTED) begin: zbsdec
-    decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB);
+  if (P.ZBS_SUPPORTED) begin: zbsdec
+    decoder #($clog2(WIDTH)) maskgen(BBMU[$clog2(WIDTH)-1:0], MaskB);
     mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
   end else assign CondMaskB = B;
  
   // 0-3 bit Pre-Shift Mux
-  if (`ZBA_SUPPORTED) begin: zbapreshift
+  if (P.ZBA_SUPPORTED) begin: zbapreshift
     if (WIDTH == 64) begin
       mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); 
     end else assign CondZextA = A;
@@ -74,18 +79,18 @@ module bitmanipalu #(parameter WIDTH=32) (
   end
 
   // Bit reverse needed for some ZBB, ZBC instructions
-  if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse
-    bitreverse #(WIDTH) brA(.A, .RevA);
+  if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
+    bitreverse #(WIDTH) brA(.A(ABMU), .RevA);
   end
 
   // ZBC Unit
-  if (`ZBC_SUPPORTED) begin: zbc
-    zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult);
+  if (P.ZBC_SUPPORTED) begin: zbc
+    zbc #(WIDTH) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
   end else assign ZBCResult = 0;
 
   // ZBB Unit
-  if (`ZBB_SUPPORTED) begin: zbb
-    zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
+  if (P.ZBB_SUPPORTED) begin: zbb
+    zbb #(WIDTH) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
   end else assign ZBBResult = 0;
 
   // Result Select Mux
diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv
index e2afb0c95..fc2530aab 100644
--- a/src/ieu/bmu/bitreverse.sv
+++ b/src/ieu/bmu/bitreverse.sv
@@ -27,7 +27,6 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
 module bitreverse #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index d1fa909d2..59a8e4a16 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -27,9 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module bmuctrl(
+module bmuctrl import cvw::*;  #(parameter cvw_t P) (
   input  logic        clk, reset,
   // Decode stage control signals
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
@@ -48,7 +46,8 @@ module bmuctrl(
   output logic [1:0]  BSelectE,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
   output logic [2:0]  ZBBSelectE,              // ZBB mux select signal
   output logic        BRegWriteE,              // Indicates if it is a R type B instruction in Execute
-  output logic [2:0]  BALUControlE             // ALU Control signals for B instructions in Execute Stage
+  output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
+  output logic        BMUActiveE               // Bit manipulation instruction being executed
 );
 
   logic [6:0] OpD;                             // Opcode in Decode stage
@@ -76,13 +75,13 @@ module bmuctrl(
   always_comb begin
     // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
     BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1;  // default: Illegal bmu instruction;
-    if (`ZBA_SUPPORTED) begin
+    if (P.ZBA_SUPPORTED) begin
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh1add
         17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh2add
         17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh3add
       endcase
-      if (`XLEN==64)
+      if (P.XLEN==64)
         casez({OpD, Funct7D, Funct3D})
           17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh1add.uw
           17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh2add.uw
@@ -91,7 +90,7 @@ module bmuctrl(
           17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0;  // slli.uw
         endcase
     end
-    if (`ZBB_SUPPORTED) begin
+    if (P.ZBB_SUPPORTED) begin
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // rol
         17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // ror
@@ -100,13 +99,13 @@ module bmuctrl(
                                 else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
                                   BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
 //        // coverage off: This case can't occur in RV64
-//        17'b0110011_0000100_100: if (`XLEN == 32)
+//        17'b0110011_0000100_100: if (P.XLEN == 32)
 //                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
 //        // coverage on
         17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
         17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
         17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor
-        17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
+        17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
                                   BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // rev8
         17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
                                   BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // orc.b
@@ -115,12 +114,12 @@ module bmuctrl(
         17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0;  // min
         17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0;  // minu
       endcase
-      if (`XLEN==32)
+      if (P.XLEN==32)
         casez({OpD, Funct7D, Funct3D})
           17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
           17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0;  // rori (rv32)                          
         endcase
-      else if (`XLEN==64)
+      else if (P.XLEN==64)
         casez({OpD, Funct7D, Funct3D})
           17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0;  // zexth (rv64)
           17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0;  // rolw
@@ -131,25 +130,25 @@ module bmuctrl(
                                     BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0;  // count word instruction
         endcase
     end
-    if (`ZBC_SUPPORTED)
+    if (P.ZBC_SUPPORTED)
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0;  // ZBC instruction
       endcase
-    if (`ZBS_SUPPORTED) begin // ZBS
+    if (P.ZBS_SUPPORTED) begin // ZBS
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0;  // bclr
         17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0;  // bext
         17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0;  // binv
         17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0;  // bset
       endcase
-      if (`XLEN==32) // ZBS 64-bit
+      if (P.XLEN==32) // ZBS 64-bit
         casez({OpD, Funct7D, Funct3D})
           17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri
           17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti
           17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0;  // binvi
           17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti
         endcase
-      else if (`XLEN==64) // ZBS 64-bit
+      else if (P.XLEN==64) // ZBS 64-bit
         casez({OpD, Funct7D, Funct3D})
           17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri (rv64)
           17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti (rv64)
@@ -157,7 +156,7 @@ module bmuctrl(
           17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti (rv64)
         endcase
     end
-    if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
+    if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0;  // sra, srl, sll
         17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0;  // srai, srli, slli
@@ -176,5 +175,5 @@ module bmuctrl(
   assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
 
   // BMU Execute stage pipieline control register
-  flopenrc#(9) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE});
+  flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
 endmodule
diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byteop.sv
similarity index 94%
rename from src/ieu/bmu/byte.sv
rename to src/ieu/bmu/byteop.sv
index 32031059a..2879ba042 100644
--- a/src/ieu/bmu/byte.sv
+++ b/src/ieu/bmu/byteop.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// byte.sv
+// byteop.sv
 //
 // Written: Kevin Kim <kekim@hmc.edu>
 // Created: 1 February 2023
@@ -27,9 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module byteUnit #(parameter WIDTH=32) (
+module byteop #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,             // Operands
   input  logic             ByteSelect,    // LSB of Immediate
   output logic [WIDTH-1:0] ByteResult);   // rev8, orcb result
@@ -43,4 +41,4 @@ module byteUnit #(parameter WIDTH=32) (
   end
 
   mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv
index cf3e1c6b1..675387577 100644
--- a/src/ieu/bmu/clmul.sv
+++ b/src/ieu/bmu/clmul.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module clmul #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] X, Y,             // Operands
   output logic [WIDTH-1:0] ClmulResult);     // ZBS result
diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv
index a1f82eb7e..d015c1195 100644
--- a/src/ieu/bmu/cnt.sv
+++ b/src/ieu/bmu/cnt.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cnt #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A, RevA,    // Operands
   input  logic [1:0]       B,          // Last 2 bits of immediate
@@ -62,4 +60,4 @@ module cnt #(parameter WIDTH = 32) (
   assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
 
   mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv
index 438addaa8..1feca6e1e 100644
--- a/src/ieu/bmu/ext.sv
+++ b/src/ieu/bmu/ext.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ext #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A,            // Operands
   input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
@@ -42,4 +40,4 @@ module ext #(parameter WIDTH = 32) (
   assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
 
   mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
index 1a1b9de24..9ae3df42d 100644
--- a/src/ieu/bmu/zbb.sv
+++ b/src/ieu/bmu/zbb.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module zbb #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, RevA, B,   // Operands
   input  logic             W64,          // Indicates word operation
@@ -47,7 +45,7 @@ module zbb #(parameter WIDTH=32) (
 
   mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
   cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
-  byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
+  byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
   ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
 
   // ZBBSelect[2] differentiates between min(u) vs max(u) instruction
@@ -55,4 +53,4 @@ module zbb #(parameter WIDTH=32) (
 
   // ZBB Result select mux
   mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv
index b173a5f63..4dc3ad1bd 100644
--- a/src/ieu/bmu/zbc.sv
+++ b/src/ieu/bmu/zbc.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module zbc #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, RevA, B,       // Operands
   input  logic [2:0]       Funct3,           // Indicates operation to perform
@@ -48,4 +46,4 @@ module zbc #(parameter WIDTH=32) (
   bitreverse  #(WIDTH) brClmulResult(ClmulResult, RevClmulResult);
 
   mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv
index 5f504dced..0803d8b2f 100644
--- a/src/ieu/comparator.sv
+++ b/src/ieu/comparator.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // This comparator is best
 module comparator #(parameter WIDTH=64) (
   input  logic [WIDTH-1:0] a, b,    // Operands
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 25395825b..ede8f258e 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -27,14 +27,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-
-module controller(
+module controller import cvw::*;  #(parameter cvw_t P) (
   input  logic        clk, reset,
   // Decode stage control signals
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
+  input  logic [1:0]  STATUS_FS,               // is FPU enabled?
+  input  logic [3:0]  ENVCFG_CBE,              // Cache block operation enables
   output logic [2:0]  ImmSrcD,                 // Type of immediate extension
   input  logic        IllegalIEUFPUInstrD,     // Illegal IEU and FPU instruction
   output logic        IllegalBaseInstrD,       // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
@@ -61,6 +60,11 @@ module controller(
   output logic [1:0]  BSelectE,                // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
   output logic [2:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
   output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
+  output logic        BMUActiveE,              // Bit manipulation instruction being executed
+  output logic        MDUActiveE,              // Mul/Div instruction being executed
+  output logic [3:0]  CMOpM,                   // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  output logic        IFUPrefetchE,            // instruction prefetch
+  output logic        LSUPrefetchM,            // data prefetch
 
   // Memory stage control signals
   input  logic        StallM, FlushM,          // Stall, flush Memory stage
@@ -81,16 +85,18 @@ module controller(
   output logic        StoreStallD              // Store (memory write) causes stall
 );
 
+
   logic [6:0] OpD;                             // Opcode in Decode stage
   logic [2:0] Funct3D;                         // Funct3 field in Decode stage
   logic [6:0] Funct7D;                         // Funct7 field in Decode stage
-  logic [4:0] Rs1D;                            // Rs1 source register in Decode stage
+  logic [4:0] Rs1D, Rs2D, RdD;                 // Rs1/2 source register / dest reg in Decode stage
 
-  `define CTRLW 23
+  `define CTRLW 24
 
   // pipelined control signals
   logic        RegWriteD, RegWriteE;           // RegWrite (register will be written)
   logic [2:0]  ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
+  logic [2:0]  PreImmSrcD;                     // Immediate source format (before amending for prefetches)
   logic [1:0]  MemRWD, MemRWE;                 // Store (write to memory)
   logic        ALUOpD;                         // 0 for address generation, 1 for all other operations (must use Funct3)
   logic        BaseW64D;                       // W64 for Base instructions specifically
@@ -104,6 +110,7 @@ module controller(
   logic        CSRReadD;                       // CSR read instruction
   logic [1:0]  AtomicD;                        // Atomic (AMO) instruction
   logic        FenceXD;                        // Fence instruction
+  logic        CMOD;                           // Cache management instruction
   logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
   logic        CSRWriteD, CSRWriteE;           // CSR write
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
@@ -127,100 +134,149 @@ module controller(
   logic [2:0]  ZBBSelectD;                     // ZBB Mux Select Signal
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
-  logic        JFunctD;                        // detect jalr instruction
+  logic        FLSFunctD;                      // Detect floating-point loads and stores
+  logic        JRFunctD;                       // detect jalr instruction
+  logic        FenceFunctD;                    // Detect fence instruction
+  logic        CMOFunctD;                      // Detect CMO instruction
+  logic        AFunctD, AMOFunctD;             // Detect atomic instructions
+  logic        RWFunctD, MWFunctD;             // detect RW/MW instructions
+  logic        PFunctD, CSRFunctD;             // detect privileged / CSR instruction
   logic        FenceM;                         // Fence.I or sfence.VMA instruction in memory stage
   logic [2:0]  ALUSelectD;                     // ALU Output selection mux control
   logic        IWValidFunct3D;                 // Detects if Funct3 is valid for IW instructions
+  logic [3:0]  CMOpD, CMOpE;                   // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  logic        IFUPrefetchD;                   // instruction prefetch
+  logic        LSUPrefetchD, LSUPrefetchE;     // data prefetch
 
   // Extract fields
-  assign OpD = InstrD[6:0];
+  assign OpD     = InstrD[6:0];
   assign Funct3D = InstrD[14:12];
   assign Funct7D = InstrD[31:25];
-  assign Rs1D = InstrD[19:15];
+  assign Rs1D    = InstrD[19:15];
+  assign Rs2D    = InstrD[24:20];
+  assign RdD     = InstrD[11:7];
 
   // Funct 7 checking
   // Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported
   // otherwise be cheap
 
-  if (`ZICSR_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED) begin:legalcheck // Exact integer decoding
+  if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED | P.ZBS_SUPPORTED) begin:legalcheck // Exact integer decoding
     logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
     logic Funct7ShiftZeroD, Funct7Shiftb5D;
 
     assign Funct7ZeroD      = (Funct7D == 7'b0000000); // most R-type instructions
     assign Funct7b5D        = (Funct7D == 7'b0100000); // srai, sub
-    assign Funct7ShiftZeroD = (`XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD;
-    assign Funct7Shiftb5D   = (`XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;
+    assign Funct7ShiftZeroD = (P.XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD;
+    assign Funct7Shiftb5D   = (P.XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;
     assign IShiftD          = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms
     assign INoShiftD        = ((Funct3D != 3'b001) & (Funct3D != 3'b101));
     assign IFunctD          = IShiftD | INoShiftD;
     assign RFunctD          = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD;
-    assign MFunctD          = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
+    assign MFunctD          = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | 
-                              ((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
+                              ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
+    assign FLSFunctD        = (STATUS_FS != 2'b00) & ((Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) |
+                              (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED));
+    assign FenceFunctD      = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001);
+    assign CMOFunctD        = (Funct3D == 3'b010 & RdD == 5'b0) & 
+                              ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) |
+                               (P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) | 
+                                                      (InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2]));
+                               // *** need to get with enable bits such as MENVCFG_CBZE
+    assign AFunctD          = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011);
+    assign AMOFunctD        = (InstrD[31:27] == 5'b00001) |
+                              (InstrD[31:27] == 5'b00000) |
+                              (InstrD[31:27] == 5'b00100) |
+                              (InstrD[31:27] == 5'b01100) |
+                              (InstrD[31:27] == 5'b01000) |
+                              (InstrD[31:27] == 5'b10000) |
+                              (InstrD[31:27] == 5'b10100) |
+                              (InstrD[31:27] == 5'b11000) |
+                              (InstrD[31:27] == 5'b11100);
+    assign RWFunctD         = ((Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101) & Funct7ZeroD |
+                              (Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) & (P.XLEN == 64);
+    assign MWFunctD         = MFunctD & (P.XLEN == 64) & ~(Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b011);
     assign SFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | 
-                              ((`XLEN == 64) & (Funct3D == 3'b011));
-    assign BFunctD          = (Funct3D[2:1] != 2'b01); // legal branches
-    assign JFunctD          = (Funct3D == 3'b000);
+                              ((P.XLEN == 64) & (Funct3D == 3'b011));
+    assign BFunctD          = Funct3D[2:1] != 2'b01; // legal branches
+    assign JRFunctD         = Funct3D == 3'b000;
+    assign PFunctD          = Funct3D == 3'b000 & RdD == 5'b0;
+    assign CSRFunctD        = Funct3D[1:0] != 2'b00; 
     assign IWValidFunct3D   = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101;
   end else begin:legalcheck2
     assign IFunctD = 1; // Don't bother to separate out shift decoding
     assign RFunctD = ~Funct7D[0]; // Not a multiply
-    assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
+    assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD = 1; // don't bother to check Funct3 for loads
+    assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores
+    assign FenceFunctD = 1; // don't bother to check fields for fences
+    assign CMOFunctD = 1; // don't bother to check fields for CMO instructions
+    assign AFunctD = 1; // don't bother to check fields for atomics
+    assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations
+    assign RWFunctD = 1; // don't bother to check fields for RW instructions
+    assign MWFunctD = 1; // don't bother to check fields for MW instructions
     assign SFunctD = 1; // don't bother to check Funct3 for stores
     assign BFunctD = 1; // don't bother to check Funct3 for branches
-    assign JFunctD = 1; // don't bother to check Funct3 for jumps
+    assign JRFunctD = 1; // don't bother to check Funct3 for jalrs
+    assign PFunctD = 1; // don't bother to check fields for privileged instructions
+    assign CSRFunctD = 1; // don't bother to check Funct3 for CSR operations
     assign IWValidFunct3D = 1;
   end
 
   // Main Instruction Decoder
   /* verilator lint_off CASEINCOMPLETE */
   always_comb begin
-    ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction
+    ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_1; // default: Illegal instruction
     case(OpD)
-    // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
-     7'b0000011: if (LFunctD) 
-                      ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads
-      7'b0000111:     ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
-      7'b0001111: if (`ZIFENCEI_SUPPORTED)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
-                  else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
+    // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal
+      7'b0000011: if (LFunctD) 
+                      ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_0; // loads
+      7'b0000111: if (FLSFunctD)  
+                      ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_1; // flw - only legal if FP supported
+      7'b0001111: if (FenceFunctD) begin
+                    if (P.ZIFENCEI_SUPPORTED)
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0_0; // fence
+                    else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // fence treated as nop
+                  end else if (CMOFunctD) begin
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction
+                  end
       7'b0010011: if (IFunctD)    
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
-      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
-      7'b0011011: if (IFunctD & IWValidFunct3D & `XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // I-type ALU
+      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // auipc
+      7'b0011011: if (IFunctD & IWValidFunct3D & P.XLEN == 64)
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // IW-type ALU for RV64i
       7'b0100011: if (SFunctD) 
-                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores
-      7'b0100111:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
-      7'b0101111: if (`A_SUPPORTED) begin
-                    if (InstrD[31:27] == 5'b00010)
-                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
+                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
+      7'b0100111: if (FLSFunctD)
+                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
+      7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
+                    if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
+                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
                     else if (InstrD[31:27] == 5'b00011)
-                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
-                    else 
-                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
+                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
+                    else if (AMOFunctD) 
+                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
                  end
       7'b0110011: if (RFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type 
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type 
                   else if (MFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
-      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
-      7'b0111011: if (RFunctD & (`XLEN == 64))
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
-                  else if (MFunctD & (`XLEN == 64))
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/divide
+      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui
+      7'b0111011: if (RWFunctD)
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i
+                  else if (MWFunctD)
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0_0; // W-type Multiply/Divide
       7'b1100011: if (BFunctD)   
-                      ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
-      7'b1100111: if (JFunctD)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
-      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
-      7'b1110011: if (`ZICSR_SUPPORTED) begin
-                   if (Funct3D == 3'b000)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
-                   else
-                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
+                      ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0_0; // branches
+      7'b1100111: if (JRFunctD)
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jalr
+      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jal
+      7'b1110011: if (P.ZICSR_SUPPORTED) begin
+                   if (PFunctD)
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0_0; // privileged; decoded further in privdec modules
+                   else if (CSRFunctD)
+                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0_0; // csrs
                   end
     endcase
   end
@@ -229,11 +285,11 @@ module controller(
   // Unswizzle control bits
   // Squash control signals if coming from an illegal compressed instruction
   // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
-  assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
+  assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
   //assign IllegalBaseInstrD = 1'b0;
-  assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
+  assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
           ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, 
-          PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
+          PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
   
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
   assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]);            // Don't write if setting or clearing zeros
@@ -247,17 +303,17 @@ module controller(
   assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
 
   // bit manipulation Configuration Block
-  if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
+  if (P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
     logic IllegalBitmanipInstrD;          // Unrecognized B instruction
     logic BRegWriteD;                     // Indicates if it is a R type BMU instruction in decode stage
     logic BW64D;                          // Indicates if it is a W type BMU instruction in decode stage
     logic BSubArithD;                     // TRUE for BMU ext, clr, andn, orn, xnor
     logic BALUSrcBD;                      // BMU alu src select signal
 
-    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, 
+    bmuctrl #(P) bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, 
       .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
-      .ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE);
-    if (`ZBA_SUPPORTED) begin
+      .ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE);
+    if (P.ZBA_SUPPORTED) begin
       // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
       assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
     end else assign sltD = (Funct3D == 3'b010);
@@ -285,12 +341,13 @@ module controller(
     assign BSelectD = 2'b00;
     assign ZBBSelectE = 3'b000;
     assign BALUControlE = 3'b0;
+    assign BMUActiveE = 1'b0;
   end
 
   // Fences
   // Ordinary fence is presently a nop
   // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
-  if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei
+  if (P.ZIFENCEI_SUPPORTED & P.ICACHE_SUPPORTED) begin:fencei
     logic FenceID;
     assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
     assign InvalidateICacheD = FenceID;
@@ -299,14 +356,42 @@ module controller(
     assign InvalidateICacheD = 0;
     assign FlushDCacheD = 0;
   end
- 
+
+  // Cache Management instructions
+  always_comb begin
+    CMOpD = 4'b0000; // default: not a cbo instruction
+    if ((P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) & CMOD) begin
+      CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero
+      CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean
+      CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush 
+      CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval
+    end 
+  end
+
+  // Prefetch Hints
+  always_comb begin
+    // default: not a prefetch hint
+    IFUPrefetchD = 1'b0;
+    LSUPrefetchD = 1'b0;
+    ImmSrcD = PreImmSrcD;
+    if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch
+      case (Rs2D) // which type of prefectch?  Note: prefetch.r and .w are handled the same in Wally
+        5'b00000: IFUPrefetchD = 1'b1; // prefetch.i
+        5'b00001: LSUPrefetchD = 1'b1; // prefetch.r
+        5'b00011: LSUPrefetchD = 1'b1; // prefetch.w
+        // default: not a prefetch hint
+      endcase
+      if (IFUPrefetchD | LSUPrefetchD) ImmSrcD = 3'b001; // use S-type immediate format for prefetches
+    end
+  end
+
   // Decode stage pipeline control register
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic
-  flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE,
-                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
-                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
+  flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE,
+                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, InstrValidD},
+                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, InstrValidE});
 
   // Branch Logic
   //  The comparator handles both signed and unsigned branches using BranchSignedE
@@ -320,13 +405,14 @@ module controller(
   // Other execute stage controller signals
   assign MemReadE = MemRWE[1];
   assign SCE = (ResultSrcE == 3'b100);
+  assign MDUActiveE = (ResultSrcE == 3'b011);
   assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
   assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
   
   // Memory stage pipeline control register
-  flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM});
+  flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
+                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
+                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
   
   // Writeback stage pipeline control register
   flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
@@ -338,5 +424,6 @@ module controller(
 
   // the synchronous DTIM cannot read immediately after write
   // a cache cannot read or write immediately after a write
-  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
+  // atomic operations are also detected as MemRWD[1]
+  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
 endmodule
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
index df9216761..bb7638514 100644
--- a/src/ieu/datapath.sv
+++ b/src/ieu/datapath.sv
@@ -27,113 +27,112 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module datapath (
-  input  logic             clk, reset,
+module datapath import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
   // Decode stage signals
-  input  logic [2:0]       ImmSrcD,                 // Selects type of immediate extension
-  input  logic [31:0]      InstrD,                  // Instruction in Decode stage
+  input  logic [2:0]        ImmSrcD,                 // Selects type of immediate extension
+  input  logic [31:0]       InstrD,                  // Instruction in Decode stage
   // Execute stage signals
-  input  logic [`XLEN-1:0] PCE,                     // PC in Execute stage  
-  input  logic [`XLEN-1:0] PCLinkE,                 // PC + 4 (of instruction in Execute stage)
-  input  logic [2:0]       Funct3E,                 // Funct3 field of instruction in Execute stage
-  input  logic             StallE, FlushE,          // Stall, flush Execute stage
-  input  logic [1:0]       ForwardAE, ForwardBE,    // Forward ALU operands from later stages
-  input  logic             W64E,                    // W64-type instruction
-  input  logic             SubArithE,               // Subtraction or arithmetic shift
-  input  logic             ALUSrcAE, ALUSrcBE,      // ALU operands
-  input  logic             ALUResultSrcE,           // Selects result to pass on to Memory stage
-  input  logic [2:0]       ALUSelectE,              // ALU mux select signal
-  input  logic             JumpE,                   // Is a jump (j) instruction
-  input  logic             BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
-  input  logic [1:0]       BSelectE,                // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
-  input  logic [2:0]       ZBBSelectE,              // ZBB mux select signal
-  input  logic [2:0]       BALUControlE,            // ALU Control signals for B instructions in Execute Stage
-  output logic [1:0]       FlagsE,                  // Comparison flags ({eq, lt})
-  output logic [`XLEN-1:0] IEUAdrE,                 // Address computed by ALU
-  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
+  input  logic [P.XLEN-1:0] PCE,                     // PC in Execute stage  
+  input  logic [P.XLEN-1:0] PCLinkE,                 // PC + 4 (of instruction in Execute stage)
+  input  logic [2:0]        Funct3E,                 // Funct3 field of instruction in Execute stage
+  input  logic              StallE, FlushE,          // Stall, flush Execute stage
+  input  logic [1:0]        ForwardAE, ForwardBE,    // Forward ALU operands from later stages
+  input  logic              W64E,                    // W64-type instruction
+  input  logic              SubArithE,               // Subtraction or arithmetic shift
+  input  logic              ALUSrcAE, ALUSrcBE,      // ALU operands
+  input  logic              ALUResultSrcE,           // Selects result to pass on to Memory stage
+  input  logic [2:0]        ALUSelectE,              // ALU mux select signal
+  input  logic              JumpE,                   // Is a jump (j) instruction
+  input  logic              BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
+  input  logic [1:0]        BSelectE,                // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
+  input  logic [2:0]        ZBBSelectE,              // ZBB mux select signal
+  input  logic [2:0]        BALUControlE,            // ALU Control signals for B instructions in Execute Stage
+  input  logic              BMUActiveE,              // Bit manipulation instruction being executed
+  output logic [1:0]        FlagsE,                  // Comparison flags ({eq, lt})
+  output logic [P.XLEN-1:0] IEUAdrE,                 // Address computed by ALU
+  output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
   // Memory stage signals
-  input  logic             StallM, FlushM,          // Stall, flush Memory stage
-  input  logic             FWriteIntM, FCvtIntW,    // FPU writes integer register file, FPU converts float to int
-  input  logic [`XLEN-1:0] FIntResM,                // FPU integer result
-  output logic [`XLEN-1:0] SrcAM,                   // ALU's Source A in Memory stage to privilege unit for CSR writes
-  output logic [`XLEN-1:0] WriteDataM,              // Write data in Memory stage
+  input  logic              StallM, FlushM,          // Stall, flush Memory stage
+  input  logic              FWriteIntM, FCvtIntW,    // FPU writes integer register file, FPU converts float to int
+  input  logic [P.XLEN-1:0] FIntResM,                // FPU integer result
+  output logic [P.XLEN-1:0] SrcAM,                   // ALU's Source A in Memory stage to privilege unit for CSR writes
+  output logic [P.XLEN-1:0] WriteDataM,              // Write data in Memory stage
   // Writeback stage signals
-  input  logic             StallW, FlushW,          // Stall, flush Writeback stage
-  input  logic             RegWriteW, IntDivW,      // Write register file, integer divide instruction
-  input  logic             SquashSCW,               // Squash a store conditional when a conflict arose
-  input  logic [2:0]       ResultSrcW,              // Select source of result to write back to register file
-  input  logic [`XLEN-1:0] FCvtIntResW,             // FPU convert fp to integer result
-  input  logic [`XLEN-1:0] ReadDataW,               // Read data from LSU
-  input  logic [`XLEN-1:0] CSRReadValW,             // CSR read result
-  input  logic [`XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
-  input  logic [`XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
+  input  logic              StallW, FlushW,          // Stall, flush Writeback stage
+  input  logic              RegWriteW, IntDivW,      // Write register file, integer divide instruction
+  input  logic              SquashSCW,               // Squash a store conditional when a conflict arose
+  input  logic [2:0]        ResultSrcW,              // Select source of result to write back to register file
+  input  logic [P.XLEN-1:0] FCvtIntResW,             // FPU convert fp to integer result
+  input  logic [P.XLEN-1:0] ReadDataW,               // Read data from LSU
+  input  logic [P.XLEN-1:0] CSRReadValW,             // CSR read result
+  input  logic [P.XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
+  input  logic [P.XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
    // Hazard Unit signals 
-  output logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E,  // Register sources to read in Decode or Execute stage
-  output logic [4:0]       RdE, RdM, RdW            // Register destinations in Execute, Memory, or Writeback stage
+  output logic [4:0]        Rs1D, Rs2D, Rs1E, Rs2E,  // Register sources to read in Decode or Execute stage
+  output logic [4:0]        RdE, RdM, RdW            // Register destinations in Execute, Memory, or Writeback stage
 );
 
   // Fetch stage signals
   // Decode stage signals
-  logic [`XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
-  logic [`XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
-  logic [4:0]       RdD;                            // Destination register in Decode stage
+  logic [P.XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
+  logic [P.XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
+  logic [4:0]        RdD;                            // Destination register in Decode stage
   // Execute stage signals
-  logic [`XLEN-1:0] R1E, R2E;                       // Source operands read from register file
-  logic [`XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
-  logic [`XLEN-1:0] SrcAE, SrcBE;                   // ALU operands
-  logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
+  logic [P.XLEN-1:0] R1E, R2E;                       // Source operands read from register file
+  logic [P.XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
+  logic [P.XLEN-1:0] SrcAE, SrcBE;                   // ALU operands
+  logic [P.XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
   // Memory stage signals
-  logic [`XLEN-1:0] IEUResultM;                     // Result from execution stage
-  logic [`XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
+  logic [P.XLEN-1:0] IEUResultM;                     // Result from execution stage
+  logic [P.XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
   // Writeback stage signals
-  logic [`XLEN-1:0] SCResultW;                      // Store Conditional result
-  logic [`XLEN-1:0] ResultW;                        // Result to write to register file
-  logic [`XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
-  logic [`XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
-  logic [`XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
+  logic [P.XLEN-1:0] SCResultW;                      // Store Conditional result
+  logic [P.XLEN-1:0] ResultW;                        // Result to write to register file
+  logic [P.XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
+  logic [P.XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
+  logic [P.XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
 
   // Decode stage
   assign Rs1D      = InstrD[19:15];
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
-  regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
-  extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
+  regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
+  extend #(P)        ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
  
   // Execute stage pipeline register and logic
-  flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
-  flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
-  flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
-  flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
-  flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
+  flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
+  flopenrc #(P.XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
+  flopenrc #(P.XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
+  flopenrc #(5)      Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
+  flopenrc #(5)      Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
+  flopenrc #(5)      RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
   
-  mux3  #(`XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
-  mux3  #(`XLEN)  fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
-  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
-  mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
-  mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
-  alu   #(`XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE);
-  mux2 #(`XLEN)   altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
-  mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
+  mux3  #(P.XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
+  mux3  #(P.XLEN)  fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
+  comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
+  mux2  #(P.XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
+  mux2  #(P.XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
+  alu   #(P, P.XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE);
+  mux2  #(P.XLEN)  altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
+  mux2  #(P.XLEN)  ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
 
   // Memory stage pipeline register
-  flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
-  flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
-  flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);  
-  flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
+  flopenrc #(P.XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
+  flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
+  flopenrc #(5)      RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);  
+  flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
   
   // Writeback stage pipeline register and logic
-  flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
-  flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
+  flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
+  flopenrc #(5)      RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
 
   // floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt
-  if (`F_SUPPORTED) begin:fpmux
-    mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
-    mux2  #(`XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
-    if (`IDIV_ON_FPU) begin
-      mux2  #(`XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
+  if (P.F_SUPPORTED) begin:fpmux
+    mux2  #(P.XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
+    mux2  #(P.XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
+    if (P.IDIV_ON_FPU) begin
+      mux2  #(P.XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
     end else begin 
       assign MulDivResultW = MDUResultW;
     end
@@ -142,9 +141,9 @@ module datapath (
     assign IFCvtResultW = IFResultW;
     assign MulDivResultW = MDUResultW;
   end
-  mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
+  mux5  #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
  
   // handle Store Conditional result if atomic extension supported
-  if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
-  else              assign SCResultW = 0;
-endmodule
\ No newline at end of file
+  if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
+  else               assign SCResultW = 0;
+endmodule
diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv
index 51a10a46c..bcda43e0a 100644
--- a/src/ieu/extend.sv
+++ b/src/ieu/extend.sv
@@ -27,30 +27,29 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+module extend import cvw::*;  #(parameter cvw_t P) (
+  input  logic [31:7]       InstrD,       // All instruction bits except opcode (lower 7 bits)
+  input  logic [2:0]        ImmSrcD,      // Select what kind of extension to perform
+  output logic [P.XLEN-1:0] ImmExtD);     // Extended immediate
 
-module extend (
-  input  logic [31:7]       InstrD,      // All instruction bits except opcode (lower 7 bits)
-  input  logic [2:0]        ImmSrcD,     // Select what kind of extension to perform
-  output logic [`XLEN-1:0 ] ImmExtD);    // Extended immediate
-
-  localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
+  localparam [P.XLEN-1:0] undefined = {(P.XLEN){1'bx}}; // could change to 0 after debug
  
   always_comb
-    case(ImmSrcD) 
+    case (ImmSrcD) 
       // I-type 
-      3'b000:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:20]};  
+      3'b000:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:20]};  
       // S-type (stores)
-      3'b001:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; 
+      3'b001:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]};
       // B-type (branches)
-      3'b010:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
+      3'b010:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
       // J-type (jal)
-      3'b011:   ImmExtD = {{(`XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
+      3'b011:   ImmExtD = {{(P.XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
       // U-type (lui, auipc)
-      3'b100:  ImmExtD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
+      3'b100:   ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
       // Store Conditional: zero offset
-      3'b101:  if (`A_SUPPORTED) ImmExtD = 0;
-               else              ImmExtD = undefined;
+      3'b101:  if (P.A_SUPPORTED) ImmExtD = 0;
+               else             ImmExtD = undefined;
       default: ImmExtD = undefined; // undefined
     endcase  
+
 endmodule
diff --git a/src/ieu/forward.sv b/src/ieu/forward.sv
index 62cc5ea4f..ef3cd4b4b 100644
--- a/src/ieu/forward.sv
+++ b/src/ieu/forward.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module forward(
   // Detect hazards
   input  logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
index 02fa1dd7c..2656b003d 100644
--- a/src/ieu/ieu.sv
+++ b/src/ieu/ieu.sv
@@ -26,45 +26,49 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module ieu (
+module ieu import cvw::*;  #(parameter cvw_t P) (
   input  logic              clk, reset,
   // Decode stage signals
   input  logic [31:0]       InstrD,                          // Instruction
+  input  logic [1:0]        STATUS_FS,                       // is FPU enabled?
+  input  logic [3:0]        ENVCFG_CBE,                      // Cache block operation enables
   input  logic              IllegalIEUFPUInstrD,             // Illegal instruction
   output logic              IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
   // Execute stage signals
-  input  logic [`XLEN-1:0]  PCE,                             // PC
-  input  logic [`XLEN-1:0]  PCLinkE,                         // PC + 4
+  input  logic [P.XLEN-1:0] PCE,                             // PC
+  input  logic [P.XLEN-1:0] PCLinkE,                         // PC + 4
   output logic              PCSrcE,                          // Select next PC (between PC+4 and IEUAdrE)
   input  logic              FWriteIntE, FCvtIntE,            // FPU writes to integer register file, FPU converts float to int
-  output logic [`XLEN-1:0]  IEUAdrE,                         // Memory address
+  output logic [P.XLEN-1:0] IEUAdrE,                         // Memory address
   output logic              IntDivE, W64E,                   // Integer divide, RV64 W-type instruction 
   output logic [2:0]        Funct3E,                         // Funct3 instruction field
-  output logic [`XLEN-1:0]  ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
+  output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
   output logic [4:0]        RdE,                             // Destination register
+  output logic              MDUActiveE,                      // Mul/Div instruction being executed
+  output logic [3:0]        CMOpM,                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  output logic              IFUPrefetchE,                    // instruction prefetch
+  output logic              LSUPrefetchM,                    // datata prefetch
   // Memory stage signals
   input  logic              SquashSCW,                       // Squash store conditional, from LSU
   output logic [1:0]        MemRWM,                          // Read/write control goes to LSU
   output logic [1:0]        AtomicM,                         // Atomic control goes to LSU
-  output logic [`XLEN-1:0]  WriteDataM,                      // Write data to LSU
+  output logic [P.XLEN-1:0] WriteDataM,                      // Write data to LSU
   output logic [2:0]        Funct3M,                         // Funct3 (size and signedness) to LSU
-  output logic [`XLEN-1:0]  SrcAM,                           // ALU SrcA to Privileged unit and FPU
+  output logic [P.XLEN-1:0] SrcAM,                           // ALU SrcA to Privileged unit and FPU
   output logic [4:0]        RdM,                             // Destination register
-  input  logic [`XLEN-1:0]  FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
+  input  logic [P.XLEN-1:0] FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
   output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic              InstrValidD, InstrValidE, InstrValidM,// Instruction is valid
+  output logic              InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
   output logic              BranchD, BranchE,
   output logic              JumpD, JumpE,
   // Writeback stage signals
-  input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
-  input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
-  input  logic [`XLEN-1:0]  MDUResultW,                      // multiply/divide unit result
-  input  logic [`XLEN-1:0]  FCvtIntResW,                     // FPU's float to int conversion result
+  input  logic [P.XLEN-1:0] FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
+  input  logic [P.XLEN-1:0] CSRReadValW,                     // CSR read value, 
+  input  logic [P.XLEN-1:0] MDUResultW,                      // multiply/divide unit result
+  input  logic [P.XLEN-1:0] FCvtIntResW,                     // FPU's float to int conversion result
   input  logic              FCvtIntW,                        // FPU converts float to int
   output logic [4:0]        RdW,                             // Destination register
-  input  logic [`XLEN-1:0]  ReadDataW,                       // LSU's read data
+  input  logic [P.XLEN-1:0] ReadDataW,                       // LSU's read data
   // Hazard unit signals
   input  logic              StallD, StallE, StallM, StallW,  // Stall signals from hazard unit
   input  logic              FlushD, FlushE, FlushM, FlushW,  // Flush signals
@@ -95,20 +99,22 @@ module ieu (
   logic       MemReadE, CSRReadE;                            // Load, CSRRead instruction
   logic       BranchSignedE;                                 // Branch does signed comparison on operands
   logic       MDUE;                                          // Multiply/divide instruction
+  logic       BMUActiveE;                                    // Bit manipulation instruction being executed
            
-controller c(
-    .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
+  controller #(P) c(
+    .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, 
-    .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM,
-    .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
+    .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, 
+    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
+    .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);
 
-  datapath   dp(
+  datapath #(P) dp(
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
     .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, 
-    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE,
+    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE,
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
     .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
@@ -119,4 +125,3 @@ controller c(
     .FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
     .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
 endmodule
-
diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv
index 967a2101e..2b76bca17 100644
--- a/src/ieu/regfile.sv
+++ b/src/ieu/regfile.sv
@@ -27,18 +27,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module regfile (
+module regfile #(parameter XLEN, E_SUPPORTED) (
   input  logic             clk, reset,
   input  logic             we3,                 // Write enable
   input  logic [4:0]       a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
-  input  logic [`XLEN-1:0] wd3,                 // Write data for port 3
-  output logic [`XLEN-1:0] rd1, rd2);           // Read data for ports 1, 2
+  input  logic [XLEN-1:0]  wd3,                 // Write data for port 3
+  output logic [XLEN-1:0]  rd1, rd2);           // Read data for ports 1, 2
 
-  localparam NUMREGS = `E_SUPPORTED ? 16 : 32;  // only 16 registers in E mode
+  localparam NUMREGS = E_SUPPORTED ? 16 : 32;   // only 16 registers in E mode
 
-  logic [`XLEN-1:0] rf[NUMREGS-1:1];
+  logic [XLEN-1:0] rf[NUMREGS-1:1];
   integer i;
 
   // Three ported register file
@@ -52,7 +50,7 @@ module regfile (
     
   always_ff @(negedge clk)
     if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
-    else       if (we3)            rf[a3] <= wd3;  
+    else       if (we3)                 rf[a3] <= wd3;  
 
   assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
   assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;
diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv
index 11ae1cf0a..bb0160c71 100644
--- a/src/ieu/shifter.sv
+++ b/src/ieu/shifter.sv
@@ -27,21 +27,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module shifter (
-  input  logic [`XLEN-1:0]     A,                             // shift Source
-  input  logic [`LOG_XLEN-1:0] Amt,                           // Shift amount
+module shifter import cvw::*; #(parameter cvw_t P) (
+  input  logic [P.XLEN-1:0]     A,                             // shift Source
+  input  logic [P.LOG_XLEN-1:0] Amt,                           // Shift amount
   input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
-  output logic [`XLEN-1:0]     Y);                            // Shifted result
+  output logic [P.XLEN-1:0]     Y);                            // Shifted result
 
-  logic [2*`XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
-  logic [`LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
+  logic [2*P.XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [P.LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
   logic                        Sign;                          // Sign bit for sign extension
 
-  assign Sign = A[`XLEN-1] & SubArith;  // sign bit for sign extension
-  if (`XLEN==32) begin // rv32
-    if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
+  assign Sign = A[P.XLEN-1] & SubArith;  // sign bit for sign extension
+  if (P.XLEN==32) begin // rv32
+    if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
       always_comb  // funnel mux
         case({Right, Rotate})
           2'b00: Z = {A[31:0], 31'b0};
@@ -56,12 +54,12 @@ module shifter (
     end
     assign TruncAmt = Amt; // shift amount
   end else begin // rv64
-    logic [`XLEN-1:0]         A64;                            
+    logic [P.XLEN-1:0]         A64;                            
     mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
-    if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
+    if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
       // shifter rotate source select mux
-      logic [`XLEN-1:0]   RotA;                          // rotate source
-      mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
+      logic [P.XLEN-1:0]   RotA;                          // rotate source
+      mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
       always_comb  // funnel mux
         case ({Right, Rotate})
           2'b00: Z = {A64[63:0],{63'b0}};
@@ -82,7 +80,5 @@ module shifter (
   
   // Funnel operation
   assign ZShift = Z >> Offset;
-  assign Y = ZShift[`XLEN-1:0];    
+  assign Y = ZShift[P.XLEN-1:0];    
 endmodule
-
-
diff --git a/src/ifu/CodeAligner.py b/src/ifu/CodeAligner.py
deleted file mode 100644
index 579fd6237..000000000
--- a/src/ifu/CodeAligner.py
+++ /dev/null
@@ -1,112 +0,0 @@
-import os
-
-# Kevin Wan kewan@hmc.edu 10/27/2021
-def read_input(filename):  #1
-    """Takes in a string filename and outputs the parsed verilog code by line into a list
-    such that each element of the list is one line of verilog code as a string."""
-    lineOfCode = []
-    input_file = open(filename, 'r')
-    for line in input_file:
-        lineOfCode.append(line)
-    return lineOfCode
-###################################################################################
-def ID_start(GiantString):#2
-    """takes in the list of sv file lines, outputs the location that variable names should start"""
-    VarLoc = 0 
-    VarLineNum = None
-    for lines in GiantString:
-        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
-            if "[" in lines and "]" in lines:# need to account for these space
-                NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear. 
-                if NowLoc>VarLoc: 
-                    VarLoc = NowLoc
-                    VarLineNum = GiantString.index(lines) # Update this number if new record is made. 
-            else:   
-                NowLoc = lines.find('logic') + 7 # same as before.
-                if NowLoc>VarLoc: 
-                    VarLoc = NowLoc
-                    VarLineNum = GiantString.index(lines)
-    #print("Furthest variable appears on line", VarLineNum + 1,VarLoc)   # Disable this line after debugging. 
-    return VarLoc
-##################################################################################
-def modified_logNew(GS,SOV): #3
-    Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it. 
-    Out = []
-    for l in GS:
-        lines = l.replace('\t',' ')
-
-        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
-            if "[" in lines and "]" in lines: # the line is an extended declaration. 
-                EditLoc = lines.find("]") # Re-finds the string index number of ]. 
-                VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1  # Checks where variable declaration currently is at. 
-                #print(VarLoc,lines[VarLoc])# VERIFIED
-                NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind) 
-                Out.append(NewLine)# Verified0957 10272021
-            else:
-                EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
-
-                VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
-                NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
-
-                Out.append(NewLine1)# Verified 1005 10272021
-        else:
-            Out.append(lines)
-    return Out   
-################################################################################
-def write_to_output(filename,GiantString,OW=True,Lines_editted=None):   #4
- """Filename is preferrably passed from the early function calls"""
- """GiantString has all the corrected features in the code, each line is a good verilog code line"""
- newname = filename
- if not OW or OW =='f':   #which means no overwrite (create a new file)
-  Decomposed=filename.split('.')
-  newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned. 
-  
- OutFile = open(newname,'w') # This step should create a new file. 
- OutFile.writelines(GiantString)
- OutFile.close()
- print("Success! " + newname + " Now contains an aligned file!")
- return newname
-#################################################################################
-
-def FindCharRel(Ln):
-    #returns the computer location of a character's first occurence
-    for num in range(len(Ln)):
-        if Ln[num] != " ":
-            return num 
-
-
-def Mod_Space_at(Ln,loc,diff):
-    #loc is the varLoc from mln, diff is varLoc - Ind
-    if diff > 0: # to delete
-        NewString = Ln[:(loc-diff)] + Ln[loc:]
-        
-    if diff < 0: # to add
-        NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
-    if diff == 0:
-        NewString = Ln
-    
-    return NewString
-
-'''def main_filehandler(overwrite=False):
-    for filename in os.listdir():
-        if ".sv" in filename:
-            GiantString = read_input(filename)
-            SOV = ID_start(GiantString)
-            ModifiedGS = modified_logNew(GiantString,SOV)
-            Newname = write_to_output(filename,ModifiedGS,overwrite)'''
-def root_filehandler(path,overwrite=False):
-    for f in os.listdir(path):
-        if os.path.isdir(f):
-            root_filehandler(path+"/"+f)
-        else:
-            if ".sv" in f:
-                GiantString = read_input(f)
-                SOV = ID_start(GiantString)
-                ModifiedGS = modified_logNew(GiantString,SOV)
-                Newname = write_to_output(f,ModifiedGS,overwrite)
-                
-                
-def driver(overwrite=False):
-    root_filehandler(os.getcwd())
- 
-driver(True)
\ No newline at end of file
diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 21cad922f..5dd3cf7b2 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -27,9 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module RASPredictor #(parameter int StackSize = 16 )(
+module RASPredictor import cvw::*;  #(parameter cvw_t P, 
+                                      parameter StackSize = 16 )(
   input  logic             clk,
   input  logic             reset, 
   input  logic             StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
@@ -37,15 +36,15 @@ module RASPredictor #(parameter int StackSize = 16 )(
   input  logic             ReturnD,
   input  logic             ReturnE, CallE,                  // Instr class
   input  logic             BPReturnF,
-  input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a call
-  output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
+  input  logic [P.XLEN-1:0] PCLinkE,                                   // PC of instruction after a call
+  output logic [P.XLEN-1:0] RASPCF                                     // Top of the stack
    );
 
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
   logic [Depth-1:0]         NextPtr, Ptr, P1, M1, IncDecPtr;
-  logic [StackSize-1:0]     [`XLEN-1:0] memory;
+  logic [StackSize-1:0]     [P.XLEN-1:0] memory;
   integer        index;
 
   logic      PopF;
@@ -85,7 +84,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
   always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
-    memory[index] <= {`XLEN{1'b0}};
+    memory[index] <= {P.XLEN{1'b0}};
     end else if(PushE) begin
       memory[NextPtr] <= #1 PCLinkE;
     end
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 881150b3f..13439cd43 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -26,27 +26,25 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 `define INSTR_CLASS_PRED 1
 
-module bpred (
+module bpred import cvw::*;  #(parameter cvw_t P) (
   input  logic             clk, reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
   // Fetch stage
   // the prediction
   input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-  input  logic [`XLEN-1:0] PCNextF,                   // Next Fetch Address
-  input  logic [`XLEN-1:0] PCPlus2or4F,               // PCF+2/4
-  output logic [`XLEN-1:0] PC1NextF,                  // Branch Predictor predicted or corrected fetch address on miss prediction
-  output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
+  input  logic [P.XLEN-1:0] PCNextF,                   // Next Fetch Address
+  input  logic [P.XLEN-1:0] PCPlus2or4F,               // PCF+2/4
+  output logic [P.XLEN-1:0] PC1NextF,                  // Branch Predictor predicted or corrected fetch address on miss prediction
+  output logic [P.XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
 
   // Update Predictor
-  input  logic [`XLEN-1:0] PCF,                       // Fetch stage instruction address
-  input  logic [`XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-  input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
-  input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
+  input  logic [P.XLEN-1:0] PCF,                       // Fetch stage instruction address
+  input  logic [P.XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+  input  logic [P.XLEN-1:0] PCE,                       // Execution stage instruction address
+  input  logic [P.XLEN-1:0] PCM,                       // Memory stage instruction address
 
   input  logic [31:0]      PostSpillInstrRawF,        // Instruction
 
@@ -55,9 +53,9 @@ module bpred (
   input  logic             BranchD, BranchE,
   input  logic             JumpD, JumpE,
   input  logic             PCSrcE,                    // Executation stage branch is taken
-  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input  logic [`XLEN-1:0] IEUAdrM,                   // The branch/jump target address
-  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [P.XLEN-1:0] IEUAdrE,                   // The branch/jump target address
+  input  logic [P.XLEN-1:0] IEUAdrM,                   // The branch/jump target address
+  input  logic [P.XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
@@ -71,21 +69,21 @@ module bpred (
 
   logic [1:0]              BPDirPredF;
 
-  logic [`XLEN-1:0]        BPBTAF, RASPCF;
+  logic [P.XLEN-1:0]        BPBTAF, RASPCF;
   logic                    BPPCWrongE;
   logic                    IClassWrongE;
   logic                    BPDirPredWrongE;
   
   logic                    BPPCSrcF;
-  logic [`XLEN-1:0]        BPPCF;
-  logic [`XLEN-1:0]        PC0NextF;
-  logic [`XLEN-1:0]        PCCorrectE;
+  logic [P.XLEN-1:0]        BPPCF;
+  logic [P.XLEN-1:0]        PC0NextF;
+  logic [P.XLEN-1:0]        PCCorrectE;
   logic [3:0]              WrongPredInstrClassD;
 
   logic                    BTBTargetWrongE;
   logic                    RASTargetWrongE;
 
-  logic [`XLEN-1:0]        BPBTAD;
+  logic [P.XLEN-1:0]        BPBTAD;
 
   logic                    BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
   logic                    BPBranchF, BPJumpF, BPReturnF, BPCallF;
@@ -95,57 +93,58 @@ module bpred (
   logic                    BranchM, JumpM, ReturnM, CallM;
   logic                    BranchW, JumpW, ReturnW, CallW;
   logic                    BPReturnWrongD;
-  logic [`XLEN-1:0]        BPBTAE;
+  logic [P.XLEN-1:0]        BPBTAE;
   
   // Part 1 branch direction prediction
-  // look into the 2 port Sram model. something is wrong. 
-  if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor
-    twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
+  if (P.BPRED_TYPE == BP_TWOBIT) begin:Predictor
+    twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
       .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
-  end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
-    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  end else if (P.BPRED_TYPE == BP_GSHARE) begin:Predictor
+    gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, 
       .PCSrcE);
 
-  end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
-    gshare #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  end else if (P.BPRED_TYPE == BP_GLOBAL) begin:Predictor
+    gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
       .PCSrcE);
 
-  end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
-    gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  end else if (P.BPRED_TYPE == BP_GSHARE_BASIC) begin:Predictor
+    gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
-  end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
-    gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  end else if (P.BPRED_TYPE == BP_GLOBAL_BASIC) begin:Predictor
+    gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   
-  end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
-    // *** Fix me
-/* -----\/----- EXCLUDED -----\/-----
-    localHistoryPredictor DirPredictor(.clk,
-      .reset, .StallF, .StallE,
-      .LookUpPC(PCNextF),
-      .Prediction(BPDirPredF),
-      // update
-      .UpdatePC(PCE),
-      .UpdateEN(InstrClassE[0] & ~StallE),
-      .PCSrcE,
-      .UpdatePrediction(InstrClassE[0]));
- -----/\----- EXCLUDED -----/\----- */
+  end else if (P.BPRED_TYPE == BP_LOCAL_BASIC) begin:Predictor
+    localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .BranchE, .BranchM, .PCSrcE);
+  end else if (P.BPRED_TYPE == BP_LOCAL_AHEAD) begin:Predictor
+    localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .BranchE, .BranchM, .PCSrcE);
+  end else if (P.BPRED_TYPE == BP_LOCAL_REPAIR) begin:Predictor
+    localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .BranchD, .BranchE, .BranchM, .PCSrcE);
   end 
 
   // Part 2 Branch target address prediction
   // BTB contains target address for all CFI
 
-  btb #(`BTB_SIZE) 
+  btb #(P, P.BTB_SIZE) 
     TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM,
       .BPBTAF, .BPBTAD, .BPBTAE,
@@ -157,13 +156,13 @@ module bpred (
       .InstrClassM({CallM, ReturnM, JumpM, BranchM}),
       .InstrClassW({CallW, ReturnW, JumpW, BranchW}));
 
-  icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
     .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
     .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
     .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .BPReturnWrongD);
 
   // Part 3 RAS
-  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+  RASPredictor #(P) RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
     .BPReturnF, .ReturnD, .ReturnE, .CallE,
     .BPReturnWrongD, .RASPCF, .PCLinkE);
 
@@ -179,21 +178,21 @@ module bpred (
   
   // Output the predicted PC or corrected PC on miss-predict.
   assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF;
-  mux2 #(`XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF);
+  mux2 #(P.XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF);
   // Selects the BP or PC+2/4.
-  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF);
+  mux2 #(P.XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF);
   // If the prediction is wrong select the correct address.
-  mux2 #(`XLEN) pcmux1(PC0NextF, PCCorrectE, BPWrongE, PC1NextF);  
+  mux2 #(P.XLEN) pcmux1(PC0NextF, PCCorrectE, BPWrongE, PC1NextF);  
   // Correct branch/jump target.
-  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
+  mux2 #(P.XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
   
   // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
   // Effectively this is PCM+4 or the non-existant PCLinkM
-  if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
+  if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
   else  assign NextValidPCE = PCE;
 
-  if(`ZICOUNTERS_SUPPORTED) begin
-    logic [`XLEN-1:0]       RASPCD, RASPCE;
+  if(P.ZIHPM_SUPPORTED) begin
+    logic [P.XLEN-1:0]       RASPCD, RASPCE;
     logic                   BTAWrongE, RASPredPCWrongE;  
     // performance counters
     // 1. class         (class wrong / minstret) (IClassWrongM / csr)                    // Correct now
@@ -209,8 +208,8 @@ module bpred (
     assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 
-    flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
-    flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
+    flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
+    flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
     flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
       {BPDirPredWrongE, BTAWrongE, RASPredPCWrongE},
       {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 2689b4128..e93c1decb 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -28,22 +28,21 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module btb #(parameter Depth = 10 ) (
+module btb import cvw::*;  #(parameter cvw_t P, 
+                             parameter Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
-  output logic [`XLEN-1:0] BPBTAF,                      // BTB's guess at PC
-  output logic [`XLEN-1:0] BPBTAD,
-  output logic [`XLEN-1:0] BPBTAE,
+  input  logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
+  output logic [P.XLEN-1:0] BPBTAF,                      // BTB's guess at PC
+  output logic [P.XLEN-1:0] BPBTAD,
+  output logic [P.XLEN-1:0] BPBTAE,
   output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
   // update
   input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
   input  logic             IClassWrongE,
-  input  logic [`XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
-  input  logic [`XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
+  input  logic [P.XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
+  input  logic [P.XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
   input  logic [3:0]       InstrClassD,                 // Instruction class to insert into btb
   input  logic [3:0]       InstrClassE,                 // Instruction class to insert into btb
   input  logic [3:0]       InstrClassM,                 // Instruction class to insert into btb
@@ -51,12 +50,12 @@ module btb #(parameter Depth = 10 ) (
 );
 
   logic [Depth-1:0]        PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex;
-  logic [`XLEN-1:0]        ResetPC;
+  logic [P.XLEN-1:0]        ResetPC;
   logic                    MatchD, MatchE, MatchM, MatchW, MatchX;
-  logic [`XLEN+3:0]        ForwardBTBPrediction, ForwardBTBPredictionF;
-  logic [`XLEN+3:0]        TableBTBPredF;
-  logic [`XLEN-1:0]        IEUAdrW;
-  logic [`XLEN-1:0]        PCW;
+  logic [P.XLEN+3:0]        ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [P.XLEN+3:0]        TableBTBPredF;
+  logic [P.XLEN-1:0]        IEUAdrW;
+  logic [P.XLEN-1:0]        PCW;
   logic                    BTBWrongE, BPBTAWrongE;
   logic                    BTBWrongM, BPBTAWrongM;
   
@@ -75,7 +74,7 @@ module btb #(parameter Depth = 10 ) (
   // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
   // While the mux could be included in IFU it is not necessary for the IROM/I$/bus.
   // For now it is optimal to leave it here.
-  assign ResetPC = `RESET_VECTOR;
+  assign ResetPC = P.RESET_VECTOR[P.XLEN-1:0];
   assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 
 
   assign MatchD = PCFIndex == PCDIndex;
@@ -93,22 +92,22 @@ module btb #(parameter Depth = 10 ) (
 
 
   // An optimization may be using a PC relative address.
-  ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
+  ram2p1r1wbe #(P, 2**Depth, P.XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
      .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
 
-  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD);
+  flopenrc #(P.XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD);
 
   // BPBTAE is not strickly necessary.  However it is used by two parts of wally.
   // 1. It gates updates to the BTB when the prediction does not change.  This save power.
   // 2. BPBTAWrongE is used by the performance counters to track when the BTB's BPBTA or instruction class is wrong.
-  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE);
+  flopenrc #(P.XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE);
   assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]);
 
   flopenrc #(1) BPBTAWrongMReg(clk, reset, FlushM, ~StallM, BPBTAWrongE, BPBTAWrongM);  
   assign BTBWrongM = BPBTAWrongM | IClassWrongM;
   
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-  flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
+  flopenr #(P.XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+  flopenr #(P.XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
 
 endmodule
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index 4f2cd83cf..460acbcbf 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -27,9 +27,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
-module gshare #(parameter k = 10,
+module gshare import cvw::*; #(parameter cvw_t P,
+                               parameter XLEN, 
+                parameter k = 10,
                 parameter integer TYPE = 1) (
   input logic             clk,
   input logic             reset,
@@ -38,7 +39,7 @@ module gshare #(parameter k = 10,
   output logic [1:0]      BPDirPredF, 
   output logic            BPDirPredWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic [XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
   input logic             BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE
 );
 
@@ -83,7 +84,7 @@ module gshare #(parameter k = 10,
   
   assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
 
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(TableBPDirPredF),
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
index 0adcfbb07..2914c3e3f 100644
--- a/src/ifu/bpred/gsharebasic.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -27,9 +27,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module gsharebasic #(parameter k = 10,
+module gsharebasic import cvw::*; #(parameter cvw_t P,
+                     parameter XLEN,
+                     parameter k = 10,
                      parameter TYPE = 1) (
   input logic             clk,
   input logic             reset,
@@ -38,7 +38,7 @@ module gsharebasic #(parameter k = 10,
   output logic [1:0]      BPDirPredF, 
   output logic            BPDirPredWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic [XLEN-1:0] PCNextF, PCM,
   input logic             BranchE, BranchM, PCSrcE
 );
 
@@ -58,7 +58,7 @@ module gsharebasic #(parameter k = 10,
   assign IndexM = GHRM;
   end
   
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(BPDirPredF),
diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv
index 82e1feebf..65e60c59c 100644
--- a/src/ifu/bpred/icpred.sv
+++ b/src/ifu/bpred/icpred.sv
@@ -26,10 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-
-module icpred #(parameter INSTR_CLASS_PRED = 1)(
+module icpred import cvw::*;  #(parameter cvw_t P, 
+                                parameter INSTR_CLASS_PRED = 1)(
   input  logic             clk, reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
@@ -56,10 +54,10 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
     logic     ccall, cj, cjr, ccallr, CJumpF, CBranchF;
     logic     NCJumpF, NCBranchF;
 
-    if(`C_SUPPORTED) begin
+    if(P.C_SUPPORTED) begin
       logic [4:0] CompressedOpcF;
       assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
-      assign ccall = CompressedOpcF == 5'h09 & `XLEN == 32;
+      assign ccall = CompressedOpcF == 5'h09 & P.XLEN == 32;
       assign cj = CompressedOpcF == 5'h0d;
       assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
       assign ccallr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
@@ -72,13 +70,13 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
     assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
     assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
     
-    assign BPBranchF = NCBranchF | (`C_SUPPORTED & CBranchF);
-    assign BPJumpF = NCJumpF | (`C_SUPPORTED & (CJumpF));
+    assign BPBranchF = NCBranchF | (P.C_SUPPORTED & CBranchF);
+    assign BPJumpF = NCJumpF | (P.C_SUPPORTED & (CJumpF));
     assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // returnurn must returnurn to ra or r5
-        (`C_SUPPORTED & (ccallr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+        (P.C_SUPPORTED & (ccallr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
     
     assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
-        (`C_SUPPORTED & (ccall | (ccallr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+        (P.C_SUPPORTED & (ccall | (ccallr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 
   end else begin
     // This section connects the BTB's instruction class prediction.
diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
deleted file mode 100644
index cde1fa7d3..000000000
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ /dev/null
@@ -1,130 +0,0 @@
-///////////////////////////////////////////
-// locallHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local history branches
-                                         k = 10) ( // number of past branches stored
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF,  StallE,
-  input  logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]       Prediction,
-  // update
-  input logic [`XLEN-1:0]  UpdatePC,
-  input logic              UpdateEN, PCSrcE, 
-  input logic [1:0]        UpdatePrediction
-);
-
-  logic [2**m-1:0][k-1:0]  LHRNextF;
-  logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
-  logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
-  logic [1:0]              PredictionMemory;
-  logic                    DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
-  logic [1:0]              UpdatePredictionF;
-
-  assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; 
-  assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
-  assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};  
-
-  // INCASE we do ahead pipelining
-  //    ram2p1r1wb #(m,k) LHR(.clk(clk)),
-  //                 .reset(reset),
-  //                 .RA1(LookUpPCIndex), // need hashing function to get correct PC address 
-  //                 .RD1(LHRF),
-  //                 .REN1(~StallF),
-  //                 .WA1(UpdatePCIndex),
-  //                 .WD1(LHRENExt),
-  //                 .WEN1(UpdateEN),
-  //                 .BitWEN1(2'b11));  
-
-  genvar      index;
-  for (index = 0; index < 2**m; index = index +1) begin:localhist
-    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
-                                      .d(LHRFNext), .q(LHRNextF[index]));
-  end 
-
-  // need to forward when updating to the same address as reading.
-  // first we compare to see if the update and lookup addreses are the same
-  assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
-  assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex]; 
-
-  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  // LHR referes to the address that the past k branches points to in the prediction stage 
-  // LHRE refers to the address that the past k branches points to in the exectution stage
-  ram2p1r1wb #(k, 2) PHT(.clk(clk), 
-    .reset(reset),
-    .ra1(ForwardLHRNext),
-    .rd1(PredictionMemory),
-    .ren1(~StallF),
-    .wa2(LHRFNext),
-    .wd2(UpdatePrediction),
-    .wen2(UpdateEN),
-    .bwe2(2'b11));
-
-
-  
-  assign DoForwardingPHT = LHRFNext == ForwardLHRNext; 
-
-  // register the update value and the forwarding signal into the Fetch stage
-  // TODO: add stall logic ***
-  flopr #(1) DoForwardingReg(.clk(clk),
-        .reset(reset),
-        .d(DoForwardingPHT),
-        .q(DoForwardingPHTF));
-  
-  flopr #(2) UpdatePredictionReg(.clk(clk),
-     .reset(reset),
-     .d(UpdatePrediction),
-     .q(UpdatePredictionF));
-
-  assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
-  
-  //pipeline for LHR
-  flopenrc #(k) LHRFReg(.clk(clk),
-   .reset(reset),
-   .en(~StallF),
-   .clear(1'b0),
-   .d(ForwardLHRNext),
-   .q(LHRF));
-  /*
-   flopenrc #(k) LHRDReg(.clk(clk),
-   .reset(reset),
-   .en(~StallD),
-   .clear(FlushD),
-   .d(LHRF),
-   .q(LHRD));
-   
-   flopenrc #(k) LHREReg(.clk(clk),
-   .reset(reset),
-   .en(~StallE),
-   .clear(FlushE),
-   .d(LHRD),
-   .q(LHRE));
-   */
-endmodule
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
new file mode 100644
index 000000000..266219416
--- /dev/null
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -0,0 +1,115 @@
+///////////////////////////////////////////
+// localaheadbp
+//
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+//
+// Purpose: local history branch predictor with ahead pipelining and SRAM memories.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module localaheadbp import cvw::*; #(parameter cvw_t P, 
+                                     parameter XLEN,
+                      parameter m = 6, // 2^m = number of local history branches 
+                      parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredD, 
+  output logic            BPDirPredWrongE,
+  // update
+  input logic [XLEN-1:0] PCNextF, PCM,
+  input logic             BranchE, BranchM, PCSrcE
+);
+
+  logic [k-1:0]           IndexNextF, IndexM;
+  //logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             BPDirPredE;
+  logic [1:0]             BPDirPredM;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
+  logic [k-1:0]           LHRNextW;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0] LHRArray;
+  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
+  logic [XLEN-1:0]       PCW;
+  
+  
+  logic                    UpdateM;
+
+  //assign IndexNextF = LHR;
+  assign IndexM = LHRW;
+  
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
+    .ce1(~StallD), .ce2(~StallW & ~FlushW),
+    .ra1(LHRF),
+    .rd1(BPDirPredD),
+    .wa2(IndexM),
+    .wd2(NewBPDirPredW),
+    .we2(BranchM),
+    .bwe2(1'b1));
+
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
+
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
+  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
+
+  // this is local history
+  //genvar      index;
+  //assign UpdateM = BranchM & ~StallW & ~FlushW;
+  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+
+  ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRF),
+    .wa2(IndexLHRM),
+    .wd2(LHRNextW),
+    .we2(BranchM),
+    .bwe2('1));  
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  //assign LHRF = LHRNextF;
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
+
+  flopenr #(XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv
new file mode 100644
index 000000000..8037b743d
--- /dev/null
+++ b/src/ifu/bpred/localbpbasic.sv
@@ -0,0 +1,106 @@
+///////////////////////////////////////////
+// localbpbasic
+//
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+//
+// Purpose: Local history branch predictor. Basic implementation without any repair and flop memories.
+
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module localbpbasic import cvw::*; #(parameter cvw_t P,
+                                     parameter XLEN,
+                      parameter m = 6, // 2^m = number of local history branches 
+                      parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredF, 
+  output logic            BPDirPredWrongE,
+  // update
+  input logic [XLEN-1:0] PCNextF, PCM,
+  input logic             BranchE, BranchM, PCSrcE
+);
+
+  logic [k-1:0]           IndexNextF, IndexM;
+  logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHR;
+  logic [k-1:0]           LHRNextW;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0]  LHRArray;
+  logic [m-1:0]            IndexLHRNextF, IndexLHRM;
+  
+  logic                    UpdateM;
+
+  assign IndexNextF = LHR;
+  assign IndexM = LHRM;
+  
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexNextF),
+    .rd1(BPDirPredF),
+    .wa2(IndexM),
+    .wd2(NewBPDirPredM),
+    .we2(BranchM),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
+  assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
+
+  // this is local history
+  genvar      index;
+  assign UpdateM = BranchM & ~StallW & ~FlushW;
+  assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
+  for (index = 0; index < 2**m; index = index +1) begin:localhist
+    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
+                                      .d(LHRNextW), .q(LHRArray[index]));
+  end
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+  assign LHR = LHRArray[IndexLHRNextF];
+
+  // this is global history
+  //flopenr #(k) LHRReg(clk, reset, ~StallM & ~FlushM & BranchM, LHRNextW, LHR);
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHR, LHRF);
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+
+
+endmodule
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
new file mode 100644
index 000000000..3af6d7b9f
--- /dev/null
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -0,0 +1,136 @@
+///////////////////////////////////////////
+// localrepairbp
+//
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 15 April 2023
+//
+// Purpose: Local history branch predictor with speculation and repair using CBH.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module localrepairbp import cvw::*; #(parameter cvw_t P,
+                                      parameter XLEN,
+                       parameter m = 6, // 2^m = number of local history branches 
+                       parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredD, 
+  output logic            BPDirPredWrongE,
+  // update
+  input logic [XLEN-1:0] PCNextF, PCE, PCM,
+  input logic             BranchD, BranchE, BranchM, PCSrcE
+);
+
+  //logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             BPDirPredE;
+  logic [1:0]             BPDirPredM;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
+  logic [k-1:0]           LHRNextW;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0] LHRArray;
+  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
+  logic [XLEN-1:0]       PCW;
+
+  logic [k-1:0]           LHRCommittedF, LHRSpeculativeF;
+  logic [m-1:0]           IndexLHRD;
+  logic [k-1:0]           LHRNextE;
+  logic                   SpeculativeFlushedF;
+  
+  
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
+    .ce1(~StallD), .ce2(~StallW & ~FlushW),
+    .ra1(LHRF),
+    .rd1(BPDirPredD),
+    .wa2(LHRW),
+    .wd2(NewBPDirPredW),
+    .we2(BranchM),
+    .bwe2(1'b1));
+
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
+
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
+  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
+
+  // this is local history
+  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+
+  ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRCommittedF),
+    .wa2(IndexLHRM),
+    .wd2(LHRNextW),
+    .we2(BranchM),
+    .bwe2('1));
+
+  assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
+  assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE;
+  // *** replace with a small CAM
+  ram2p1r1wbe #(P, 2**m, k) SHB(.clk(clk),
+    .ce1(~StallF), .ce2(~StallE & ~FlushE),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRSpeculativeF),
+    .wa2(IndexLHRD),
+    .wd2(LHRNextE),
+    .we2(BranchD),
+    .bwe2('1));
+  // **** replace with small CAM
+  logic [2**m-1:0]        FlushedBits;
+  always_ff @(posedge clk) begin // Valid bit array,
+    SpeculativeFlushedF <= #1 FlushedBits[IndexLHRNextF];
+    if (reset | FlushD) FlushedBits        <= #1 '1;
+    if(BranchD & ~StallE & ~FlushE) begin
+      FlushedBits[IndexLHRD] <= #1 '0;
+    end
+  end
+
+  //assign SpeculativeFlushedF = '1;
+  mux2 #(k) LHRMux(LHRSpeculativeF, LHRCommittedF, SpeculativeFlushedF, LHRF);
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  //assign LHRF = LHRNextF;
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
+
+  flopenr #(XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv
index 514a29564..470375adc 100644
--- a/src/ifu/bpred/satCounter2.sv
+++ b/src/ifu/bpred/satCounter2.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module satCounter2
   (input logic        BrDir,
    input logic [1:0]  OldState,
diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv
index 7011a0580..52e24d901 100644
--- a/src/ifu/bpred/twoBitPredictor.sv
+++ b/src/ifu/bpred/twoBitPredictor.sv
@@ -26,14 +26,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module twoBitPredictor #(parameter k = 10) (
+module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
+                         parameter k = 10) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
-  input  logic [`XLEN-1:0] PCNextF, PCM,
+  input  logic [XLEN-1:0]  PCNextF, PCM,
   output logic [1:0]       BPDirPredF,
   output logic             BPDirPredWrongE,
   input  logic             BranchE, BranchM,
@@ -54,7 +53,7 @@ module twoBitPredictor #(parameter k = 10) (
   assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};  
 
 
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(BPDirPredF),
diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index bc9ae0abe..1605ed039 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -29,9 +29,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
-module decompress (
+module decompress #(parameter XLEN)(
   input  logic [31:0] InstrRawD,         // 32-bit instruction or raw compressed 16-bit instruction in bottom half
   output logic [31:0] InstrD,            // Decompressed instruction
   output logic        IllegalCompInstrD  // Invalid decompressed instruction
@@ -91,18 +90,18 @@ module decompress (
                   end
         5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
         5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
-        5'b00011: if (`XLEN==32)
+        5'b00011: if (XLEN==32)
                     InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
                   else
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
         5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
         5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
-        5'b00111: if (`XLEN==32)
+        5'b00111: if (XLEN==32)
                     InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
                   else
                     InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
         5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
-        5'b01001: if (`XLEN==32) 
+        5'b01001: if (XLEN==32) 
                     InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
                   else
                     InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
@@ -126,7 +125,7 @@ module decompress (
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
                     else // if (instr16[6:5] == 2'b11) 
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
-                  else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] 
+                  else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] 
                     if (instr16[6:5] == 2'b00)
                       InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
                     else if (instr16[6:5] == 2'b01)
@@ -151,7 +150,7 @@ module decompress (
         5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
         5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
         5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
-        5'b10011: if (`XLEN == 32)
+        5'b10011: if (XLEN == 32)
                     InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
                   else 
                     InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
@@ -170,7 +169,7 @@ module decompress (
                       InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
         5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
         5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
-        5'b10111: if (`XLEN==32)
+        5'b10111: if (XLEN==32)
                     InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
                   else
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
@@ -181,4 +180,3 @@ module decompress (
       endcase
     end
 endmodule
-    
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 82e8a33b9..de0200058 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -25,119 +25,116 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module ifu (
-  input  logic                clk, reset,
-  input  logic                StallF, StallD, StallE, StallM, StallW,
-  input  logic                FlushD, FlushE, FlushM, FlushW, 
-  output logic                IFUStallF,                                // IFU stalsl pipeline during a multicycle operation
+module ifu import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk, reset,
+  input  logic                 StallF, StallD, StallE, StallM, StallW,
+  input  logic                 FlushD, FlushE, FlushM, FlushW, 
+  output logic                 IFUStallF,                                // IFU stalsl pipeline during a multicycle operation
   // Command from CPU
-  input  logic                InvalidateICacheM,                        // Clears all instruction cache valid bits
-  input  logic                CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
-  input  logic                InstrValidD, InstrValidE, InstrValidM,
-  input  logic                BranchD, BranchE,
-  input  logic                JumpD, JumpE,
+  input  logic                 InvalidateICacheM,                        // Clears all instruction cache valid bits
+  input  logic                 CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
+  input  logic                 InstrValidD, InstrValidE, InstrValidM,
+  input  logic                 BranchD, BranchE,
+  input  logic                 JumpD, JumpE,
   // Bus interface
-  output logic [`PA_BITS-1:0] IFUHADDR,                                 // Bus address from IFU to EBU
-  input  logic [`XLEN-1:0]    HRDATA,                                   // Bus read data from IFU to EBU
-  input  logic                IFUHREADY,                                // Bus ready from IFU to EBU
-  output logic                IFUHWRITE,                                // Bus write operation from IFU to EBU
-  output logic [2:0]          IFUHSIZE,                                 // Bus operation size from IFU to EBU
-  output logic [2:0]          IFUHBURST,                                // Bus burst from IFU to EBU
-  output logic [1:0]          IFUHTRANS,                                // Bus transaction type from IFU to EBU
+  output logic [P.PA_BITS-1:0] IFUHADDR,                                 // Bus address from IFU to EBU
+  input  logic [P.XLEN-1:0]    HRDATA,                                   // Bus read data from IFU to EBU
+  input  logic                 IFUHREADY,                                // Bus ready from IFU to EBU
+  output logic                 IFUHWRITE,                                // Bus write operation from IFU to EBU
+  output logic [2:0]           IFUHSIZE,                                 // Bus operation size from IFU to EBU
+  output logic [2:0]           IFUHBURST,                                // Bus burst from IFU to EBU
+  output logic [1:0]           IFUHTRANS,                                // Bus transaction type from IFU to EBU
 
-  output logic [`XLEN-1:0]    PCSpillF,                                 // PCF with possible + 2 to handle spill to HPTW
+  output logic [P.XLEN-1:0]    PCSpillF,                                 // PCF with possible + 2 to handle spill to HPTW
   // Execute
-  output logic [`XLEN-1:0]    PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
-  input  logic                PCSrcE,                                   // Executation stage branch is taken
-  input  logic [`XLEN-1:0]    IEUAdrE,                                  // The branch/jump target address
-  input  logic [`XLEN-1:0]    IEUAdrM,                                  // The branch/jump target address
-  output logic [`XLEN-1:0]    PCE,                                      // Execution stage instruction address
-  output logic                BPWrongE,                                 // Prediction is wrong
-  output logic                BPWrongM,                                 // Prediction is wrong
+  output logic [P.XLEN-1:0]    PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
+  input  logic                 PCSrcE,                                   // Executation stage branch is taken
+  input  logic [P.XLEN-1:0]    IEUAdrE,                                  // The branch/jump target address
+  input  logic [P.XLEN-1:0]    IEUAdrM,                                  // The branch/jump target address
+  output logic [P.XLEN-1:0]    PCE,                                      // Execution stage instruction address
+  output logic                 BPWrongE,                                 // Prediction is wrong
+  output logic                 BPWrongM,                                 // Prediction is wrong
   // Mem
-  output logic                CommittedF,                               // I$ or bus memory operation started, delay interrupts
-  input  logic [`XLEN-1:0]    UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
-  output logic [`XLEN-1:0]    PC2NextF,                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
-  output logic [31:0]         InstrD,                                   // The decoded instruction in Decode stage
-  output logic [31:0]         InstrM,                                   // The decoded instruction in Memory stage
-  output logic [31:0]         InstrOrigM,                               // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  output logic [`XLEN-1:0]    PCM,                                      // Memory stage instruction address
+  output logic                 CommittedF,                               // I$ or bus memory operation started, delay interrupts
+  input  logic [P.XLEN-1:0]    UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
+  output logic [P.XLEN-1:0]    PC2NextF,                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
+  output logic [31:0]          InstrD,                                   // The decoded instruction in Decode stage
+  output logic [31:0]          InstrM,                                   // The decoded instruction in Memory stage
+  output logic [31:0]          InstrOrigM,                               // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
+  output logic [P.XLEN-1:0]    PCM,                                      // Memory stage instruction address
   // branch predictor
-  output logic [3:0]          InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-  output logic                BPDirPredWrongM,                          // Prediction direction is wrong
-  output logic                BTAWrongM,                                // Prediction target wrong
-  output logic                RASPredPCWrongM,                          // RAS prediction is wrong
-  output logic                IClassWrongM,                             // Class prediction is wrong
-  output logic                ICacheStallF,                             // I$ busy with multicycle operation
+  output logic [3:0]           InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic                 BPDirPredWrongM,                          // Prediction direction is wrong
+  output logic                 BTAWrongM,                                // Prediction target wrong
+  output logic                 RASPredPCWrongM,                          // RAS prediction is wrong
+  output logic                 IClassWrongM,                             // Class prediction is wrong
+  output logic                 ICacheStallF,                             // I$ busy with multicycle operation
   // Faults
-  input logic                 IllegalBaseInstrD,                        // Illegal non-compressed instruction
-  input logic                 IllegalFPUInstrD,                         // Illegal FP instruction
-  output logic                InstrPageFaultF,                          // Instruction page fault 
-  output logic                IllegalIEUFPUInstrD,                      // Illegal instruction including compressed & FP
-  output logic                InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
+  input logic                  IllegalBaseInstrD,                        // Illegal non-compressed instruction
+  input logic                  IllegalFPUInstrD,                         // Illegal FP instruction
+  output logic                 InstrPageFaultF,                          // Instruction page fault 
+  output logic                 IllegalIEUFPUInstrD,                      // Illegal instruction including compressed & FP
+  output logic                 InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   // mmu management
-  input logic [1:0]           PrivilegeModeW,                           // Priviledge mode in Writeback stage
-  input logic [`XLEN-1:0]     PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
-  input logic [1:0]           PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
-  input logic                 ITLBWriteF,                               // Writes PTE and PageType to ITLB
-  input logic [`XLEN-1:0]     SATP_REGW,                                // Location of the root page table and page table configuration
-  input logic                 STATUS_MXR,                               // Status CSR: make executable page readable 
-  input logic                 STATUS_SUM,                               // Status CSR: Supervisor access to user memory
-  input logic                 STATUS_MPRV,                              // Status CSR: modify machine privilege
-  input logic [1:0]           STATUS_MPP,                               // Status CSR: previous machine privilege level
-  input logic                 sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
-  output logic                ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
-  output logic                InstrUpdateDAF,                           // ITLB hit needs to update dirty or access bits
-  input  var logic [7:0]      PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],      // PMP configuration from privileged unit
-  input  var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit
-  output logic                InstrAccessFaultF,                        // Instruction access fault 
-  output logic                ICacheAccess,                             // Report I$ read to performance counters
-  output logic                ICacheMiss                                // Report I$ miss to performance counters
+  input logic [1:0]            PrivilegeModeW,                           // Priviledge mode in Writeback stage
+  input logic [P.XLEN-1:0]     PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
+  input logic [1:0]            PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
+  input logic                  ITLBWriteF,                               // Writes PTE and PageType to ITLB
+  input logic [P.XLEN-1:0]     SATP_REGW,                                // Location of the root page table and page table configuration
+  input logic                  STATUS_MXR,                               // Status CSR: make executable page readable 
+  input logic                  STATUS_SUM,                               // Status CSR: Supervisor access to user memory
+  input logic                  STATUS_MPRV,                              // Status CSR: modify machine privilege
+  input logic [1:0]            STATUS_MPP,                               // Status CSR: previous machine privilege level
+  input logic                  sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
+  output logic                 ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
+  output logic                 InstrUpdateDAF,                           // ITLB hit needs to update dirty or access bits
+  input  var logic [7:0]       PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
+  input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
+  output logic                 InstrAccessFaultF,                        // Instruction access fault 
+  output logic                 ICacheAccess,                             // Report I$ read to performance counters
+  output logic                 ICacheMiss                                // Report I$ miss to performance counters
 );
 
-  localparam [31:0]           nop = 32'h00000013;                    // instruction for NOP
+  localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
 
-  logic [`XLEN-1:0]           PCNextF;                               // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
-  logic                       BranchMisalignedFaultE;                // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
-  logic [`XLEN-1:0]           PCPlus2or4F;                           // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
-  logic [`XLEN-1:0]           PCSpillNextF;                          // Next PCF after possible + 2 to handle spill
-  logic [`XLEN-1:0]           PCLinkD;                               // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
-  logic [`XLEN-1:2]           PCPlus4F;                              // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
-  logic [`XLEN-1:0]           PCD;                                   // Decode stage instruction address
-  logic [`XLEN-1:0]           NextValidPCE;                          // The PC of the next valid instruction in the pipeline after  csr write or fence
-  logic [`XLEN-1:0]           PCF;                                   // Fetch stage instruction address
-  logic [`PA_BITS-1:0]        PCPF;                                  // Physical address after address translation
-  logic [`XLEN+1:0]           PCFExt;                                //
+  logic [P.XLEN-1:0]           PCNextF;                                  // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
+  logic                        BranchMisalignedFaultE;                   // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
+  logic [P.XLEN-1:0]           PCPlus2or4F;                              // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
+  logic [P.XLEN-1:0]           PCSpillNextF;                             // Next PCF after possible + 2 to handle spill
+  logic [P.XLEN-1:0]           PCLinkD;                                  // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
+  logic [P.XLEN-1:2]           PCPlus4F;                                 // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
+  logic [P.XLEN-1:0]           PCD;                                      // Decode stage instruction address
+  logic [P.XLEN-1:0]           NextValidPCE;                             // The PC of the next valid instruction in the pipeline after  csr write or fence
+  logic [P.XLEN-1:0]           PCF;                                      // Fetch stage instruction address
+  logic [P.PA_BITS-1:0]        PCPF;                                     // Physical address after address translation
+  logic [P.XLEN+1:0]           PCFExt;                                
 
-  logic [31:0]                IROMInstrF;                            // Instruction from the IROM
-  logic [31:0]                ICacheInstrF;                          // Instruction from the I$
-  logic [31:0]                InstrRawF;                             // Instruction from the IROM, I$, or bus
-  logic                       CompressedF;                           // The fetched instruction is compressed
-  logic                       CompressedD;                           // The decoded instruction is compressed
-  logic                       CompressedE;                           // The execution instruction is compressed
-  logic                       CompressedM;                           // The execution instruction is compressed
-  logic [31:0]                PostSpillInstrRawF;                    // Fetch instruction after merge two halves of spill
-  logic [31:0]                InstrRawD;                             // Non-decompressed instruction in the Decode stage
-  logic                       IllegalIEUInstrD;                      // IEU Instruction (regular or compressed) is not good
+  logic [31:0]                 IROMInstrF;                               // Instruction from the IROM
+  logic [31:0]                 ICacheInstrF;                             // Instruction from the I$
+  logic [31:0]                 InstrRawF;                                // Instruction from the IROM, I$, or bus
+  logic                        CompressedF;                              // The fetched instruction is compressed
+  logic                        CompressedD;                              // The decoded instruction is compressed
+  logic                        CompressedE;                              // The execution instruction is compressed
+  logic                        CompressedM;                              // The execution instruction is compressed
+  logic [31:0]                 PostSpillInstrRawF;                       // Fetch instruction after merge two halves of spill
+  logic [31:0]                 InstrRawD;                                // Non-decompressed instruction in the Decode stage
+  logic                        IllegalIEUInstrD;                         // IEU Instruction (regular or compressed) is not good
   
-  logic [1:0]                 IFURWF;                                // IFU alreays read IFURWF = 10
-  logic [31:0]                InstrE;                                // Instruction in the Execution stage
-  logic [31:0]                NextInstrD, NextInstrE;                // Instruction into the next stage after possible stage flush
+  logic [1:0]                  IFURWF;                                   // IFU alreays read IFURWF = 10
+  logic [31:0]                 InstrE;                                   // Instruction in the Execution stage
+  logic [31:0]                 NextInstrD, NextInstrE;                   // Instruction into the next stage after possible stage flush
 
-
-  logic                       CacheableF;                            // PMA indicates instruction address is cacheable
-  logic                       SelSpillNextF;                         // In a spill, stall pipeline and gate local stallF
-  logic                       BusStall;                              // Bus interface busy with multicycle operation
-  logic                       IFUCacheBusStallF;                     // EIther I$ or bus busy with multicycle operation
-  logic                       GatedStallD;                           // StallD gated by selected next spill
+  logic                        CacheableF;                               // PMA indicates instruction address is cacheable
+  logic                        SelSpillNextF;                            // In a spill, stall pipeline and gate local stallF
+  logic                        BusStall;                                 // Bus interface busy with multicycle operation
+  logic                        IFUCacheBusStallF;                        // EIther I$ or bus busy with multicycle operation
+  logic                        GatedStallD;                              // StallD gated by selected next spill
   // branch predictor signal
-  logic [`XLEN-1:0]           PC1NextF;                              // Branch predictor next PCF
-  logic                       BusCommittedF;                         // Bus memory operation in flight, delay interrupts
-  logic                       CacheCommittedF;                       // I$ memory operation started, delay interrupts
-  logic                       SelIROM;                               // PMA indicates instruction address is in the IROM
-  logic [15:0]                InstrRawE, InstrRawM;
+  logic [P.XLEN-1:0]           PC1NextF;                                 // Branch predictor next PCF
+  logic                        BusCommittedF;                            // Bus memory operation in flight, delay interrupts
+  logic                        CacheCommittedF;                          // I$ memory operation started, delay interrupts
+  logic                        SelIROM;                                  // PMA indicates instruction address is in the IROM
+  logic [15:0]                 InstrRawE, InstrRawM;
   
   assign PCFExt = {2'b00, PCSpillF};
 
@@ -145,8 +142,8 @@ module ifu (
   // Spill Support
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`C_SUPPORTED) begin : Spill
-    spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
+  if(P.C_SUPPORTED) begin : Spill
+    spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
       .InstrUpdateDAF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
     assign PCSpillNextF = PCNextF;
@@ -159,7 +156,7 @@ module ifu (
   // Memory management
   ////////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`ZICSR_SUPPORTED == 1) begin : immu
+  if(P.ZICSR_SUPPORTED == 1) begin : immu
     ///////////////////////////////////////////
     // sfence.vma causes TLB flushes
     ///////////////////////////////////////////
@@ -172,7 +169,7 @@ module ifu (
     flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
     assign TLBFlush = sfencevmaM & ~StallMQ;
 
-    mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
+    mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1))
     immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
          .PrivilegeModeW, .DisableTranslation(1'b0),
          .VAdr(PCFExt),
@@ -193,7 +190,7 @@ module ifu (
 
   end else begin
     assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = '0;
-    assign PCPF = PCFExt[`PA_BITS-1:0];
+    assign PCPF = PCFExt[P.PA_BITS-1:0];
     assign CacheableF = '1;
     assign SelIROM = '0;
   end
@@ -201,6 +198,7 @@ module ifu (
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Memory 
   ////////////////////////////////////////////////////////////////////////////////////////////////
+  
   // CommittedM tells the CPU's privileged unit the current instruction
   // in the memory stage is a memory operaton and that memory operation is either completed
   // or is partially executed. Partially completed memory operations need to prevent an interrupts.
@@ -208,35 +206,35 @@ module ifu (
   // delay the interrupt until the LSU is in a clean state.
   assign CommittedF = CacheCommittedF | BusCommittedF;
 
-  logic          IgnoreRequest;
+  logic  IgnoreRequest;
   assign IgnoreRequest = ITLBMissF | FlushD;
 
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
-  if (`IROM_SUPPORTED) begin : irom
+  if (P.IROM_SUPPORTED) begin : irom
   logic IROMce;
   assign IROMce = ~GatedStallD | reset;
     assign IFURWF = 2'b10;
-    irom irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[`XLEN-1:0]), .IROMInstrF);
+    irom #(P) irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF);
   end else begin
     assign IFURWF = 2'b10;
   end
-  if (`BUS_SUPPORTED) begin : bus
+  if (P.BUS_SUPPORTED) begin : bus
     // **** must fix words per line vs beats per line as in lsu.
-    localparam   WORDSPERLINE = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS/`XLEN : 1;
-    localparam   LOGBWPL = `ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
-    if(`ICACHE_SUPPORTED) begin : icache
-      localparam           LINELEN = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS : `XLEN;
-      localparam           LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
-      logic [LINELEN-1:0]  FetchBuffer;
-      logic [`PA_BITS-1:0] ICacheBusAdr;
-      logic                ICacheBusAck;
-      logic [1:0]          CacheBusRW, BusRW, CacheRWF;
+    localparam   WORDSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.XLEN : 1;
+    localparam   LOGBWPL = P.ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
+    if(P.ICACHE_SUPPORTED) begin : icache
+      localparam            LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
+      localparam            LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+      logic [LINELEN-1:0]   FetchBuffer;
+      logic [P.PA_BITS-1:0] ICacheBusAdr;
+      logic                 ICacheBusAck;
+      logic [1:0]           CacheBusRW, BusRW, CacheRWF;
       
       assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
       assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
-      cache #(.LINELEN(`ICACHE_LINELENINBITS),
-              .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
-              .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
+              .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
+              .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
       icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
              .FetchBuffer, .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
@@ -251,13 +249,13 @@ module ifu (
              .NextSet(PCSpillNextF[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
-      ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
+      ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
       ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
             .HRDATA,
             .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
             .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
             .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
-             .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
+            .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
             .FetchBuffer, .PAdr(PCPF),
             .BusRW, .Stall(GatedStallD),
             .BusStall, .BusCommitted(BusCommittedF));
@@ -271,13 +269,13 @@ module ifu (
       assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
       assign IFUHSIZE = 3'b010;
 
-      ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
+      ahbinterface #(P.XLEN, 0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
         .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
         .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
         .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
 
       assign CacheCommittedF = '0;
-      if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
+      if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
       else assign InstrRawF = FetchBuffer;
       assign IFUHBURST = 3'b0;
       assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
@@ -298,17 +296,17 @@ module ifu (
   // PCNextF logic
   ////////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`ZICSR_SUPPORTED | `ZIFENCEI_SUPPORTED)
-    mux2 #(`XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
+  if(P.ZICSR_SUPPORTED | P.ZIFENCEI_SUPPORTED)
+    mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
   else assign PC2NextF = PC1NextF;
 
-  assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
-  flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
+  assign  PCNextF = {UnalignedPCNextF[P.XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
+  flopenl #(P.XLEN) pcreg(clk, reset, ~StallF, PCNextF, P.RESET_VECTOR[P.XLEN-1:0], PCF);
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   // *** consider using PCPlus2or4F = PCF + CompressedF ? 2 : 4;
-  assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC
+  assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
   // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
   // Speeds up critical path as compared to selecting adder input based on CompressedF
   // *** consider gating PCPlus4F to provide the reset.
@@ -320,15 +318,14 @@ module ifu (
     if(reset) PCPlus2or4F = '0;
     else if (CompressedF) // add 2
       if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
-      else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
+      else        PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
     else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
 
-
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Branch and Jump Predictor
   ////////////////////////////////////////////////////////////////////////////////////////////////
-  if (`BPRED_SUPPORTED) begin : bpred
-    bpred bpred(.clk, .reset,
+  if (P.BPRED_SUPPORTED) begin : bpred
+    bpred #(P) bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
                 .BranchD, .BranchE, .JumpD, .JumpE,
@@ -337,23 +334,23 @@ module ifu (
                 .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
 
   end else begin : bpred
-    mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
+    mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
     assign BPWrongE = PCSrcE;
     assign {InstrClassM, BPDirPredWrongM, BTAWrongM, RASPredPCWrongM, IClassWrongM} = '0;
     assign NextValidPCE = PCE;
   end      
 
-
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Decode stage pipeline register and compressed instruction decoding.
   ////////////////////////////////////////////////////////////////////////////////////////////////
+  
   // Decode stage pipeline register and logic
-  flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
+  flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (`C_SUPPORTED) begin
+  if (P.C_SUPPORTED) begin
     logic IllegalCompInstrD;
-    decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
+    decompress #(P.XLEN) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   end else begin  
     assign InstrD = InstrRawD;
@@ -371,19 +368,19 @@ module ifu (
   // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
-  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
+  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.C_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC/PCLink pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
-  mux2    #(32)    FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
-  mux2    #(32)    FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
-  flopenr #(32)    InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
-  flopenr #(32)    InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
-  flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
-  flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  //flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
-  //flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+  mux2    #(32)     FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
+  mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
+  flopenr #(32)     InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
+  flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
+  flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
+  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
+  //flopenr #(P.XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
+  //flopenr #(P.XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
 
   flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
   flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv
index 88eb8f1ee..1339c26fa 100644
--- a/src/ifu/irom.sv
+++ b/src/ifu/irom.sv
@@ -24,28 +24,25 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module irom(
-  input logic             clk, 
-  input logic             ce,        // Chip Enable.  0: Holds IROMInstrF constant
-  input logic [`XLEN-1:0] Adr,       // PCNextFSpill
-  output logic [31:0]     IROMInstrF // Instruction read data
+module irom import cvw::*;  #(parameter cvw_t P) (
+  input logic              clk, 
+  input logic              ce,        // Chip Enable.  0: Holds IROMInstrF constant
+  input logic [P.XLEN-1:0] Adr,       // PCNextFSpill
+  output logic [31:0]      IROMInstrF // Instruction read data
 );
 
-  localparam XLENBYTES = `XLEN/8;
-  localparam ADDR_WDITH = $clog2(`IROM_RANGE/XLENBYTES); 
+  localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width
+  localparam ADDR_WDITH = $clog2(P.IROM_RANGE[P.PA_BITS-1:0]/XLENBYTES); 
   localparam OFFSET = $clog2(XLENBYTES);
 
-  logic [`XLEN-1:0] IROMInstrFFull;
-  logic [31:0]     RawIROMInstrF;
-
-  logic [1:0]       AdrD;
+  logic [P.XLEN-1:0] IROMInstrFFull;
+  logic [31:0]       RawIROMInstrF;
+  logic [1:0]        AdrD;
   flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
 
-  rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
-  if (`XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
-  else             begin
+  rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
+  if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
+  else              begin
   // IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two
   // haves.  Adr is the Next PCF not PCF so we delay 1 cycle.
     assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
@@ -54,4 +51,3 @@ module irom(
   // The spill logic will handle merging the two together.
   assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
 endmodule  
-  
diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index 54c0f2261..bb018406a 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -29,56 +29,52 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module spill #(
-  parameter CACHE_ENABLED                     // Changes spill threshold to 1 if there is no cache
-)(input logic              clk,               
-  input logic              reset,
-  input logic              StallD, FlushD,
-  input logic [`XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
-  input logic [`XLEN-1:2]  PCPlus4F,          // PCF + 4
-  input logic [`XLEN-1:0]  PCNextF,           // The next PCF
-  input logic [31:0]       InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
-  input logic              IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic              ITLBMissF,         // ITLB miss, ignore memory request
-  input logic              InstrUpdateDAF,    // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
-  output logic [`XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
-  output logic [`XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
-  output logic             SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic [31:0]      PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
-  output logic             CompressedF);      // The fetched instruction is compressed
+module spill import cvw::*;  #(parameter cvw_t P) (
+  input logic               clk,               
+  input logic               reset,
+  input logic               StallD, FlushD,
+  input logic [P.XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
+  input logic [P.XLEN-1:2]  PCPlus4F,          // PCF + 4
+  input logic [P.XLEN-1:0]  PCNextF,           // The next PCF
+  input logic [31:0]        InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
+  input logic               IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
+  input logic               ITLBMissF,         // ITLB miss, ignore memory request
+  input logic               InstrUpdateDAF,    // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
+  output logic [P.XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
+  output logic [P.XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
+  output logic              SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
+  output logic [31:0]       PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
+  output logic              CompressedF);      // The fetched instruction is compressed
 
   // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
-  typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
-  localparam           SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; 
+  typedef enum logic [1:0]  {STATE_READY, STATE_SPILL} statetype;
+  localparam                SPILLTHRESHOLD = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/32 : 1; 
 
-  statetype         CurrState, NextState;
-  logic [`XLEN-1:0] PCPlus2F;         
-  logic             TakeSpillF;
-  logic             SpillF;
-  logic             SelSpillF;
-  logic             SpillSaveF;
-  logic [15:0]      InstrFirstHalfF;
+  statetype          CurrState, NextState;
+  logic [P.XLEN-1:0] PCPlus2F;         
+  logic              TakeSpillF;
+  logic              SpillF;
+  logic              SelSpillF;
+  logic              SpillSaveF;
+  logic [15:0]       InstrFirstHalfF;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // PC logic 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   
   // compute PCF+2 from the raw PC+4
-  mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
+  mux2 #(P.XLEN) pcplus2mux(.d0({PCF[P.XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
   // select between PCNextF and PCF+2
-  mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelSpillNextF & ~FlushD), .y(PCSpillNextF));
+  mux2 #(P.XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelSpillNextF & ~FlushD), .y(PCSpillNextF));
   // select between PCF and PCF+2
-  mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
+  mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
 
-  
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Detect spill
   ////////////////////////////////////////////////////////////////////////////////////////////////////
 
   assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
-  assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF));
+  assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
   
   always_ff @(posedge clk)
     if (reset | FlushD)    CurrState <= #1 STATE_READY;
diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv
index eda3576be..c8b7ccee3 100644
--- a/src/lsu/amoalu.sv
+++ b/src/lsu/amoalu.sv
@@ -27,17 +27,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module amoalu (
-  input  logic [`XLEN-1:0] ReadDataM,    // LSU's ReadData
-  input  logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
-  input  logic [6:0]       LSUFunct7M,   // ALU Operation
-  input  logic [2:0]       LSUFunct3M,   // Memoy access width
-  output logic [`XLEN-1:0] AMOResult     // ALU output
+module amoalu import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.XLEN-1:0] ReadDataM,    // LSU's ReadData
+  input  logic [P.XLEN-1:0] IHWriteDataM, // LSU's WriteData
+  input  logic [6:0]        LSUFunct7M,   // ALU Operation
+  input  logic [2:0]        LSUFunct3M,   // Memoy access width
+  output logic [P.XLEN-1:0] AMOResultM    // ALU output
 );
 
-  logic [`XLEN-1:0] a, b, y;
+  logic [P.XLEN-1:0] a, b, y;
 
   // *** see how synthesis generates this and optimize more structurally if necessary to share hardware
   // a single carry chain should be shared for + and the four min/max
@@ -53,25 +51,24 @@ module amoalu (
       5'b10100: y = ($signed(a) >= $signed(b)) ? a : b;     // amomax
       5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b;  // amominu
       5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
-      default:  y = `XLEN'bx;                               // undefined; *** could change to b for efficiency
+      default:  y = 'x;                                     // undefined; *** could change to b for efficiency
     endcase
 
   // sign extend if necessary
-  if (`XLEN == 32) begin:sext
+  if (P.XLEN == 32) begin:sext
     assign a = ReadDataM;
     assign b = IHWriteDataM;
-    assign AMOResult = y;
-  end else begin:sext // `XLEN = 64
+    assign AMOResultM = y;
+  end else begin:sext // P.XLEN = 64
     always_comb 
       if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
         a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
         b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
-        AMOResult = {{32{y[31]}}, y[31:0]};
+        AMOResultM = {{32{y[31]}}, y[31:0]};
       end else begin
         a = ReadDataM;
         b = IHWriteDataM;
-        AMOResult = y;
+        AMOResultM = y;
       end
   end
 endmodule
-
diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
index fc9ede119..117a42c2b 100644
--- a/src/lsu/atomic.sv
+++ b/src/lsu/atomic.sv
@@ -27,33 +27,31 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module atomic (
-  input logic                clk,
-  input logic                reset, 
-  input logic                StallW,
-  input logic [`XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [`XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [`PA_BITS-1:0] PAdrM,          // Physical memory address
-  input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
-  input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
-  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
-  input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
-  input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
-  output logic [`XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
-  output logic               SquashSCW,      // Store conditional failed disable write to GPR
-  output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
+module atomic import cvw::*;  #(parameter cvw_t P) (
+  input logic                 clk,
+  input logic                 reset, 
+  input logic                 StallW,
+  input logic [P.XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [P.XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [P.PA_BITS-1:0] PAdrM,          // Physical memory address
+  input logic [6:0]           LSUFunct7M,     // AMO alu operation gated by HPTW
+  input logic [2:0]           LSUFunct3M,     // IEU or HPTW memory operation size
+  input logic [1:0]           LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
+  input logic [1:0]           PreLSURWM,      // IEU or HPTW Read/Write signal
+  input logic                 IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
+  output logic [P.XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
+  output logic                SquashSCW,      // Store conditional failed disable write to GPR
+  output logic [1:0]          LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
 );
 
-  logic [`XLEN-1:0]          AMOResult;
-  logic                      MemReadM;
+  logic [P.XLEN-1:0]          AMOResultM;
+  logic                       MemReadM;
 
-  amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult);
+  amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
 
-  mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
+  mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
 
-  lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+  lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
 
 endmodule  
diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv
index 0107236d1..c8668e767 100644
--- a/src/lsu/dtim.sv
+++ b/src/lsu/dtim.sv
@@ -27,31 +27,28 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module dtim(
-  input logic                clk, 
-  input logic                FlushW,        
-  input logic                ce,            // Chip Enable.  0: Holds ReadDataWordM
-  input logic [1:0]          MemRWM,        // Read/Write control
-  input logic [`PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
-  input logic [`LLEN-1:0]    WriteDataM,    // Write data from IEU
-  input logic [`LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
-  output logic [`LLEN-1:0]   ReadDataWordM  // Read data before subword selection
+module dtim import cvw::*;  #(parameter cvw_t P) (
+  input logic                 clk, 
+  input logic                 FlushW,        
+  input logic                 ce,            // Chip Enable.  0: Holds ReadDataWordM
+  input logic [1:0]           MemRWM,        // Read/Write control
+  input logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
+  input logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
+  input logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
+  output logic [P.LLEN-1:0]   ReadDataWordM  // Read data before subword selection
   );
 
-  logic                      we;
+  logic                       we;
  
-  localparam LLENBYTES  = `LLEN/8;
+  localparam LLENBYTES  = P.LLEN/8;
   // verilator  lint_off WIDTH 
-  localparam DEPTH      = `DTIM_RANGE/LLENBYTES;
+  localparam DEPTH      = P.DTIM_RANGE/LLENBYTES;
   // verilator  lint_on WIDTH 
   localparam ADDR_WDITH = $clog2(DEPTH);
   localparam OFFSET     = $clog2(LLENBYTES);
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN)) 
+  ram1p1rwbe #(.P(P), .DEPTH(DEPTH), .WIDTH(P.LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
-  
diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv
index 97846d97e..551f08de4 100644
--- a/src/lsu/endianswap.sv
+++ b/src/lsu/endianswap.sv
@@ -27,9 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module endianswap #(parameter LEN=`XLEN) (
+module endianswap #(parameter LEN) (
   input  logic            BigEndianM,
   input  logic [LEN-1:0]  a,
   output logic [LEN-1:0]  y
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
index 5b4b37665..cc6c94ba8 100644
--- a/src/lsu/lrsc.sv
+++ b/src/lsu/lrsc.sv
@@ -28,30 +28,28 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module lrsc(
-  input  logic                clk, 
-  input  logic                reset,
-  input  logic                StallW,
-  input  logic                MemReadM,   // Memory read
-  input  logic [1:0]          PreLSURWM,  // Memory operation from the HPTW or IEU [1]: read, [0]: write
-  output logic [1:0]          LSURWM,     // Memory operation after potential squash of SC
-  input  logic [1:0]          LSUAtomicM, // Atomic memory operaiton
-  input  logic [`PA_BITS-1:0] PAdrM,      // Physical memory address 
-  output logic                SquashSCW   // Squash the store conditional by not allowing rf write
+module lrsc import cvw::*;  #(parameter cvw_t P) (
+  input  logic                 clk, 
+  input  logic                 reset,
+  input  logic                 StallW,
+  input  logic                 MemReadM,   // Memory read
+  input  logic [1:0]           PreLSURWM,  // Memory operation from the HPTW or IEU [1]: read, [0]: write
+  output logic [1:0]           LSURWM,     // Memory operation after potential squash of SC
+  input  logic [1:0]           LSUAtomicM, // Atomic memory operaiton
+  input  logic [P.PA_BITS-1:0] PAdrM,      // Physical memory address 
+  output logic                 SquashSCW   // Squash the store conditional by not allowing rf write
 );
 
   // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
-  logic [`PA_BITS-1:2]        ReservationPAdrW;
-  logic                       ReservationValidM, ReservationValidW; 
-  logic                       lrM, scM, WriteAdrMatchM;
-  logic                       SquashSCM;
+  logic [P.PA_BITS-1:2]        ReservationPAdrW;
+  logic                        ReservationValidM, ReservationValidW; 
+  logic                        lrM, scM, WriteAdrMatchM;
+  logic                        SquashSCM;
 
   assign lrM = MemReadM & LSUAtomicM[0];
   assign scM = PreLSURWM[0] & LSUAtomicM[0]; 
-  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
+  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
   assign SquashSCM = scM & ~WriteAdrMatchM;
   assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
   always_comb begin // ReservationValidM (next value of valid reservation)
@@ -61,7 +59,7 @@ module lrsc(
     else ReservationValidM = ReservationValidW; // otherwise don't change valid
   end
   
-  flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
+  flopenr #(P.PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
   flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
   flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
 endmodule
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 51efeccb2..9fda87cd0 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -29,118 +29,117 @@
 // and limitations under the License.
 /////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module lsu (
-  input  logic                clk, reset,
-  input  logic                StallM, FlushM, StallW, FlushW,
-  output logic                LSUStallM,                            // LSU stalls pipeline during a multicycle operation
+module lsu import cvw::*;  #(parameter cvw_t P) (
+  input  logic                    clk, reset,
+  input  logic                    StallM, FlushM, StallW, FlushW,
+  output logic                    LSUStallM,                            // LSU stalls pipeline during a multicycle operation
   // connected to cpu (controls)
-  input  logic [1:0]          MemRWM,                               // Read/Write control
-  input  logic [2:0]          Funct3M,                              // Size of memory operation
-  input  logic [6:0]          Funct7M,                              // Atomic memory operation function
-  input  logic [1:0]          AtomicM,                              // Atomic memory operation
-  input  logic                FlushDCacheM,                         // Flush D cache to next level of memory
-  output logic                CommittedM,                           // Delay interrupts while memory operation in flight
-  output logic                SquashSCW,                            // Store conditional failed disable write to GPR
-  output logic                DCacheMiss,                           // D cache miss for performance counters
-  output logic                DCacheAccess,                         // D cache memory access for performance counters
+  input  logic [1:0]              MemRWM,                               // Read/Write control
+  input  logic [2:0]              Funct3M,                              // Size of memory operation
+  input  logic [6:0]              Funct7M,                              // Atomic memory operation function
+  input  logic [1:0]              AtomicM,                              // Atomic memory operation
+  input  logic                    FlushDCacheM,                         // Flush D cache to next level of memory
+  input  logic [3:0]              CMOpM,                                // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  input  logic                    LSUPrefetchM,                         // Prefetch
+  output logic                    CommittedM,                           // Delay interrupts while memory operation in flight
+  output logic                    SquashSCW,                            // Store conditional failed disable write to GPR
+  output logic                    DCacheMiss,                           // D cache miss for performance counters
+  output logic                    DCacheAccess,                         // D cache memory access for performance counters
   // address and write data
-  input  logic [`XLEN-1:0]    IEUAdrE,                              // Execution stage memory address
-  output logic [`XLEN-1:0]    IEUAdrM,                              // Memory stage memory address
-  input  logic [`XLEN-1:0]    WriteDataM,                           // Write data from IEU
-  output logic [`LLEN-1:0]    ReadDataW,                            // Read data to IEU or FPU
+  input  logic [P.XLEN-1:0]       IEUAdrE,                              // Execution stage memory address
+  output logic [P.XLEN-1:0]       IEUAdrM,                              // Memory stage memory address
+  input  logic [P.XLEN-1:0]       WriteDataM,                           // Write data from IEU
+  output logic [P.LLEN-1:0]       ReadDataW,                            // Read data to IEU or FPU
   // cpu privilege
-  input  logic [1:0]          PrivilegeModeW,                       // Current privilege mode
-  input  logic                BigEndianM,                           // Swap byte order to big endian
-  input  logic                sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
-  output logic                DCacheStallM,                         // D$ busy with multicycle operation
+  input  logic [1:0]              PrivilegeModeW,                       // Current privilege mode
+  input  logic                    BigEndianM,                           // Swap byte order to big endian
+  input  logic                    sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
+  output logic                    DCacheStallM,                         // D$ busy with multicycle operation
   // fpu
-  input  logic [`FLEN-1:0]    FWriteDataM,                          // Write data from FPU
-  input  logic                FpLoadStoreM,                         // Selects FPU as store for write data
+  input  logic [P.FLEN-1:0]       FWriteDataM,                          // Write data from FPU
+  input  logic                    FpLoadStoreM,                         // Selects FPU as store for write data
   // faults
-  output logic                LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
-  output logic                LoadMisalignedFaultM,                 // Load address misaligned fault
-  output logic                LoadAccessFaultM,                     // Load access fault (PMA)
-  output logic                HPTWInstrAccessFaultF,                // HPTW generated access fault during instruction fetch
+  output logic                    LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
+  output logic                    LoadMisalignedFaultM,                 // Load address misaligned fault
+  output logic                    LoadAccessFaultM,                     // Load access fault (PMA)
+  output logic                    HPTWInstrAccessFaultF,                // HPTW generated access fault during instruction fetch
   // cpu hazard unit (trap)
-  output logic                StoreAmoMisalignedFaultM,             // Store or AMO address misaligned fault
-  output logic                StoreAmoAccessFaultM,                 // Store or AMO access fault
+  output logic                    StoreAmoMisalignedFaultM,             // Store or AMO address misaligned fault
+  output logic                    StoreAmoAccessFaultM,                 // Store or AMO access fault
   // connect to ahb
-  output logic [`PA_BITS-1:0] LSUHADDR,                             // Bus address from LSU to EBU
-  input  logic [`XLEN-1:0]    HRDATA,                               // Bus read data from LSU to EBU
-  output logic [`XLEN-1:0]    LSUHWDATA,                            // Bus write data from LSU to EBU
-  input  logic                LSUHREADY,                            // Bus ready from LSU to EBU
-  output logic                LSUHWRITE,                            // Bus write operation from LSU to EBU
-  output logic [2:0]          LSUHSIZE,                             // Bus operation size from LSU to EBU
-  output logic [2:0]          LSUHBURST,                            // Bus burst from LSU to EBU
-  output logic [1:0]          LSUHTRANS,                            // Bus transaction type from LSU to EBU
-  output logic [`XLEN/8-1:0]  LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
+  output logic [P.PA_BITS-1:0]    LSUHADDR,                             // Bus address from LSU to EBU
+  input  logic [P.XLEN-1:0]       HRDATA,                               // Bus read data from LSU to EBU
+  output logic [P.XLEN-1:0]       LSUHWDATA,                            // Bus write data from LSU to EBU
+  input  logic                    LSUHREADY,                            // Bus ready from LSU to EBU
+  output logic                    LSUHWRITE,                            // Bus write operation from LSU to EBU
+  output logic [2:0]              LSUHSIZE,                             // Bus operation size from LSU to EBU
+  output logic [2:0]              LSUHBURST,                            // Bus burst from LSU to EBU
+  output logic [1:0]              LSUHTRANS,                            // Bus transaction type from LSU to EBU
+  output logic [P.XLEN/8-1:0]     LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
   // page table walker
-  input  logic [`XLEN-1:0]    SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
-  input  logic                STATUS_MXR, STATUS_SUM, STATUS_MPRV,  // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
-  input  logic [1:0]          STATUS_MPP,                           // Machine previous privilege mode
-  input  logic [`XLEN-1:0]    PCSpillF,                             // Fetch PC 
-  input  logic                ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
-  input  logic                InstrUpdateDAF,                       // ITLB hit needs to update dirty or access bits
-  output logic [`XLEN-1:0]    PTE,                                  // Page table entry write to ITLB
-  output logic [1:0]          PageType,                             // Type of page table entry to write to ITLB
-  output logic                ITLBWriteF,                           // Write PTE to ITLB
-  output logic                SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],  // PMP configuration from privileged unit
-  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]  // PMP address from privileged unit
+  input  logic [P.XLEN-1:0]       SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
+  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,  // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
+  input  logic [1:0]              STATUS_MPP,                           // Machine previous privilege mode
+  input  logic [P.XLEN-1:0]       PCSpillF,                             // Fetch PC 
+  input  logic                    ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
+  input  logic                    InstrUpdateDAF,                       // ITLB hit needs to update dirty or access bits
+  output logic [P.XLEN-1:0]       PTE,                                  // Page table entry write to ITLB
+  output logic [1:0]              PageType,                             // Type of page table entry to write to ITLB
+  output logic                    ITLBWriteF,                           // Write PTE to ITLB
+  output logic                    SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
+  input var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
+  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
 );
 
-  logic [`XLEN+1:0]     IEUAdrExtM;                             // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [`XLEN+1:0]     IEUAdrExtE;                             // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [`PA_BITS-1:0]  PAdrM;                                  // Physical memory address
-  logic [`XLEN+1:0]     IHAdrM;                                 // Either IEU or HPTW memory address
+  logic [P.XLEN+1:0]     IEUAdrExtM;                             // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [P.XLEN+1:0]     IEUAdrExtE;                             // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [P.PA_BITS-1:0]  PAdrM;                                  // Physical memory address
+  logic [P.XLEN+1:0]     IHAdrM;                                 // Either IEU or HPTW memory address
 
-  logic [1:0]           PreLSURWM;                              // IEU or HPTW Read/Write signal
-  logic [1:0]           LSURWM;                                 // IEU or HPTW Read/Write signal gated by LR/SC
-  logic [2:0]           LSUFunct3M;                             // IEU or HPTW memory operation size
-  logic [6:0]           LSUFunct7M;                             // AMO function gated by HPTW
-  logic [1:0]           LSUAtomicM;                             // AMO signal gated by HPTW
+  logic [1:0]            PreLSURWM;                              // IEU or HPTW Read/Write signal
+  logic [1:0]            LSURWM;                                 // IEU or HPTW Read/Write signal gated by LR/SC
+  logic [2:0]            LSUFunct3M;                             // IEU or HPTW memory operation size
+  logic [6:0]            LSUFunct7M;                             // AMO function gated by HPTW
+  logic [1:0]            LSUAtomicM;                             // AMO signal gated by HPTW
 
-  logic                 GatedStallW;                            // Hazard unit StallW gated when SelHPTW = 1
+  logic                  GatedStallW;                            // Hazard unit StallW gated when SelHPTW = 1
   
-  logic                 BusStall;                               // Bus interface busy with multicycle operation
-  logic                 HPTWStall;                              // HPTW busy with multicycle operation
+  logic                  BusStall;                               // Bus interface busy with multicycle operation
+  logic                  HPTWStall;                              // HPTW busy with multicycle operation
 
-  logic                 CacheableM;                             // PMA indicates memory address is cacheable
-  logic                 BusCommittedM;                          // Bus memory operation in flight, delay interrupts
-  logic                 DCacheCommittedM;                       // D$ memory operation started, delay interrupts
+  logic                  CacheableM;                             // PMA indicates memory address is cacheable
+  logic                  BusCommittedM;                          // Bus memory operation in flight, delay interrupts
+  logic                  DCacheCommittedM;                       // D$ memory operation started, delay interrupts
 
-  logic [`LLEN-1:0]     DTIMReadDataWordM;                      // DTIM read data
-  logic [`LLEN-1:0]     DCacheReadDataWordM;                    // D$ read data
-  logic [`LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
-  logic [`LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
-  logic [`LLEN-1:0]     ReadDataWordM;                          // Read data before subword selection
-  logic [`LLEN-1:0]     ReadDataM;                              // Final read data
+  logic [P.LLEN-1:0]     DTIMReadDataWordM;                      // DTIM read data
+  logic [P.LLEN-1:0]     DCacheReadDataWordM;                    // D$ read data
+  logic [P.LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
+  logic [P.LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
+  logic [P.LLEN-1:0]     ReadDataWordM;                          // Read data before subword selection
+  logic [P.LLEN-1:0]     ReadDataM;                              // Final read data
 
-  logic [`XLEN-1:0]     IHWriteDataM;                           // IEU or HPTW write data
-  logic [`XLEN-1:0]     IMAWriteDataM;                          // IEU, HPTW, or AMO write data
-  logic [`LLEN-1:0]     IMAFWriteDataM;                         // IEU, HPTW, AMO, or FPU write data
-  logic [`LLEN-1:0]     LittleEndianWriteDataM;                 // Ending-swapped write data 
-  logic [`LLEN-1:0]     LSUWriteDataM;                          // Final write data
-  logic [(`LLEN-1)/8:0] ByteMaskM;                              // Selects which bytes within a word to write
+  logic [P.XLEN-1:0]     IHWriteDataM;                           // IEU or HPTW write data
+  logic [P.XLEN-1:0]     IMAWriteDataM;                          // IEU, HPTW, or AMO write data
+  logic [P.LLEN-1:0]     IMAFWriteDataM;                         // IEU, HPTW, AMO, or FPU write data
+  logic [P.LLEN-1:0]     LittleEndianWriteDataM;                 // Ending-swapped write data 
+  logic [P.LLEN-1:0]     LSUWriteDataM;                          // Final write data
+  logic [(P.LLEN-1)/8:0] ByteMaskM;                              // Selects which bytes within a word to write
 
-  logic                 DTLBMissM;                              // DTLB miss causes HPTW walk
-  logic                 DTLBWriteM;                             // Writes PTE and PageType to DTLB
-  logic                 DataUpdateDAM;                          // DTLB hit needs to update dirty or access bits
-  logic                 LSULoadAccessFaultM;                    // Load acces fault
-  logic                 LSUStoreAmoAccessFaultM;                // Store access fault
-  logic                 IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
-  logic                 IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
-  logic                 SelDTIM;                                // Select DTIM rather than bus or D$
+  logic                  DTLBMissM;                              // DTLB miss causes HPTW walk
+  logic                  DTLBWriteM;                             // Writes PTE and PageType to DTLB
+  logic                  DataUpdateDAM;                          // DTLB hit needs to update dirty or access bits
+  logic                  LSULoadAccessFaultM;                    // Load acces fault
+  logic                  LSUStoreAmoAccessFaultM;                // Store access fault
+  logic                  IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
+  logic                  IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
+  logic                  SelDTIM;                                // Select DTIM rather than bus or D$
 
-  
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
   // Zero-extend address to 34 bits for XLEN=32
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
+  flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   assign IEUAdrExtM = {2'b00, IEUAdrM}; 
   assign IEUAdrExtE = {2'b00, IEUAdrE};
 
@@ -149,12 +148,12 @@ module lsu (
   // MMU include PMP and is needed if any privileged supported
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`VIRTMEM_SUPPORTED) begin : hptw
-    hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
+  if(P.VIRTMEM_SUPPORTED) begin : hptw
+    hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
-      .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
+      .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
       .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
       .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
       .IHAdrM, .HPTWStall, .SelHPTW,
@@ -184,10 +183,10 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
   // MMU and misalignment fault logic required if privileged unit exists
   /////////////////////////////////////////////////////////////////////////////////////////////
-  if(`ZICSR_SUPPORTED == 1) begin : dmmu
+  if(P.ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
     assign DisableTranslation = SelHPTW | FlushDCacheM;
-    mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
+    mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
     dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
       .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
       .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
@@ -204,9 +203,9 @@ module lsu (
   end else begin  // No MMU, so no PMA/page faults and no address translation
     assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
     assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
-    assign PAdrM = IHAdrM[`PA_BITS-1:0];
+    assign PAdrM = IHAdrM[P.PA_BITS-1:0];
     assign CacheableM = 1'b1;
-    assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM.  If there is 
+    assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM.  If there is 
     // a bus then this is always 0. Cannot have both without PMA.
   end
   
@@ -222,49 +221,51 @@ module lsu (
   // Discard memory request on pipeline flush
   assign IgnoreRequest = IgnoreRequestTLB | FlushW;
   
-  if (`DTIM_SUPPORTED) begin : dtim
-    logic [`PA_BITS-1:0] DTIMAdr;
-    logic [1:0]          DTIMMemRWM;
+  if (P.DTIM_SUPPORTED) begin : dtim
+    logic [P.PA_BITS-1:0] DTIMAdr;
+    logic [1:0]           DTIMMemRWM;
     
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
-  mux2 #(`PA_BITS) DTIMAdrMux(IEUAdrExtE[`PA_BITS-1:0], IEUAdrExtM[`PA_BITS-1:0], MemRWM[0], DTIMAdr);
+    mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
     // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
     // **** create config to support DTIM with floating point.
-    dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
+    dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
               .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
-              .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
+              .ReadDataWordM(DTIMReadDataWordM[P.XLEN-1:0]), .ByteMaskM(ByteMaskM[P.XLEN/8-1:0]));
   end else begin
   end
-  if (`BUS_SUPPORTED) begin : bus              
-    if(`DCACHE_SUPPORTED) begin : dcache
-      localparam   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
-      localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
-      localparam   BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW;                 // Number of AHBW words (beats) in cacheline
-      localparam   AHBWLOGBWPL = $clog2(BEATSPERLINE);                         // Log2 of ^
-      localparam   LINELEN = `DCACHE_LINELENINBITS;                            // Number of bits in cacheline
-      localparam   LLENPOVERAHBW = `LLEN / `AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+  if (P.BUS_SUPPORTED) begin : bus              
+    if(P.DCACHE_SUPPORTED) begin : dcache
+      localparam   LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN;             // Number of LLEN words in cacheline
+      localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                       // Log2 of ^
+      localparam   BEATSPERLINE = P.DCACHE_LINELENINBITS/P.AHBW;                 // Number of AHBW words (beats) in cacheline
+      localparam   AHBWLOGBWPL = $clog2(BEATSPERLINE);                           // Log2 of ^
+      localparam   LINELEN = P.DCACHE_LINELENINBITS;                             // Number of bits in cacheline
+      localparam   LLENPOVERAHBW = P.LLEN / P.AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
 
-      logic [LINELEN-1:0]  FetchBuffer;                                                // Temporary buffer to hold partially fetched cacheline
-      logic [`PA_BITS-1:0] DCacheBusAdr;                                               // Cacheline address to fetch or writeback.
-      logic [AHBWLOGBWPL-1:0]  BeatCount;                                              // Position within a cacheline.  ahbcacheinterface to cache
-      logic                DCacheBusAck;                                               // ahbcacheinterface completed fetch or writeback
-      logic                SelBusBeat;                                                 // ahbcacheinterface selects postion in cacheline with BeatCount
-      logic [1:0]        CacheBusRW;                                                 // Cache sends request to ahbcacheinterface
-    logic [1:0]        BusRW;                                                      // Uncached bus memory access
-      logic                CacheableOrFlushCacheM;                                     // Memory address is cacheable or operation is a cache flush
-      logic [1:0]        CacheRWM;                                                   // Cache read (10), write (01), AMO (11)
-    logic [1:0]        CacheAtomicM;                                               // Cache AMO
-    logic          FlushDCache;                                                // Suppress d cache flush if there is an ITLB miss.
+      logic [LINELEN-1:0]      FetchBuffer;                                      // Temporary buffer to hold partially fetched cacheline
+      logic [P.PA_BITS-1:0]    DCacheBusAdr;                                     // Cacheline address to fetch or writeback.
+      logic [AHBWLOGBWPL-1:0]  BeatCount;                                        // Position within a cacheline.  ahbcacheinterface to cache
+      logic                    DCacheBusAck;                                     // ahbcacheinterface completed fetch or writeback
+      logic                    SelBusBeat;                                       // ahbcacheinterface selects postion in cacheline with BeatCount
+      logic [1:0]              CacheBusRW;                                       // Cache sends request to ahbcacheinterface
+      logic [1:0]              BusRW;                                            // Uncached bus memory access
+      logic                    CacheableOrFlushCacheM;                           // Memory address is cacheable or operation is a cache flush
+      logic [1:0]              CacheRWM;                                         // Cache read (10), write (01), AMO (11)
+      logic [1:0]              CacheAtomicM;                                     // Cache AMO
+      logic                    FlushDCache;                                      // Suppress d cache flush if there is an ITLB miss.
       
       assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
       assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
       assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
-    assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
+      assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
       
-      cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
-              .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .READ_ONLY_CACHE(0)) dcache(
+      // *** need RT to add support for CMOpM and LSUPrefetchM (DH 7/2/23)
+      // *** prefetch can just act as a read operation
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
+              .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
         .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
@@ -275,7 +276,7 @@ module lsu (
         .FetchBuffer, .CacheBusRW, 
         .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
 
-      ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
+      ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
         .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
         .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
         .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
@@ -289,25 +290,25 @@ module lsu (
     // Uncache bus access may be smaller width than LLEN.  Duplicate LLENPOVERAHBW times.
       // *** DTIMReadDataWordM should be increased to LLEN.
       // pma should generate exception for LLEN read to periph.
-      mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
-                                    .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
+      mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
+                                    .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
                                     .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
     end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
       logic [1:0] BusRW;                    // Non-DTIM memory access, ignore cacheableM
-      logic [`XLEN-1:0] FetchBuffer;
+      logic [P.XLEN-1:0] FetchBuffer;
       assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
       
       assign LSUHADDR = PAdrM;
       assign LSUHSIZE = LSUFunct3M;
 
-      ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
+      ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
         .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
         .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
         .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
 
     // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
-      if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
-      else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];
+      if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
+      else assign ReadDataWordMuxM = FetchBuffer[P.XLEN-1:0];
       assign LSUHBURST = 3'b0;
       assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
  end
@@ -322,33 +323,35 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Atomic operations
   /////////////////////////////////////////////////////////////////////////////////////////////
-  if (`A_SUPPORTED) begin:atomic
-    atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IHWriteDataM, .PAdrM, 
+ 
+  if (P.A_SUPPORTED) begin:atomic
+    atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
       .IMAWriteDataM, .SquashSCW, .LSURWM);
   end else begin:lrsc
     assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM;
   end
 
-  if (`F_SUPPORTED) 
-    mux2 #(`LLEN) datamux({{{`LLEN-`XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
+  if (P.F_SUPPORTED) 
+    mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
   else assign IMAFWriteDataM = IMAWriteDataM;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Subword Accesses
   /////////////////////////////////////////////////////////////////////////////////////////////
-  subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
+  
+  subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
     .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
-  subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
+  subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
 
   // Compute byte masks
-  swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
+  swbytemask #(P.LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM));
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // MW Pipeline Register
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
+  flopen #(P.LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Big Endian Byte Swapper
@@ -356,12 +359,11 @@ module lsu (
   //  swap the bytes when read from big-endian memory
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if (`BIGENDIAN_SUPPORTED) begin:endian
-    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+  if (P.BIGENDIAN_SUPPORTED) begin:endian
+    endianswap #(P.LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+    endianswap #(P.LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
   end else begin
     assign LSUWriteDataM = LittleEndianWriteDataM;
     assign LittleEndianReadDataWordM = ReadDataWordMuxM;
   end
-
 endmodule
diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
index 49cf2c099..e5666eb84 100644
--- a/src/lsu/subwordread.sv
+++ b/src/lsu/subwordread.sv
@@ -27,16 +27,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module subwordread 
+module subwordread #(parameter LLEN) 
   (
-   input logic [`LLEN-1:0]  ReadDataWordMuxM,
+   input logic [LLEN-1:0]   ReadDataWordMuxM,
    input logic [2:0]        PAdrM,
    input logic [2:0]        Funct3M,
    input logic              FpLoadStoreM, 
    input logic              BigEndianM, 
-   output logic [`LLEN-1:0] ReadDataM
+   output logic [LLEN-1:0]  ReadDataM
 );
 
   logic [7:0]               ByteM; 
@@ -46,7 +44,7 @@ module subwordread
   // Funct3M[1:0] is the size of the memory access.
   assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
 
-  if (`LLEN == 64) begin:swrmux
+  if (LLEN == 64) begin:swrmux
     // ByteMe mux
     always_comb
     case(PAdrSwap[2:0])
@@ -83,15 +81,15 @@ module subwordread
     // sign extension/ NaN boxing
     always_comb
     case(Funct3M)
-      3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                              // lb
-      3'b001:  ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
-      3'b010:  ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};         // lw/flw
-      3'b011:  ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};   // ld/fld
-      3'b100:  ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]};                             // lbu
-    //3'b100:  ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq   - only needed when LLEN=128
-      3'b101:  ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]};                       // lhu
-      3'b110:  ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]};                           // lwu
-      default: ReadDataM = ReadDataWordMuxM;                                          // Shouldn't happen
+      3'b000:  ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM};                              // lb
+      3'b001:  ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
+      3'b010:  ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};         // lw/flw
+      3'b011:  ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};   // ld/fld
+      3'b100:  ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]};                             // lbu
+    //3'b100:  ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq   - only needed when LLEN=128
+      3'b101:  ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]};                       // lhu
+      3'b110:  ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]};                           // lwu
+      default: ReadDataM = ReadDataWordMuxM;                                         // Shouldn't happen
     endcase
 
   end else begin:swrmux // 32-bit
@@ -114,12 +112,12 @@ module subwordread
     // sign extension
     always_comb
     case(Funct3M)
-      3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                                            // lb
-      3'b001:  ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};               // lh/flh
-      3'b010:  ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
+      3'b000:  ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM};                                            // lb
+      3'b001:  ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};               // lh/flh
+      3'b010:  ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
       3'b011:  ReadDataM = ReadDataWordMuxM;                                                        // fld
-      3'b100:  ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]};                                           // lbu
-      3'b101:  ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]};                                     // lhu
+      3'b100:  ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]};                                           // lbu
+      3'b101:  ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]};                                     // lhu
       default: ReadDataM = ReadDataWordMuxM;                                                        // Shouldn't happen
     endcase
   end
diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv
index ee26b78fd..ad21b3c25 100644
--- a/src/lsu/subwordwrite.sv
+++ b/src/lsu/subwordwrite.sv
@@ -27,16 +27,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module subwordwrite (
-  input logic [2:0]          LSUFunct3M,
-  input logic [`LLEN-1:0]    IMAFWriteDataM,
-  output logic [`LLEN-1:0]   LittleEndianWriteDataM
+module subwordwrite #(parameter LLEN) (
+  input logic  [2:0]        LSUFunct3M,
+  input logic  [LLEN-1:0]   IMAFWriteDataM,
+  output logic [LLEN-1:0]   LittleEndianWriteDataM
 );
 
   // Replicate data for subword writes
-  if (`LLEN == 128) begin:sww
+  if (LLEN == 128) begin:sww
     always_comb 
       case(LSUFunct3M[2:0])
         3'b000:  LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
@@ -45,21 +43,21 @@ module subwordwrite (
         3'b011:  LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
         default: LittleEndianWriteDataM = IMAFWriteDataM;            // sq
       endcase
-  end else if (`LLEN == 64) begin:sww
+  end else if (LLEN == 64) begin:sww
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}};  // sb
-        2'b01:  LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}}; // sh
-        2'b10:  LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}}; // sw
-        2'b11:  LittleEndianWriteDataM = IMAFWriteDataM;            // sd
+        2'b00:  LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}};   // sb
+        2'b01:  LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}};  // sh
+        2'b10:  LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}};  // sw
+        2'b11:  LittleEndianWriteDataM = IMAFWriteDataM;             // sd
       endcase
   end else begin:sww // 32-bit
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}};  // sb
-        2'b01:  LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh
-        2'b10:  LittleEndianWriteDataM = IMAFWriteDataM;            // sw
-        default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen
+        2'b00:  LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}};   // sb
+        2'b01:  LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}};  // sh
+        2'b10:  LittleEndianWriteDataM = IMAFWriteDataM;             // sw
+        default: LittleEndianWriteDataM = IMAFWriteDataM;            // shouldn't happen
       endcase
   end
 endmodule
diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv
index 17eedd4c4..ad20a4414 100644
--- a/src/lsu/swbytemask.sv
+++ b/src/lsu/swbytemask.sv
@@ -27,19 +27,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module swbytemask #(parameter WORDLEN = `XLEN)(
-  input logic [2:0]              Size,
-  input logic [$clog2(WORDLEN/8)-1:0] Adr,
-  output logic [WORDLEN/8-1:0]   ByteMask
+module swbytemask #(parameter WORDLEN)(
+  input logic  [2:0]                   Size,
+  input logic  [$clog2(WORDLEN/8)-1:0] Adr,
+  output logic [WORDLEN/8-1:0]         ByteMask
 );
   
   assign ByteMask = ((2**(2**Size))-1) << Adr;
 
 /* Equivalent to the following
 
-  if(`XLEN == 64) begin
+  if(WORDLEN == 64) begin
     always_comb begin
       case(Size[1:0])
         2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
diff --git a/src/mdu/div.sv b/src/mdu/div.sv
index 848760032..c550c06fc 100644
--- a/src/mdu/div.sv
+++ b/src/mdu/div.sv
@@ -26,41 +26,39 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module div(
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallM,
-  input  logic             FlushE,
-  input  logic             IntDivE,                       // integer division/remainder instruction of any type
-  input  logic             DivSignedE,                    // signed division 
-  input  logic             W64E,                          // W-type instructions (divw, divuw, remw, remuw)
-  input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,// Forwarding mux outputs for Source A and B
-  output logic             DivBusyE,                      // Divide is busy - stall pipeline
-  output logic [`XLEN-1:0] QuotM, RemM                    // Quotient and remainder outputs
+module div import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk,
+  input  logic              reset,
+  input  logic              StallM,
+  input  logic              FlushE,
+  input  logic              IntDivE,                        // integer division/remainder instruction of any type
+  input  logic              DivSignedE,                     // signed division 
+  input  logic              W64E,                           // W-type instructions (divw, divuw, remw, remuw)
+  input  logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
+  output logic              DivBusyE,                       // Divide is busy - stall pipeline
+  output logic [P.XLEN-1:0] QuotM, RemM                     // Quotient and remainder outputs
  );
 
-  localparam STEPBITS = $clog2(`XLEN/`IDIV_BITSPERCYCLE); // Number of steps
+  localparam STEPBITS = $clog2(P.XLEN/P.IDIV_BITSPERCYCLE); // Number of steps
 
-  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;  // division FSM state
+  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;    // division FSM state
   statetype state;
 
-  logic [`XLEN-1:0]   W[`IDIV_BITSPERCYCLE:0];            // Residual for each of k steps
-  logic [`XLEN-1:0]   XQ[`IDIV_BITSPERCYCLE:0];           // dividend/quotient for each of k steps
-  logic [`XLEN-1:0]   WNext, XQNext;                      // initialized W and XQ going into registers
-  logic [`XLEN-1:0]   DinE, XinE;                         // divisor & dividend, possibly truncated to 32 bits
-  logic [`XLEN-1:0]   DnE;                                // DnE = ~DinE
-  logic [`XLEN-1:0]   DAbsBE;                             // absolute value of D
-  logic [`XLEN-1:0]   DAbsB;                              // registered absolute value of D, constant during division
-  logic [`XLEN-1:0]   XnE;                                // DXnE = ~XinE
-  logic [`XLEN-1:0]   XInitE;                             // |X|, or original X for divide by 0
-  logic [`XLEN-1:0]   WnM, XQnM;                          // negated residual W and quotient XQ for postprocessing sign correction
-  logic [STEPBITS:0]  step;                               // division step
-  logic               Div0E, Div0M;                       // divide by 0
-  logic               DivStartE;                          // start integer division
-  logic               SignXE, SignDE;                     // sign of dividend and divisor
-  logic               NegQE, NegWM, NegQM;                // negate quotient or residual during postprocessing
+  logic [P.XLEN-1:0]   W[P.IDIV_BITSPERCYCLE:0];            // Residual for each of k steps
+  logic [P.XLEN-1:0]   XQ[P.IDIV_BITSPERCYCLE:0];           // dividend/quotient for each of k steps
+  logic [P.XLEN-1:0]   WNext, XQNext;                       // initialized W and XQ going into registers
+  logic [P.XLEN-1:0]   DinE, XinE;                          // divisor & dividend, possibly truncated to 32 bits
+  logic [P.XLEN-1:0]   DnE;                                 // DnE = ~DinE
+  logic [P.XLEN-1:0]   DAbsBE;                              // absolute value of D
+  logic [P.XLEN-1:0]   DAbsB;                               // registered absolute value of D, constant during division
+  logic [P.XLEN-1:0]   XnE;                                 // DXnE = ~XinE
+  logic [P.XLEN-1:0]   XInitE;                              // |X|, or original X for divide by 0
+  logic [P.XLEN-1:0]   WnM, XQnM;                           // negated residual W and quotient XQ for postprocessing sign correction
+  logic [STEPBITS:0]   step;                                // division step
+  logic                Div0E, Div0M;                        // divide by 0
+  logic                DivStartE;                           // start integer division
+  logic                SignXE, SignDE;                      // sign of dividend and divisor
+  logic                NegQE, NegWM, NegQM;                 // negate quotient or residual during postprocessing
  
   //////////////////////////////
   // Execute Stage: prepare for division calculation with control logic, W logic and absolute values, initialize W and XQ
@@ -71,43 +69,43 @@ module div(
   assign DivBusyE = (state == BUSY) | DivStartE;
 
   // Handle sign extension for W-type instructions
-  if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions
-    mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
-    mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
+  if (P.XLEN == 64) begin:rv64 // RV64 has W-type instructions
+    mux2 #(P.XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
+    mux2 #(P.XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
   end else begin // RV32 has no W-type instructions
     assign XinE = ForwardedSrcAE;
     assign DinE = ForwardedSrcBE;      
     end   
 
   // Extract sign bits and check fo division by zero
-  assign SignDE = DivSignedE & DinE[`XLEN-1]; 
-  assign SignXE = DivSignedE & XinE[`XLEN-1];
+  assign SignDE = DivSignedE & DinE[P.XLEN-1]; 
+  assign SignXE = DivSignedE & XinE[P.XLEN-1];
   assign NegQE = SignDE ^ SignXE;
   assign Div0E = (DinE == 0);
 
   // Take absolute value for signed operations, and negate D to handle subtraction in divider stages
-  neg #(`XLEN) negd(DinE, DnE);
-  mux2 #(`XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE);  // take absolute value for signed operations, and negate for subtraction setp
-  neg #(`XLEN) negx(XinE, XnE);
-  mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
+  neg #(P.XLEN) negd(DinE, DnE);
+  mux2 #(P.XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE);  // take absolute value for signed operations, and negate for subtraction setp
+  neg #(P.XLEN) negx(XinE, XnE);
+  mux3 #(P.XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
 
   //////////////////////////////
   // Division Iterations (effectively stalled execute stage, no suffix)
   //////////////////////////////
 
   // initialization multiplexers on first cycle of operation
-  mux2 #(`XLEN) wmux(W[`IDIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext);
-  mux2 #(`XLEN) xmux(XQ[`IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
+  mux2 #(P.XLEN) wmux(W[P.IDIV_BITSPERCYCLE], {P.XLEN{1'b0}}, DivStartE, WNext);
+  mux2 #(P.XLEN) xmux(XQ[P.IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
 
   // registers before division steps
-  flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]); 
-  flopen #(`XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
-  flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
+  flopen #(P.XLEN) wreg(clk, DivBusyE, WNext, W[0]); 
+  flopen #(P.XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
+  flopen #(P.XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
 
   // one copy of divstep for each bit produced per cycle
   genvar i;
-  for (i=0; i<`IDIV_BITSPERCYCLE; i = i+1)
-    divstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
+  for (i=0; i<P.IDIV_BITSPERCYCLE; i = i+1)
+    divstep #(P.XLEN) divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
 
   //////////////////////////////
   // Memory Stage: output sign correction and special cases
@@ -116,11 +114,11 @@ module div(
   flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
   
   // On final setp of signed operations, negate outputs as needed to get correct sign
-  neg #(`XLEN) qneg(XQ[0], XQnM);
-  neg #(`XLEN) wneg(W[0], WnM);
+  neg #(P.XLEN) qneg(XQ[0], XQnM);
+  neg #(P.XLEN) wneg(W[0], WnM);
   // Select appropriate output: normal, negated, or for divide by zero
-  mux3 #(`XLEN) qmux(XQ[0], XQnM, {`XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
-  mux3 #(`XLEN) remmux(W[0], WnM, XQ[0], {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
+  mux3 #(P.XLEN) qmux(XQ[0], XQnM, {P.XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
+  mux3 #(P.XLEN) remmux(W[0], WnM, XQ[0], {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
 
   //////////////////////////////
   // Divider FSM to sequence Busy and Done
@@ -133,8 +131,8 @@ module div(
         step <= 1;
         if (Div0E) state <= DONE;
         else       state <= BUSY;
-     end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
-        if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
+    end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
+        if (step[STEPBITS] | (P.XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
             state <= DONE;
         end
         step <= step + 1;
diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv
index cb06efda2..712e98866 100644
--- a/src/mdu/divstep.sv
+++ b/src/mdu/divstep.sv
@@ -26,26 +26,24 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 /* verilator lint_off UNOPTFLAT */
 
-module divstep(
-  input  logic [`XLEN-1:0] W,     // Residual in
-  input  logic [`XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
-  input  logic [`XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
-  output logic [`XLEN-1:0] WOut,  // Residual out
-  output logic [`XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
+module divstep #(parameter XLEN) (
+  input  logic [XLEN-1:0] W,     // Residual in
+  input  logic [XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
+  input  logic [XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
+  output logic [XLEN-1:0] WOut,  // Residual out
+  output logic [XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
 );
 
-  logic [`XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
-  logic [`XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
+  logic [XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
+  logic [XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
   logic qi, qib;                  // Quotient digit and its complement
   
-  assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
-  adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
+  assign {WShift, XQOut} = {W[XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
+  adder #(XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
   assign qi = ~qib;
-  mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
+  mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
 endmodule
 
 /* verilator lint_on UNOPTFLAT */
diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv
index 64fdc2891..83327a460 100644
--- a/src/mdu/mdu.sv
+++ b/src/mdu/mdu.sv
@@ -26,38 +26,43 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module mdu(
-  input  logic             clk, reset,
-  input  logic             StallM, StallW, 
-  input  logic             FlushE, FlushM, FlushW,
-  input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
-  input  logic [2:0]       Funct3E, Funct3M,               // type of MDU operation
-  input  logic             IntDivE, W64E,                  // Integer division/remainder, and W-type instrutions
-  output logic [`XLEN-1:0] MDUResultW,                     // multiply/divide result
-  output logic             DivBusyE                        // busy signal to stall pipeline in Execute stage
+module mdu import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
+  input  logic              StallM, StallW, 
+  input  logic              FlushE, FlushM, FlushW,
+  input  logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
+  input  logic [2:0]        Funct3E, Funct3M,               // type of MDU operation
+  input  logic              IntDivE, W64E,                  // Integer division/remainder, and W-type instrutions
+  input  logic              MDUActiveE,                     // Mul/Div instruction being executed
+  output logic [P.XLEN-1:0] MDUResultW,                     // multiply/divide result
+  output logic              DivBusyE                        // busy signal to stall pipeline in Execute stage
 );
 
-  logic [`XLEN*2-1:0]      ProdM;                          // double-width product from mul
-  logic [`XLEN-1:0]        QuotM, RemM;                    // quotient and remainder from intdivrestoring
-  logic [`XLEN-1:0]        PrelimResultM;                  // selected result before W truncation
-  logic [`XLEN-1:0]        MDUResultM;                     // result after W truncation
-  logic                    W64M;                           // W-type instruction
+  logic [P.XLEN*2-1:0]      ProdM;                          // double-width product from mul
+  logic [P.XLEN-1:0]        QuotM, RemM;                    // quotient and remainder from intdivrestoring
+  logic [P.XLEN-1:0]        PrelimResultM;                  // selected result before W truncation
+  logic [P.XLEN-1:0]        MDUResultM;                     // result after W truncation
+  logic                     W64M;                           // W-type instruction
+
+  logic [P.XLEN-1:0]        AMDU, BMDU;                     // Gated inputs to MDU
+
+  // gate data inputs to MDU to only operate when MDU is active.
+  assign AMDU = ForwardedSrcAE & {P.XLEN{MDUActiveE}};
+  assign BMDU = ForwardedSrcBE & {P.XLEN{MDUActiveE}};
 
   // Multiplier
-  mul mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
+  mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
 
   // Divider
   // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
   // When IDIV_ON_FPU is set, use the FPU divider instead
   // In ZMMUL, with M_SUPPORTED = 0, omit the divider
-  if ((`IDIV_ON_FPU) || (!`M_SUPPORTED)) begin:nodiv  
+  if ((P.IDIV_ON_FPU) || (!P.M_SUPPORTED)) begin:nodiv  
     assign QuotM = 0;
     assign RemM = 0;
     assign DivBusyE = 0;
   end else begin:div
-    div div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, 
+    div #(P) div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, 
         .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
   end
     
@@ -65,26 +70,24 @@ module mdu(
   // For ZMMUL, QuotM and RemM are tied to 0, so the mux automatically simplifies
   always_comb
     case (Funct3M)     
-      3'b000: PrelimResultM = ProdM[`XLEN-1:0];          // mul
-      3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulh
-      3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhsu
-      3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhu
-      3'b100: PrelimResultM = QuotM;                     // div
-      3'b101: PrelimResultM = QuotM;                     // divu
-      3'b110: PrelimResultM = RemM;                      // rem
-      3'b111: PrelimResultM = RemM;                      // remu
+      3'b000: PrelimResultM = ProdM[P.XLEN-1:0];          // mul
+      3'b001: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulh
+      3'b010: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulhsu
+      3'b011: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulhu
+      3'b100: PrelimResultM = QuotM;                      // div
+      3'b101: PrelimResultM = QuotM;                      // divu
+      3'b110: PrelimResultM = RemM;                       // rem
+      3'b111: PrelimResultM = RemM;                       // remu
     endcase 
 
   // Handle sign extension for W-type instructions
   flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
-  if (`XLEN == 64) begin:resmux // RV64 has W-type instructions
+  if (P.XLEN == 64) begin:resmux // RV64 has W-type instructions
     assign MDUResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
   end else begin:resmux // RV32 has no W-type instructions
     assign MDUResultM = PrelimResultM;
   end
 
   // Writeback stage pipeline register
-  flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);   
+  flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);   
 endmodule // mdu
-
-
diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv
index 952b4daf2..a5946b95c 100644
--- a/src/mdu/mul.sv
+++ b/src/mdu/mul.sv
@@ -26,14 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module mul(
+module mul #(parameter XLEN) (
   input  logic                clk, reset,
   input  logic                StallM, FlushM,
-  input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
+  input  logic [XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
   input  logic [2:0]          Funct3E,                        // type of multiply
-  output logic [`XLEN*2-1:0]  ProdM                           // double-widthproduct
+  output logic [XLEN*2-1:0]   ProdM                           // double-widthproduct
 );
 
   // Number systems
@@ -50,46 +48,45 @@ module mul(
   // Signed * Unsigned   = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
   // Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
 
-  logic [`XLEN-1:0]   Aprime, Bprime;                       // lower bits of source A and B
+  logic [XLEN-1:0]    Aprime, Bprime;                       // lower bits of source A and B
   logic               MULH, MULHSU;                         // type of multiply
-  logic [`XLEN-2:0]   PA, PB;                               // product of msb and lsbs
+  logic [XLEN-2:0]    PA, PB;                               // product of msb and lsbs
   logic               PP;                                   // product of msbs
-  logic [`XLEN*2-1:0] PP1E, PP2E, PP3E, PP4E;               // partial products
-  logic [`XLEN*2-1:0] PP1M, PP2M, PP3M, PP4M;               // registered partial proudcts
+  logic [XLEN*2-1:0]  PP1E, PP2E, PP3E, PP4E;               // partial products
+  logic [XLEN*2-1:0]  PP1M, PP2M, PP3M, PP4M;               // registered partial proudcts
  
   //////////////////////////////
   // Execute Stage: Compute partial products
   //////////////////////////////
 
-  assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]};
-  assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]};
+  assign Aprime = {1'b0, ForwardedSrcAE[XLEN-2:0]};
+  assign Bprime = {1'b0, ForwardedSrcBE[XLEN-2:0]};
   assign PP1E = Aprime * Bprime;
-  assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0];  
-  assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0];
-  assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1];
+  assign PA = {(XLEN-1){ForwardedSrcAE[XLEN-1]}} & ForwardedSrcBE[XLEN-2:0];  
+  assign PB = {(XLEN-1){ForwardedSrcBE[XLEN-1]}} & ForwardedSrcAE[XLEN-2:0];
+  assign PP = ForwardedSrcAE[XLEN-1] & ForwardedSrcBE[XLEN-1];
 
   // flavor of multiplication
   assign MULH   = (Funct3E == 3'b001);
   assign MULHSU = (Funct3E == 3'b010);
 
   // Select partial products, handling signed multiplication
-  assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
-  assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
+  assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(XLEN-1){1'b0}}};
+  assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(XLEN-1){1'b0}}};
   always_comb 
-  if (MULH)        PP4E = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}}; 
-  else if (MULHSU) PP4E = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
-  else             PP4E = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
+  if (MULH)        PP4E = {1'b1, PP, {(XLEN-3){1'b0}}, 1'b1, {(XLEN){1'b0}}}; 
+  else if (MULHSU) PP4E = {1'b1, ~PP, {(XLEN-2){1'b0}}, 1'b1, {(XLEN-1){1'b0}}};
+  else             PP4E = {1'b0, PP, {(XLEN*2-2){1'b0}}};
 
   //////////////////////////////
   // Memory Stage: Sum partial proudcts
   //////////////////////////////
 
-  flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M); 
-  flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M); 
-  flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); 
-  flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); 
+  flopenrc #(XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M); 
+  flopenrc #(XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M); 
+  flopenrc #(XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); 
+  flopenrc #(XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); 
 
   // add up partial products; this multi-input add implies CSAs and a final CPA
   assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
  endmodule
-
diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
index ddb8423b6..492d55372 100644
--- a/src/mmu/adrdec.sv
+++ b/src/mmu/adrdec.sv
@@ -26,11 +26,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module adrdec (
-  input  logic [`PA_BITS-1:0] PhysicalAddress,  // Physical address to decode
-  input  logic [`PA_BITS-1:0] Base, Range,      // Base and range of peripheral addresses
+module adrdec #(parameter PA_BITS) (
+  input  logic [PA_BITS-1:0]  PhysicalAddress,  // Physical address to decode
+  input  logic [PA_BITS-1:0]  Base, Range,      // Base and range of peripheral addresses
   input  logic                Supported,        // Is this peripheral supported?
   input  logic                AccessValid,      // Is the access type valid?
   input  logic [1:0]          Size,             // Size of access
@@ -52,4 +50,3 @@ module adrdec (
   // Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
   assign Sel = Match & Supported & AccessValid & SizeValid;
 endmodule
-
diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index b1832d8c9..fd15cdd8b 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -26,28 +26,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
   // verilator lint_off UNOPTFLAT 
 
-module adrdecs (
-  input  logic [`PA_BITS-1:0] PhysicalAddress,
-  input  logic                AccessRW, AccessRX, AccessRWX,
-  input  logic [1:0]          Size,
-  output logic [10:0]         SelRegions
+module adrdecs import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.PA_BITS-1:0] PhysicalAddress,
+  input  logic                 AccessRW, AccessRX, AccessRWX,
+  input  logic [1:0]           Size,
+  output logic [10:0]          SelRegions
 );
 
-  localparam logic [3:0]          SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111);
+  localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
  // Determine which region of physical memory (if any) is being accessed
-  adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[10]);  
-  adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[9]);  
-  adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[8]);  
-  adrdec bootromdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[7]);
-  adrdec uncoreramdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[6]);
-  adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[5]);
-  adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[4]);
-  adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]);
-  adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
-  adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); 
+  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[9]);  
+  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[8]);  
+  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[7]);
+  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[6]);
+  adrdec #(P.PA_BITS) clintdec(PhysicalAddress, P.CLINT_BASE[P.PA_BITS-1:0], P.CLINT_RANGE[P.PA_BITS-1:0], P.CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[5]);
+  adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[4]);
+  adrdec #(P.PA_BITS) uartdec(PhysicalAddress, P.UART_BASE[P.PA_BITS-1:0], P.UART_RANGE[P.PA_BITS-1:0], P.UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]);
+  adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
+  adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); 
 
   assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected
 
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index f90e42ce9..029c718df 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -29,83 +29,82 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module hptw (
-  input  logic             clk, reset,
-  input  logic [`XLEN-1:0] SATP_REGW,              // includes SATP.MODE to determine number of levels in page table
-  input  logic [`XLEN-1:0] PCSpillF,               // addresses to translate
-  input  logic [`XLEN+1:0] IEUAdrExtM,             // addresses to translate
-  input  logic [1:0]       MemRWM, AtomicM,
+module hptw import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
+  input  logic [P.XLEN-1:0] SATP_REGW,              // includes SATP.MODE to determine number of levels in page table
+  input  logic [P.XLEN-1:0] PCSpillF,               // addresses to translate
+  input  logic [P.XLEN+1:0] IEUAdrExtM,             // addresses to translate
+  input  logic [1:0]        MemRWM, AtomicM,
   // system status
-  input  logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]       STATUS_MPP,
-  input  logic [1:0]       PrivilegeModeW,
-  input  logic [`XLEN-1:0] ReadDataM,              // page table entry from LSU 
-  input  logic [`XLEN-1:0] WriteDataM,
-  input  logic             DCacheStallM,           // stall from LSU
-  input  logic [2:0]       Funct3M,
-  input  logic [6:0]       Funct7M,
-  input  logic             ITLBMissF,
-  input  logic             DTLBMissM,
-  input  logic             FlushW,
-  input  logic             InstrUpdateDAF,
-  input  logic             DataUpdateDAM,
-  output logic [`XLEN-1:0] PTE,                    // page table entry to TLBs
-  output logic [1:0]       PageType,               // page type to TLBs
-  output logic             ITLBWriteF, DTLBWriteM, // write TLB with new entry
-  output logic [1:0]       PreLSURWM,
-  output logic [`XLEN+1:0] IHAdrM,
-  output logic [`XLEN-1:0] IHWriteDataM,
-  output logic [1:0]       LSUAtomicM,
-  output logic [2:0]       LSUFunct3M,
-  output logic [6:0]       LSUFunct7M,
-  output logic             IgnoreRequestTLB,
-  output logic             SelHPTW,
-  output logic             HPTWStall,
-  input  logic             LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, 
-  output logic             LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultF
+  input  logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input  logic [1:0]        STATUS_MPP,
+  input  logic [1:0]        PrivilegeModeW,
+  input  logic [P.XLEN-1:0] ReadDataM,              // page table entry from LSU 
+  input  logic [P.XLEN-1:0] WriteDataM,
+  input  logic              DCacheStallM,           // stall from LSU
+  input  logic [2:0]        Funct3M,
+  input  logic [6:0]        Funct7M,
+  input  logic              ITLBMissF,
+  input  logic              DTLBMissM,
+  input  logic              FlushW,
+  input  logic              InstrUpdateDAF,
+  input  logic              DataUpdateDAM,
+  output logic [P.XLEN-1:0] PTE,                    // page table entry to TLBs
+  output logic [1:0]        PageType,               // page type to TLBs
+  output logic              ITLBWriteF, DTLBWriteM, // write TLB with new entry
+  output logic [1:0]        PreLSURWM,
+  output logic [P.XLEN+1:0] IHAdrM,
+  output logic [P.XLEN-1:0] IHWriteDataM,
+  output logic [1:0]        LSUAtomicM,
+  output logic [2:0]        LSUFunct3M,
+  output logic [6:0]        LSUFunct7M,
+  output logic              IgnoreRequestTLB,
+  output logic              SelHPTW,
+  output logic              HPTWStall,
+  input  logic              LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, 
+  output logic              LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultF
 );
 
   typedef enum logic [3:0] {L0_ADR, L0_RD, 
           L1_ADR, L1_RD, 
           L2_ADR, L2_RD, 
           L3_ADR, L3_RD, 
-          LEAF, IDLE, UPDATE_PTE} statetype;
+          LEAF, IDLE, UPDATE_PTE,
+          FAULT} statetype;
 
-  logic                    DTLBWalk; // register TLBs translation miss requests
-  logic [`PPN_BITS-1:0]    BasePageTablePPN;
-  logic [`PPN_BITS-1:0]    CurrentPPN;
-  logic                    Executable, Writable, Readable, Valid, PTE_U;
-  logic                    Misaligned, MegapageMisaligned;
-  logic                    ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
-  logic                    StartWalk;
-  logic                    TLBMiss;
-  logic                    PRegEn;
-  logic [1:0]              NextPageType;
-  logic [`SVMODE_BITS-1:0] SvMode;
-  logic [`XLEN-1:0]        TranslationVAdr;
-  logic [`XLEN-1:0]        NextPTE;
-  logic                    UpdatePTE;
-  logic                    HPTWUpdateDA;
-  logic [`PA_BITS-1:0]     HPTWReadAdr;
-  logic                    SelHPTWAdr;
-  logic [`XLEN+1:0]        HPTWAdrExt;
-  logic                    ITLBMissOrUpdateDAF;
-  logic                    DTLBMissOrUpdateDAM;
-  logic                    LSUAccessFaultM;
-  logic [`PA_BITS-1:0]     HPTWAdr;
-  logic [1:0]              HPTWRW;
-  logic [2:0]              HPTWSize; // 32 or 64 bit access
-  statetype                WalkerState, NextWalkerState, InitialWalkerState;
-  logic                    HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault;
-  logic                    HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
-  logic                    HPTWAccessFaultDelay;
-  logic                    TakeHPTWFault, TakeHPTWFaultDelay;
+  logic                     DTLBWalk; // register TLBs translation miss requests
+  logic [P.PPN_BITS-1:0]    BasePageTablePPN;
+  logic [P.PPN_BITS-1:0]    CurrentPPN;
+  logic                     Executable, Writable, Readable, Valid, PTE_U;
+  logic                     Misaligned, MegapageMisaligned;
+  logic                     ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
+  logic                     StartWalk;
+  logic                     TLBMiss;
+  logic                     PRegEn;
+  logic [1:0]               NextPageType;
+  logic [P.SVMODE_BITS-1:0] SvMode;
+  logic [P.XLEN-1:0]        TranslationVAdr;
+  logic [P.XLEN-1:0]        NextPTE;
+  logic                     UpdatePTE;
+  logic                     HPTWUpdateDA;
+  logic [P.PA_BITS-1:0]     HPTWReadAdr;
+  logic                     SelHPTWAdr;
+  logic [P.XLEN+1:0]        HPTWAdrExt;
+  logic                     ITLBMissOrUpdateDAF;
+  logic                     DTLBMissOrUpdateDAM;
+  logic                     LSUAccessFaultM;
+  logic [P.PA_BITS-1:0]     HPTWAdr;
+  logic [1:0]               HPTWRW;
+  logic [2:0]               HPTWSize; // 32 or 64 bit access
+  statetype                 WalkerState, NextWalkerState, InitialWalkerState;
+  logic                     HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault;
+  logic                     HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
+  logic                     HPTWAccessFaultDelay;
+  logic                     TakeHPTWFault, TakeHPTWFaultDelay;
 
   // map hptw access faults onto either the original LSU load/store fault or instruction access fault
-  assign LSUAccessFaultM       = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
-  assign HPTWLoadAccessFault   = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
+  assign LSUAccessFaultM         = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
+  assign HPTWLoadAccessFault     = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
   assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0];
   assign HPTWInstrAccessFault    = LSUAccessFaultM & ~DTLBWalk;
 
@@ -119,18 +118,18 @@ module hptw (
   assign HPTWInstrAccessFaultF = TakeHPTWFaultDelay ? HPTWInstrAccessFaultDelay : 1'b0;
 
   // Extract bits from CSRs and inputs
-  assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
-  assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
+  assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS];
+  assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0];
   assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF);
 
   // Determine which address to translate
-  mux2 #(`XLEN) vadrmux(PCSpillF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
-  assign CurrentPPN = PTE[`PPN_BITS+9:10];
+  mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr);
+  assign CurrentPPN = PTE[P.PPN_BITS+9:10];
 
   // State flops
   flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
   assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE;
-  flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
+  flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
 
   // Assign PTE descriptors common across all XLEN values
   // For non-leaf PTEs, D, A, U bits are reserved and ignored.  They do not cause faults while walking the page table
@@ -140,26 +139,26 @@ module hptw (
   assign ValidLeafPTE = ValidPTE & LeafPTE;
   assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
 
-  if(`SVADU_SUPPORTED) begin : hptwwrites
-    logic                ReadAccess, WriteAccess;
-    logic                InvalidRead, InvalidWrite, InvalidOp;
-    logic                UpperBitsUnequal; 
-    logic                OtherPageFault;
-    logic [1:0]          EffectivePrivilegeMode;
-    logic                ImproperPrivilege;
-    logic                SaveHPTWAdr, SelHPTWWriteAdr;
-    logic [`PA_BITS-1:0] HPTWWriteAdr;  
-    logic                SetDirty;
-    logic                Dirty, Accessed;
-    logic [`XLEN-1:0]    AccessedPTE;
+  if(P.SVADU_SUPPORTED) begin : hptwwrites
+    logic                 ReadAccess, WriteAccess;
+    logic                 InvalidRead, InvalidWrite, InvalidOp;
+    logic                 UpperBitsUnequal; 
+    logic                 OtherPageFault;
+    logic [1:0]           EffectivePrivilegeMode;
+    logic                 ImproperPrivilege;
+    logic                 SaveHPTWAdr, SelHPTWWriteAdr;
+    logic [P.PA_BITS-1:0] HPTWWriteAdr;  
+    logic                 SetDirty;
+    logic                 Dirty, Accessed;
+    logic [P.XLEN-1:0]    AccessedPTE;
 
-    assign AccessedPTE = {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    mux2 #(`XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
-    flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
+    assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
+    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
+    flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
   
     assign SaveHPTWAdr = WalkerState == L0_ADR;
     assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
-    mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); 
+    mux2 #(P.PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); 
 
     assign {Dirty, Accessed} = PTE[7:6];
     assign WriteAccess = MemRWM[0]; // implies | (|AtomicM);
@@ -167,15 +166,15 @@ module hptw (
     assign ReadAccess = MemRWM[1];
 
     assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
-                               ((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
+                               ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
 
     // Check for page faults
-    vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr), 
+    vm64check #(P) vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr), 
       .SV39Mode(), .UpperBitsUnequal);
     assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
     assign InvalidWrite = WriteAccess & ~Writable;
-  assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
+    assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
     assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid;
 
     // hptw needs to know if there is a Dirty or Access fault occuring on this
@@ -195,8 +194,8 @@ module hptw (
   end
 
   // Enable and select signals based on states
-  assign StartWalk = (WalkerState == IDLE) & TLBMiss;
-  assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
+  assign StartWalk  = (WalkerState == IDLE) & TLBMiss;
+  assign HPTWRW[1]  = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
   assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk;
   assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk;
   
@@ -212,16 +211,16 @@ module hptw (
     endcase
 
   // HPTWAdr muxing
-  if (`XLEN==32) begin // RV32
+  if (P.XLEN==32) begin // RV32
     logic [9:0] VPN;
-    logic [`PPN_BITS-1:0] PPN;
+    logic [P.PPN_BITS-1:0] PPN;
     assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
     assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
     assign HPTWReadAdr = {PPN, VPN, 2'b00};
     assign HPTWSize = 3'b010;
   end else begin // RV64
     logic [8:0] VPN;
-    logic [`PPN_BITS-1:0] PPN;
+    logic [P.PPN_BITS-1:0] PPN;
     always_comb
       case (WalkerState) // select VPN field based on HPTW state
         L3_ADR, L3_RD:  VPN = TranslationVAdr[47:39];
@@ -230,19 +229,19 @@ module hptw (
         default:    VPN = TranslationVAdr[20:12];
       endcase
     assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
-            (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
+            (SvMode != P.SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
     assign HPTWReadAdr = {PPN, VPN, 3'b000};
     assign HPTWSize = 3'b011;
   end
 
   // Initial state and misalignment for RV32/64
-  if (`XLEN == 32) begin
+  if (P.XLEN == 32) begin
     assign InitialWalkerState = L1_ADR;
     assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
     assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
   end else begin
     logic  GigapageMisaligned, TerapageMisaligned;
-    assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
+    assign InitialWalkerState = (SvMode == P.SV48) ? L3_ADR : L2_ADR;
     assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
     assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
     assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0      
@@ -260,41 +259,47 @@ module hptw (
   flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
   always_comb 
     case (WalkerState)
-      IDLE:       if (TLBMiss & ~DCacheStallM & ~HPTWAccessFaultDelay) NextWalkerState = InitialWalkerState;
+      IDLE:       if (TLBMiss & ~DCacheStallM)                        NextWalkerState = InitialWalkerState;
                   else                                                NextWalkerState = IDLE;
       L3_ADR:                                                         NextWalkerState = L3_RD; // first access in SV48
       L3_RD:      if (DCacheStallM)                                   NextWalkerState = L3_RD;
-                  else if(LSUAccessFaultM)                            NextWalkerState = IDLE;
+                  else if(LSUAccessFaultM)                            NextWalkerState = FAULT;
                   else                                                NextWalkerState = L2_ADR;
       L2_ADR:     if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
                   else                                                NextWalkerState = LEAF;
       L2_RD:      if (DCacheStallM)                                   NextWalkerState = L2_RD;
-                  else if(LSUAccessFaultM)                            NextWalkerState = IDLE;
+                  else if(LSUAccessFaultM)                            NextWalkerState = FAULT;
                   else                                                NextWalkerState = L1_ADR;
       L1_ADR:     if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
                   else                                                NextWalkerState = LEAF;  
       L1_RD:      if (DCacheStallM)                                   NextWalkerState = L1_RD;
-                  else if(LSUAccessFaultM)                            NextWalkerState = IDLE;
+                  else if(LSUAccessFaultM)                            NextWalkerState = FAULT;
                   else                                                NextWalkerState = L0_ADR;
       L0_ADR:     if (ValidNonLeafPTE)                                NextWalkerState = L0_RD;
                   else                                                NextWalkerState = LEAF;
       L0_RD:      if (DCacheStallM)                                   NextWalkerState = L0_RD;
-                  else if(LSUAccessFaultM)                            NextWalkerState = IDLE;
+                  else if(LSUAccessFaultM)                            NextWalkerState = FAULT;
                   else                                                NextWalkerState = LEAF;
-      LEAF:       if (`SVADU_SUPPORTED & HPTWUpdateDA)                NextWalkerState = UPDATE_PTE;
+      LEAF:       if (P.SVADU_SUPPORTED & HPTWUpdateDA)               NextWalkerState = UPDATE_PTE;
                   else                                                NextWalkerState = IDLE;
       UPDATE_PTE: if(DCacheStallM)                                    NextWalkerState = UPDATE_PTE;
                   else                                                NextWalkerState = LEAF;
+      FAULT:                                                          NextWalkerState = IDLE;
       default:                                                        NextWalkerState = IDLE; // should never be reached
     endcase // case (WalkerState)
 
   assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (LSUAccessFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access.
   assign SelHPTW = WalkerState != IDLE;
-  assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
-  assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss & ~(HPTWAccessFaultDelay));
 
-  assign ITLBMissOrUpdateDAF = ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF);
-  assign DTLBMissOrUpdateDAM = DTLBMissM | (`SVADU_SUPPORTED & DataUpdateDAM);  
+  // RT 30 May 2023: When there is an access fault caused by the hptw itself, the fsm jumps to FAULT, removes
+  // stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay.
+  // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high.
+
+  assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
+  assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss);
+
+  assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF);
+  assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);  
 
   // HTPW address/data/control muxing
 
@@ -304,15 +309,15 @@ module hptw (
   // always block interrupts when using the hardware page table walker.
 
   // multiplex the outputs to LSU
-  if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
-  else            assign HPTWAdrExt = HPTWAdr;
+  if(P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
+  else             assign HPTWAdrExt = HPTWAdr;
   mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
   mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
   mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);    
   mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
-  mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
-  if(`SVADU_SUPPORTED)
-    mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
+  mux2 #(P.XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
+  if(P.SVADU_SUPPORTED)
+    mux2 #(P.XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
   else assign IHWriteDataM = WriteDataM;
 
 endmodule
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index ccbbfaf78..f05073fcf 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -26,90 +26,89 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
-  input  logic                clk, reset,
-  input  logic [`XLEN-1:0]    SATP_REGW,          // Current value of satp CSR (from privileged unit)
-  input  logic                STATUS_MXR,         // Status CSR: make executable page readable
-  input  logic                STATUS_SUM,         // Status CSR: Supervisor access to user memory
-  input  logic                STATUS_MPRV,        // Status CSR: modify machine privilege
-  input  logic [1:0]          STATUS_MPP,         // Status CSR: previous machine privilege level
-  input  logic [1:0]          PrivilegeModeW,     // Current privilege level of the processeor
-  input  logic                DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
-  input  logic [`XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
-  input  logic [1:0]          Size,               // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
-  input  logic [`XLEN-1:0]    PTE,                // page table entry
-  input  logic [1:0]          PageTypeWriteVal,   // page type
-  input  logic                TLBWrite,           // write TLB entry
-  input  logic                TLBFlush,           // Invalidate all TLB entries
-  output logic [`PA_BITS-1:0] PhysicalAddress,    // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
-  output logic                TLBMiss,            // Miss TLB
-  output logic                Cacheable,          // PMA indicates memory address is cachable
-  output logic                Idempotent,         // PMA indicates memory address is idempotent
-  output logic                SelTIM,             // Select a tightly integrated memory
+module mmu import cvw::*;  #(parameter cvw_t P,
+                             parameter TLB_ENTRIES = 8, IMMU = 0) (
+  input  logic                 clk, reset,
+  input  logic [P.XLEN-1:0]    SATP_REGW,          // Current value of satp CSR (from privileged unit)
+  input  logic                 STATUS_MXR,         // Status CSR: make executable page readable
+  input  logic                 STATUS_SUM,         // Status CSR: Supervisor access to user memory
+  input  logic                 STATUS_MPRV,        // Status CSR: modify machine privilege
+  input  logic [1:0]           STATUS_MPP,         // Status CSR: previous machine privilege level
+  input  logic [1:0]           PrivilegeModeW,     // Current privilege level of the processeor
+  input  logic                 DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
+  input  logic [P.XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
+  input  logic [1:0]           Size,               // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
+  input  logic [P.XLEN-1:0]    PTE,                // page table entry
+  input  logic [1:0]           PageTypeWriteVal,   // page type
+  input  logic                 TLBWrite,           // write TLB entry
+  input  logic                 TLBFlush,           // Invalidate all TLB entries
+  output logic [P.PA_BITS-1:0] PhysicalAddress,    // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
+  output logic                 TLBMiss,            // Miss TLB
+  output logic                 Cacheable,          // PMA indicates memory address is cachable
+  output logic                 Idempotent,         // PMA indicates memory address is idempotent
+  output logic                 SelTIM,             // Select a tightly integrated memory
   // Faults
-  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
-  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
-  output logic                UpdateDA,                                                  // page fault due to setting dirty or access bit
-  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
+  output logic                 InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
+  output logic                 InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
+  output logic                 UpdateDA,                                                  // page fault due to setting dirty or access bit
+  output logic                 LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
   // PMA checker signals
-  input  logic                AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                       // PMP configuration
-  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                    // PMP addresses
+  input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
+  input var logic [7:0]        PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],                      // PMP configuration
+  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0]                   // PMP addresses
 );
 
-  logic [`PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
-  logic                       PMAInstrAccessFaultF;     // Instruction access fault from PMA
-  logic                       PMPInstrAccessFaultF;     // Instruction access fault from PMP
-  logic                       PMALoadAccessFaultM;      // Load access fault from PMA
-  logic                       PMPLoadAccessFaultM;      // Load access fault from PMP
-  logic                       PMAStoreAmoAccessFaultM;  // Store or AMO access fault from PMA
-  logic                       PMPStoreAmoAccessFaultM;  // Store or AMO access fault from PMP
-  logic                       DataMisalignedM;          // load or store misaligned
-  logic                       Translate;                // Translation occurs when virtual memory is active and DisableTranslation is off
-  logic                       TLBHit;                   // Hit in TLB
-  logic                       TLBPageFault;             // Page fault from TLB
-  logic                       ReadNoAmoAccessM;         // Read that is not part of atomic operation causes Load faults.  Otherwise StoreAmo faults
+  logic [P.PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
+  logic                        PMAInstrAccessFaultF;     // Instruction access fault from PMA
+  logic                        PMPInstrAccessFaultF;     // Instruction access fault from PMP
+  logic                        PMALoadAccessFaultM;      // Load access fault from PMA
+  logic                        PMPLoadAccessFaultM;      // Load access fault from PMP
+  logic                        PMAStoreAmoAccessFaultM;  // Store or AMO access fault from PMA
+  logic                        PMPStoreAmoAccessFaultM;  // Store or AMO access fault from PMP
+  logic                        DataMisalignedM;          // load or store misaligned
+  logic                        Translate;                // Translation occurs when virtual memory is active and DisableTranslation is off
+  logic                        TLBHit;                   // Hit in TLB
+  logic                        TLBPageFault;             // Page fault from TLB
+  logic                        ReadNoAmoAccessM;         // Read that is not part of atomic operation causes Load faults.  Otherwise StoreAmo faults
   
   // only instantiate TLB if Virtual Memory is supported
-  if (`VIRTMEM_SUPPORTED) begin:tlb
+  if (P.VIRTMEM_SUPPORTED) begin:tlb
     logic ReadAccess, WriteAccess;
     assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read.  Execute and Read are never active for the same MMU, so safe to mix pipestages
     assign WriteAccess = WriteAccessM;
-    tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
+    tlb #(.P(P), .TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
           .clk, .reset,
-          .SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
-          .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
-          .VAdr(VAdr[`XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+          .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
+          .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
+          .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
           .PrivilegeModeW, .ReadAccess, .WriteAccess,
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
           .Translate, .TLBPageFault, .UpdateDA);
   end else begin:tlb // just pass address through as physical
-    assign Translate = 0;
-    assign TLBMiss = 0;
-    assign TLBHit = 1; // *** is this necessary
+    assign Translate    = 0;
+    assign TLBMiss      = 0;
+    assign TLBHit       = 1; // *** is this necessary
     assign TLBPageFault = 0;
   end
 
   // If translation is occuring, select translated physical address from TLB
   // the lower 12 bits are the page offset. These are never changed from the orginal
   // non translated address.
-  mux2 #(`PA_BITS-12) addressmux(VAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
+  mux2 #(P.PA_BITS-12) addressmux(VAdr[P.PA_BITS-1:12], TLBPAdr[P.PA_BITS-1:12], Translate, PhysicalAddress[P.PA_BITS-1:12]);
   assign PhysicalAddress[11:0] = VAdr[11:0];
   
   ///////////////////////////////////////////
   // Check physical memory accesses
   ///////////////////////////////////////////
 
-  pmachecker pmachecker(.PhysicalAddress, .Size,
+  pmachecker #(P) pmachecker(.PhysicalAddress, .Size,
     .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
-  if (`PMP_ENTRIES > 0) begin : pmp
-    pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
+  if (P.PMP_ENTRIES > 0) begin : pmp
+    pmpchecker #(P) pmpchecker(.PhysicalAddress, .PrivilegeModeW,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
       .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
@@ -128,7 +127,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
   assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
 
   // Misaligned faults
-   always_comb
+   always_comb // exclusion-tag: immu-wordaccess
     case(Size[1:0]) 
       2'b00:  DataMisalignedM = 0;                 // lb, sb, lbu
       2'b01:  DataMisalignedM = VAdr[0];           // lh, sh, lhu
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index 909cc564d..41d8f9b74 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -28,48 +28,45 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module pmachecker (
-  input  logic [`PA_BITS-1:0] PhysicalAddress,
-  input  logic [1:0]          Size,
-  input  logic                AtomicAccessM,  // Atomic access
-  input  logic                ExecuteAccessF, // Execute access 
-  input  logic                WriteAccessM,   // Write access 
-  input  logic                ReadAccessM,    // Read access
-  output logic                Cacheable, Idempotent, SelTIM,
-  output logic                PMAInstrAccessFaultF,
-  output logic                PMALoadAccessFaultM,
-  output logic                PMAStoreAmoAccessFaultM
+module pmachecker import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.PA_BITS-1:0] PhysicalAddress,
+  input  logic [1:0]           Size,
+  input  logic                 AtomicAccessM,  // Atomic access
+  input  logic                 ExecuteAccessF, // Execute access 
+  input  logic                 WriteAccessM,   // Write access 
+  input  logic                 ReadAccessM,    // Read access
+  output logic                 Cacheable, Idempotent, SelTIM,
+  output logic                 PMAInstrAccessFaultF,
+  output logic                 PMALoadAccessFaultM,
+  output logic                 PMAStoreAmoAccessFaultM
 );
 
-  logic                       PMAAccessFault;
-  logic                       AccessRW, AccessRWX, AccessRX;
-  logic [10:0]                SelRegions;
-  logic                       AtomicAllowed;
+  logic                        PMAAccessFault;
+  logic                        AccessRW, AccessRWX, AccessRX;
+  logic [10:0]                 SelRegions;
+  logic                        AtomicAllowed;
 
   // Determine what type of access is being made
-  assign AccessRW = ReadAccessM | WriteAccessM;
+  assign AccessRW  = ReadAccessM | WriteAccessM;
   assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
-  assign AccessRX = ReadAccessM | ExecuteAccessF;
+  assign AccessRX  = ReadAccessM | ExecuteAccessF;
 
   // Determine which region of physical memory (if any) is being accessed
-  adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
+  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
 
   // Only non-core RAM/ROM memory regions are cacheable
-  assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];
+  assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];  // exclusion-tag: unused-cachable
   // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
   // I/O is nonidempotent.  
-  assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6];
+  assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-idempotent
   // Atomic operations are only allowed on RAM
-  assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6];
+  assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; // exclusion-tag: unused-atomic
   // Check if tightly integrated memories are selected
-  assign SelTIM = SelRegions[10] | SelRegions[9];
+  assign SelTIM = SelRegions[10] | SelRegions[9]; // exclusion-tag: unused-tim
 
   // Detect access faults
-  assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;  
-  assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
-  assign PMALoadAccessFaultM  = ReadAccessM    & PMAAccessFault;
+  assign PMAAccessFault          = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;  
+  assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
+  assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
   assign PMAStoreAmoAccessFaultM = WriteAccessM   & PMAAccessFault;
 endmodule
-
diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv
index f36fa99fc..9f283772d 100644
--- a/src/mmu/pmpadrdec.sv
+++ b/src/mmu/pmpadrdec.sv
@@ -30,12 +30,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module pmpadrdec (
-  input  logic [`PA_BITS-1:0]   PhysicalAddress,
+module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.PA_BITS-1:0]  PhysicalAddress,
   input  logic [7:0]            PMPCfg,
-  input  logic [`PA_BITS-3:0]      PMPAdr,
+  input  logic [P.PA_BITS-3:0]  PMPAdr,
   input  logic                  PAgePMPAdrIn,
   output logic                  PAgePMPAdrOut,
   output logic                  Match, 
@@ -49,7 +47,7 @@ module pmpadrdec (
 
   logic                         TORMatch, NAMatch;
   logic                         PAltPMPAdr;
-  logic [`PA_BITS-1:0]          CurrentAdrFull;
+  logic [P.PA_BITS-1:0]         CurrentAdrFull;
   logic [1:0]                   AdrMode;
 
   assign AdrMode = PMPCfg[4:3];
@@ -63,16 +61,16 @@ module pmpadrdec (
   assign CurrentAdrFull  = {PMPAdr,  2'b00};
   assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
   assign PAgePMPAdrOut = ~PAltPMPAdr;
-  assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
+  assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn
 
   // Naturally aligned regions
-  logic [`PA_BITS-1:0] NAMask, NABase;
+  logic [P.PA_BITS-1:0] NAMask, NABase;
 
   assign NAMask[1:0] = {2'b11};
-  assign NAMask[`PA_BITS-1:2] = (PMPAdr + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr;
+  assign NAMask[P.PA_BITS-1:2] = (PMPAdr + {{(P.PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr;
   // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. 
   // This assumes we're using at least an NA4 region, but works for any size NAPOT region.
-  assign NABase = {(PMPAdr & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. 
+  assign NABase = {(PMPAdr & ~NAMask[P.PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. 
   
   assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range
 
@@ -89,4 +87,3 @@ module pmpadrdec (
   // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This
   // implementation will not detect the failure.
  endmodule
-
diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
index e7c660ca0..89c22c486 100644
--- a/src/mmu/pmpchecker.sv
+++ b/src/mmu/pmpchecker.sv
@@ -29,10 +29,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module pmpchecker (
-  input  logic [`PA_BITS-1:0]      PhysicalAddress,  
+module pmpchecker import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.PA_BITS-1:0]     PhysicalAddress,  
   input  logic [1:0]               PrivilegeModeW,
   // ModelSim has a switch -svinputport which controls whether input ports
   // are nets (wires) or vars by default. The default setting of this switch is
@@ -41,8 +39,8 @@ module pmpchecker (
   // this will be understood as a var. However, if we don't supply the `var`
   // keyword, the compiler warns us that it's interpreting the signal as a var,
   // which we might not intend.
-  input  var logic [7:0]           PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
-  input  var logic [`PA_BITS-3:0]  PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
+  input  var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
+  input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
   input  logic                     ExecuteAccessF, WriteAccessM, ReadAccessM,
   output logic                     PMPInstrAccessFaultF,
   output logic                     PMPLoadAccessFaultM,
@@ -50,26 +48,26 @@ module pmpchecker (
 );
 
   // Bit i is high when the address falls in PMP region i
-  logic                    EnforcePMP; // should PMP be checked in this privilege level
-  logic [`PMP_ENTRIES-1:0] Match;      // physical address matches one of the pmp ranges
-  logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-  logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
-  logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
+  logic                            EnforcePMP; // should PMP be checked in this privilege level
+  logic [P.PMP_ENTRIES-1:0]        Match;      // physical address matches one of the pmp ranges
+  logic [P.PMP_ENTRIES-1:0]        FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
+  logic [P.PMP_ENTRIES-1:0]        L, X, W, R; // PMP matches and has flag set
+  logic [P.PMP_ENTRIES-1:0]        PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
-  if (`PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
-    pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
+  if (P.PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
+    pmpadrdec #(P) pmpadrdecs[P.PMP_ENTRIES-1:0](
       .PhysicalAddress, 
       .PMPCfg(PMPCFG_ARRAY_REGW),
       .PMPAdr(PMPADDR_ARRAY_REGW),
-      .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
+      .PAgePMPAdrIn({PAgePMPAdr[P.PMP_ENTRIES-2:0], 1'b1}),
       .PAgePMPAdrOut(PAgePMPAdr),
       .Match, .L, .X, .W, .R);
   end
 
-  priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
+  priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
   // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
+  assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode
 
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
   assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv
index 64fd3c95d..c081b0925 100644
--- a/src/mmu/tlb/tlb.sv
+++ b/src/mmu/tlb/tlb.sv
@@ -49,36 +49,35 @@
  *                         RSW(2) -- for OS
  */
 
-`include "wally-config.vh"
-
 // The TLB will have 2**ENTRY_BITS total entries
-module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
-  input logic                     clk, reset,
-  input  logic [`SVMODE_BITS-1:0] SATP_MODE,        // Current address translation mode
-  input  logic [`ASID_BITS-1:0]   SATP_ASID,
-  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]              STATUS_MPP,
-  input  logic [1:0]              PrivilegeModeW,   // Current privilege level of the processeor
-  input  logic                    ReadAccess, 
-  input  logic                    WriteAccess,
-  input  logic                    DisableTranslation,
-  input  logic [`XLEN-1:0]        VAdr,             // address input before translation (could be physical or virtual)
-  input  logic [`XLEN-1:0]        PTE,
-  input  logic [1:0]              PageTypeWriteVal,
-  input  logic                    TLBWrite,
-  input  logic                    TLBFlush,
-  output logic [`PA_BITS-1:0]     TLBPAdr,
-  output logic                    TLBMiss,
-  output logic                    TLBHit,
-  output logic                    Translate,
-  output logic                    TLBPageFault,
-  output logic                    UpdateDA
+module tlb import cvw::*;  #(parameter cvw_t P,
+                             parameter TLB_ENTRIES = 8, ITLB = 0) (
+  input logic                      clk, reset,
+  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,        // Current address translation mode
+  input  logic [P.ASID_BITS-1:0]   SATP_ASID,
+  input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input  logic [1:0]               STATUS_MPP,
+  input  logic [1:0]               PrivilegeModeW,   // Current privilege level of the processeor
+  input  logic                     ReadAccess, 
+  input  logic                     WriteAccess,
+  input  logic                     DisableTranslation,
+  input  logic [P.XLEN-1:0]        VAdr,             // address input before translation (could be physical or virtual)
+  input  logic [P.XLEN-1:0]        PTE,
+  input  logic [1:0]               PageTypeWriteVal,
+  input  logic                     TLBWrite,
+  input  logic                     TLBFlush,
+  output logic [P.PA_BITS-1:0]     TLBPAdr,
+  output logic                     TLBMiss,
+  output logic                     TLBHit,
+  output logic                     Translate,
+  output logic                     TLBPageFault,
+  output logic                     UpdateDA
 );
 
   logic [TLB_ENTRIES-1:0]         Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
   // Sections of the virtual and physical addresses
-  logic [`VPN_BITS-1:0]           VPN;
-  logic [`PPN_BITS-1:0]           PPN;
+  logic [P.VPN_BITS-1:0]          VPN;
+  logic [P.PPN_BITS-1:0]          PPN;
   // Sections of the page table entry
   logic [7:0]                     PTEAccessBits;
   logic [1:0]                     HitPageType;
@@ -87,7 +86,7 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
   logic                           Misaligned;
   logic                           MegapageMisaligned;
 
-  if(`XLEN == 32) begin
+  if(P.XLEN == 32) begin
     assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
     assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
   end else begin // 64-bit
@@ -100,22 +99,22 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
               ((HitPageType == 2'b01) & MegapageMisaligned);
   end
 
-  assign VPN = VAdr[`VPN_BITS+11:12];
+  assign VPN = VAdr[P.VPN_BITS+11:12];
 
-  tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+  tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
     .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
     .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, 
     .UpdateDA, .SV39Mode, .Translate);
 
   tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
-  tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) 
+  tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS) 
   tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, 
            .SATP_ASID, .Matches, .HitPageType, .CAMHit);
-  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
+  tlbram #(P, TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
 
   // Replace segments of the virtual page number with segments of the physical
   // page number. For 4 KB pages, the entire virtual page number is replaced.
   // For superpages, some segments are considered offsets into a larger page.
-  tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
+  tlbmixer #(P) Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
 
 endmodule
diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv
index 449411e20..7a4100829 100644
--- a/src/mmu/tlb/tlbcam.sv
+++ b/src/mmu/tlb/tlbcam.sv
@@ -29,17 +29,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
+module tlbcam  import cvw::*;  #(parameter cvw_t P,
+                                 parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                    clk, reset,
-  input  logic [`VPN_BITS-1:0]    VPN,
+  input  logic [P.VPN_BITS-1:0]    VPN,
   input  logic [1:0]              PageTypeWriteVal,
   input  logic                    SV39Mode,
   input  logic                    TLBFlush,
   input  logic [TLB_ENTRIES-1:0]  WriteEnables,
   input  logic [TLB_ENTRIES-1:0]  PTE_Gs,
-  input  logic [`ASID_BITS-1:0]   SATP_ASID,
+  input  logic [P.ASID_BITS-1:0]   SATP_ASID,
   output logic [TLB_ENTRIES-1:0]  Matches,
   output logic [1:0]              HitPageType,
   output logic                    CAMHit
@@ -53,7 +52,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
   // of page type. However, matches are determined based on a subset of the
   // page number segments.
 
-  tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
+  tlbcamline #(P, KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
     .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
     .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
   assign CAMHit = |Matches & ~TLBFlush;
diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv
index 9f7a68e81..55023006f 100644
--- a/src/mmu/tlb/tlbcamline.sv
+++ b/src/mmu/tlb/tlbcamline.sv
@@ -29,12 +29,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
+module tlbcamline import cvw::*;  #(parameter cvw_t P, 
+                                    parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                  clk, reset,
-  input  logic [`VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
-  input  logic [`ASID_BITS-1:0] SATP_ASID,
+  input  logic [P.VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
+  input  logic [P.ASID_BITS-1:0] SATP_ASID,
   input  logic                  SV39Mode,
   input  logic                  WriteEnable,  // Write a new entry to this line
   input  logic                  PTE_G,
@@ -56,13 +55,13 @@ module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
   logic [1:0]          PageType;
   
   // Split up key and query into sections for each page table level.
-  logic [`ASID_BITS-1:0] Key_ASID;
+  logic [P.ASID_BITS-1:0] Key_ASID;
   logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
   logic MatchASID, Match0, Match1;
 
   assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; 
 
-  if (`XLEN == 32) begin: match
+  if (P.XLEN == 32) begin: match
 
     assign {Key_ASID, Key1, Key0} = Key;
     assign {Query1, Query0} = VPN;
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 9754124da..67d598038 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -26,11 +26,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module tlbcontrol #(parameter ITLB = 0) (
-  input  logic [`SVMODE_BITS-1:0] SATP_MODE,
-  input  logic [`XLEN-1:0]        VAdr,
+module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
+  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
+  input  logic [P.XLEN-1:0]        VAdr,
   input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input  logic [1:0]              STATUS_MPP,
   input  logic [1:0]              PrivilegeModeW, // Current privilege level of the processeor
@@ -58,13 +56,13 @@ module tlbcontrol #(parameter ITLB = 0) (
 
   // Grab the sv mode from SATP and determine whether translation should occur
   assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
-  assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; 
+  assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeMode != P.M_MODE) & ~DisableTranslation; 
 
   // Determine whether TLB is being used
   assign TLBAccess = ReadAccess | WriteAccess;
 
   // Check that upper bits are legal (all 0s or all 1s)
-  vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
+  vm64check #(P) vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
 
   // unswizzle useful PTE bits
   assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
@@ -74,9 +72,9 @@ module tlbcontrol #(parameter ITLB = 0) (
   if (ITLB == 1) begin:itlb // Instruction TLB fault checking
     // User mode may only execute user mode pages, and supervisor mode may
     // only execute non-user mode pages.
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeMode == `S_MODE) & PTE_U);
-    if(`SVADU_SUPPORTED) begin : hptwwrites
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
+      ((EffectivePrivilegeMode == P.S_MODE) & PTE_U);
+    if(P.SVADU_SUPPORTED) begin : hptwwrites
       assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
       assign TLBPageFault = Translate  & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V);
     end else begin
@@ -89,8 +87,8 @@ module tlbcontrol #(parameter ITLB = 0) (
 
     // User mode may only load/store from user mode pages, and supervisor mode
     // may only access user mode pages when STATUS_SUM is low.
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM);
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
+      ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & ~STATUS_SUM);
     // Check for read error. Reads are invalid when the page is not readable
     // (and executable pages are not readable) or when the page is neither
     // readable nor executable (and executable pages are readable).
@@ -98,7 +96,7 @@ module tlbcontrol #(parameter ITLB = 0) (
     // Check for write error. Writes are invalid when the page's write bit is
     // low.
     assign InvalidWrite = WriteAccess & ~PTE_W;
-    if(`SVADU_SUPPORTED) begin : hptwwrites
+    if(P.SVADU_SUPPORTED) begin : hptwwrites
       assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; 
       assign TLBPageFault =  (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V));
     end else begin
diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv
index 6cdb475e3..4cabb33ab 100644
--- a/src/mmu/tlb/tlblru.sv
+++ b/src/mmu/tlb/tlblru.sv
@@ -50,7 +50,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
   assign RUBitsAccessed = AccessLines | RUBits;
   assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
   assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; 
-
-  // enable must be ORd with TLBFlush to ensure flop fires on a flush.  DH 7/8/21
-  flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
+  flopenr #(TLB_ENTRIES) lrustate(clk, reset, (CAMHit | TLBWrite), RUBitsNext, RUBits);
 endmodule
diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv
index f5555c2a1..07d6eb985 100644
--- a/src/mmu/tlb/tlbmixer.sv
+++ b/src/mmu/tlb/tlbmixer.sv
@@ -29,24 +29,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module tlbmixer (
-    input  logic [`VPN_BITS-1:0]   VPN,
-    input  logic [`PPN_BITS-1:0]   PPN,
+module tlbmixer import cvw::*;  #(parameter cvw_t P) (
+    input  logic [P.VPN_BITS-1:0]   VPN,
+    input  logic [P.PPN_BITS-1:0]   PPN,
     input  logic [1:0]             HitPageType,
     input  logic [11:0]            Offset,
     input  logic                   TLBHit,
-    output logic [`PA_BITS-1:0]    TLBPAdr
+    output logic [P.PA_BITS-1:0]    TLBPAdr
 );
 
-  localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS;
-  logic [`PPN_BITS-1:0] ZeroExtendedVPN;
-  logic [`PPN_BITS-1:0] PageNumberMask;
-  logic [`PPN_BITS-1:0] PPNMixed;
+  localparam EXTRA_BITS = P.PPN_BITS - P.VPN_BITS;
+  logic [P.PPN_BITS-1:0] ZeroExtendedVPN;
+  logic [P.PPN_BITS-1:0] PageNumberMask;
+  logic [P.PPN_BITS-1:0] PPNMixed;
 
   // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages
-  if (`XLEN == 32)
+  if (P.XLEN == 32)
     // kilopage: 22 bits of PPN, 0 bits of VPN
     // megapage: 12 bits of PPN, 10 bits of VPN
     mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask);
@@ -60,10 +58,10 @@ module tlbmixer (
   // merge low segments of VPN with high segments of PPN decided by the pagetype.
   assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
   assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // 
-  //mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed);
+  //mux2 #(1) mixmux[P.PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed);
   //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
   // Output the hit physical address if translation is currently on.
   // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
-  mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
+  mux2 #(P.PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
 
 endmodule
diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv
index febb8b6f6..eb8dedca7 100644
--- a/src/mmu/tlb/tlbram.sv
+++ b/src/mmu/tlb/tlbram.sv
@@ -28,27 +28,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
-module tlbram #(parameter TLB_ENTRIES = 8) (
+module tlbram import cvw::*;  #(parameter cvw_t P, 
+                                parameter TLB_ENTRIES = 8) (
   input  logic                      clk, reset,
-  input  logic [`XLEN-1:0]          PTE,
+  input  logic [P.XLEN-1:0]          PTE,
   input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,
-  output logic [`PPN_BITS-1:0]      PPN,
+  output logic [P.PPN_BITS-1:0]      PPN,
   output logic [7:0]                PTEAccessBits,
   output logic [TLB_ENTRIES-1:0]    PTE_Gs
 );
 
-  logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
-  logic [`PPN_BITS+9:0] PageTableEntry;
+  logic [P.PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
+  logic [P.PPN_BITS+9:0] PageTableEntry;
 
   // RAM implemented with array of flops and AND/OR read logic
-  tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
+  tlbramline #(P.PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
      (.clk, .reset, .re(Matches), .we(WriteEnables), 
-      .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
-  or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
+      .d(PTE[P.PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
+  or_rows #(TLB_ENTRIES, P.PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
 
   // Rename the bits read from the TLB RAM
   assign PTEAccessBits = PageTableEntry[7:0];
-  assign PPN = PageTableEntry[`PPN_BITS+9:10];
+  assign PPN = PageTableEntry[P.PPN_BITS+9:10];
 endmodule
diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv
index 035c58d58..cc393f72a 100644
--- a/src/mmu/tlb/tlbramline.sv
+++ b/src/mmu/tlb/tlbramline.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module tlbramline #(parameter WIDTH = 22)
   (input  logic             clk, reset,
    input  logic             re, we,
diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv
index 5f12eef7a..a089031c2 100644
--- a/src/mmu/tlb/vm64check.sv
+++ b/src/mmu/tlb/vm64check.sv
@@ -26,17 +26,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module vm64check (
-  input  logic [`SVMODE_BITS-1:0] SATP_MODE,
-  input  logic [`XLEN-1:0]        VAdr,
+module vm64check import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
+  input  logic [P.XLEN-1:0]        VAdr,
   output logic                    SV39Mode, 
   output logic                    UpperBitsUnequal
 );
 
-  if (`XLEN == 64) begin
-    assign SV39Mode = (SATP_MODE == `SV39);
+  if (P.XLEN == 64) begin
+    assign SV39Mode = (SATP_MODE == P.SV39);
 
     // page fault if upper bits aren't all the same
     logic                           eq_63_47, eq_46_38;
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index db142de5f..ccca40a00 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -28,102 +28,107 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module csr #(parameter
-    MIP = 12'h344,
-    SIP = 12'h144) (
-  input  logic             clk, reset,
-  input  logic             FlushM, FlushW,
-  input  logic             StallE, StallM, StallW,
-  input  logic [31:0]      InstrM,                    // current instruction
-  input  logic [31:0]      InstrOrigM,                // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [`XLEN-1:0] PCM, PC2NextF,             // program counter, next PC going to trap/return logic
-  input  logic [`XLEN-1:0] SrcAM, IEUAdrM,            // SrcA and memory address from IEU
-  input  logic             CSRReadM, CSRWriteM,       // read or write CSR
-  input  logic             TrapM,                     // trap is occurring
-  input  logic             mretM, sretM, wfiM,        // return or WFI instruction
-  input  logic             IntPendingM,               // at least one interrupt is pending and could occur if enabled
-  input  logic             InterruptM,                // interrupt is occurring
-  input  logic             ExceptionM,                // interrupt is occurring
-  input  logic             MTimerInt,                 // timer interrupt
-  input  logic             MExtInt, SExtInt,          // external interrupt (from PLIC) 
-  input  logic             MSwInt,                    // software interrupt
-  input  logic [63:0]      MTIME_CLINT,               // TIME value from CLINT
-  input  logic             InstrValidM,               // current instruction is valid
-  input  logic             FRegWriteM,                // writes to floating point registers change STATUS.FS
-  input  logic [4:0]       SetFflagsM,                // Set floating point flag bits in FCSR
-  input  logic [1:0]       NextPrivilegeModeM,        // STATUS bits updated based on next privilege mode
-  input  logic [1:0]       PrivilegeModeW,            // current privilege mode
-  input  logic [3:0]       CauseM,                    // Trap cause
-  input  logic             SelHPTW,                   // hardware page table walker active, so base endianness on supervisor mode
+module csr import cvw::*;  #(parameter cvw_t P) (
+  input  logic                     clk, reset,
+  input  logic                     FlushM, FlushW,
+  input  logic                     StallE, StallM, StallW,
+  input  logic [31:0]              InstrM,                    // current instruction
+  input  logic [31:0]              InstrOrigM,                // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
+  input  logic [P.XLEN-1:0]        PCM, PC2NextF,             // program counter, next PC going to trap/return logic
+  input  logic [P.XLEN-1:0]        SrcAM, IEUAdrM,            // SrcA and memory address from IEU
+  input  logic                     CSRReadM, CSRWriteM,       // read or write CSR
+  input  logic                     TrapM,                     // trap is occurring
+  input  logic                     mretM, sretM, wfiM,        // return or WFI instruction
+  input  logic                     IntPendingM,               // at least one interrupt is pending and could occur if enabled
+  input  logic                     InterruptM,                // interrupt is occurring
+  input  logic                     ExceptionM,                // interrupt is occurring
+  input  logic                     MTimerInt,                 // timer interrupt
+  input  logic                     MExtInt, SExtInt,          // external interrupt (from PLIC) 
+  input  logic                     MSwInt,                    // software interrupt
+  input  logic [63:0]              MTIME_CLINT,               // TIME value from CLINT
+  input  logic                     InstrValidM,               // current instruction is valid
+  input  logic                     FRegWriteM,                // writes to floating point registers change STATUS.FS
+  input  logic [4:0]               SetFflagsM,                // Set floating point flag bits in FCSR
+  input  logic [1:0]               NextPrivilegeModeM,        // STATUS bits updated based on next privilege mode
+  input  logic [1:0]               PrivilegeModeW,            // current privilege mode
+  input  logic [3:0]               CauseM,                    // Trap cause
+  input  logic                     SelHPTW,                   // hardware page table walker active, so base endianness on supervisor mode
   // inputs for performance counters
-  input  logic             LoadStallD,
-  input  logic             StoreStallD,
-  input  logic             ICacheStallF,
-  input  logic             DCacheStallM,
-  input  logic             BPDirPredWrongM,
-  input  logic             BTAWrongM,
-  input  logic             RASPredPCWrongM,
-  input  logic             IClassWrongM,
-  input  logic             BPWrongM,                              // branch predictor is wrong
-  input  logic [3:0]       InstrClassM,
-  input  logic             DCacheMiss,
-  input  logic             DCacheAccess,
-  input  logic             ICacheMiss,
-  input  logic             ICacheAccess,
-  input  logic             sfencevmaM,
-  input  logic             InvalidateICacheM,
-  input  logic             DivBusyE,                                  // integer divide busy
-  input  logic             FDivBusyE,                                 // floating point divide busy
+  input  logic                     LoadStallD,
+  input  logic                     StoreStallD,
+  input  logic                     ICacheStallF,
+  input  logic                     DCacheStallM,
+  input  logic                     BPDirPredWrongM,
+  input  logic                     BTAWrongM,
+  input  logic                     RASPredPCWrongM,
+  input  logic                     IClassWrongM,
+  input  logic                     BPWrongM,                  // branch predictor is wrong
+  input  logic [3:0]               InstrClassM,
+  input  logic                     DCacheMiss,
+  input  logic                     DCacheAccess,
+  input  logic                     ICacheMiss,
+  input  logic                     ICacheAccess,
+  input  logic                     sfencevmaM,
+  input  logic                     InvalidateICacheM,
+  input  logic                     DivBusyE,                  // integer divide busy
+  input  logic                     FDivBusyE,                 // floating point divide busy
   // outputs from CSRs
-  output logic [1:0]       STATUS_MPP,
-  output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
-  output logic [15:0] MEDELEG_REGW, 
-  output logic [`XLEN-1:0] SATP_REGW,
-  output logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
-  output logic             STATUS_MIE, STATUS_SIE,
-  output logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
-  output logic [1:0]       STATUS_FS,
-  output var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
-  output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
-  output logic [2:0]       FRM_REGW, 
+  output logic [1:0]               STATUS_MPP,
+  output logic                     STATUS_SPP, STATUS_TSR, STATUS_TVM,
+  output logic [15:0]              MEDELEG_REGW, 
+  output logic [P.XLEN-1:0]        SATP_REGW,
+  output logic [11:0]              MIP_REGW, MIE_REGW, MIDELEG_REGW,
+  output logic                     STATUS_MIE, STATUS_SIE,
+  output logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
+  output logic [1:0]               STATUS_FS,
+  output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
+  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],
+  output logic [2:0]               FRM_REGW, 
+  output logic [3:0]               ENVCFG_CBE,
   //
-  output logic [`XLEN-1:0] CSRReadValW,               // value read from CSR
-  output logic [`XLEN-1:0] UnalignedPCNextF,          // Next PC, accounting for traps and returns
-  output logic             IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
-  output logic             BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
+  output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
+  output logic [P.XLEN-1:0]        UnalignedPCNextF,          // Next PC, accounting for traps and returns
+  output logic                     IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
+  output logic                     BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
 );
 
-  logic [`XLEN-1:0]        CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
-  logic [`XLEN-1:0]        CSRReadValM;  
-  logic [`XLEN-1:0]        CSRSrcM;
-  logic [`XLEN-1:0]        CSRRWM, CSRRSM, CSRRCM;  
-  logic [`XLEN-1:0]        CSRWriteValM;
-  logic [`XLEN-1:0]        MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
-  logic [`XLEN-1:0]        STVEC_REGW, MTVEC_REGW;
-  logic [`XLEN-1:0]        MEPC_REGW, SEPC_REGW;
+  localparam MIP = 12'h344;
+  localparam SIP = 12'h144;
+  
+  logic [P.XLEN-1:0]       CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
+  logic [P.XLEN-1:0]       CSRReadValM;  
+  logic [P.XLEN-1:0]       CSRSrcM;
+  logic [P.XLEN-1:0]       CSRRWM, CSRRSM, CSRRCM;  
+  logic [P.XLEN-1:0]       CSRWriteValM;
+  logic [P.XLEN-1:0]       MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
+  logic [P.XLEN-1:0]       STVEC_REGW, MTVEC_REGW;
+  logic [P.XLEN-1:0]       MEPC_REGW, SEPC_REGW;
   logic [31:0]             MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
   logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
   logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
   logic                    UngatedCSRMWriteM;
   logic                    WriteFRMM, WriteFFLAGSM;
-  logic [`XLEN-1:0]        UnalignedNextEPCM, NextEPCM, NextMtvalM;
+  logic [P.XLEN-1:0]       UnalignedNextEPCM, NextEPCM, NextMtvalM;
   logic [4:0]              NextCauseM;
   logic [11:0]             CSRAdrM;
   logic                    IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
   logic                    InsufficientCSRPrivilegeM;
   logic                    IllegalCSRMWriteReadonlyM;
-  logic [`XLEN-1:0]        CSRReadVal2M;
+  logic [P.XLEN-1:0]       CSRReadVal2M;
   logic [11:0]             MIP_REGW_writeable;
-  logic [`XLEN-1:0]        TVecM, TrapVectorM, NextFaultMtvalM;
+  logic [P.XLEN-1:0]       TVecM, TrapVectorM, NextFaultMtvalM;
   logic                    MTrapM, STrapM;
-  logic [`XLEN-1:0]        EPC;
+  logic [P.XLEN-1:0]       EPC;
   logic                    RetM;
   logic                    SelMtvecM;
-  logic [`XLEN-1:0]        TVecAlignedM;
+  logic [P.XLEN-1:0]       TVecAlignedM;
   logic                    InstrValidNotFlushedM;
   logic                    STimerInt;
+  logic [63:0]             MENVCFG_REGW;
+  logic [P.XLEN-1:0]       SENVCFG_REGW;
+  logic                    ENVCFG_STCE; // supervisor timer counter enable
+  logic                    ENVCFG_PBMTE; // page-based memory types enable
+  logic                    ENVCFG_FIOM; // fence implies io (presently not used)
 
   // only valid unflushed instructions can access CSRs
   assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
@@ -136,7 +141,7 @@ module csr #(parameter
     if (InterruptM)           NextFaultMtvalM = 0;
     else case (CauseM)
       12, 1, 3:               NextFaultMtvalM = PCM;  // Instruction page/access faults, breakpoint
-      2:                      NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 
+      2:                      NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 
       0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
       default:                NextFaultMtvalM = 0; // Ecall, interrupts
     endcase
@@ -146,26 +151,26 @@ module csr #(parameter
   ///////////////////////////////////////////
 
   // Select trap vector from STVEC or MTVEC and word-align
-  assign SelMtvecM = (NextPrivilegeModeM == `M_MODE);
-  mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM);
-  assign TVecAlignedM = {TVecM[`XLEN-1:2], 2'b00};
+  assign SelMtvecM = (NextPrivilegeModeM == P.M_MODE);
+  mux2 #(P.XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM);
+  assign TVecAlignedM = {TVecM[P.XLEN-1:2], 2'b00};
 
   // Support vectored interrupts
-  if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
+  if(P.VECTORED_INTERRUPTS_SUPPORTED) begin:vec
     logic VectoredM;
-    logic [`XLEN-1:0] TVecPlusCauseM;
+    logic [P.XLEN-1:0] TVecPlusCauseM;
     assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
-    assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition
-    mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
+    assign TVecPlusCauseM = {TVecAlignedM[P.XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition
+    mux2 #(P.XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
   end else 
-    assign TrapVectorM = TVecAlignedM;
+    assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd
 
   // Trap Returns
   // A trap sets the PC to TrapVector
   // A return sets the PC to MEPC or SEPC
   assign RetM = mretM | sretM;
-  mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
-  mux3 #(`XLEN) pcmux3(PC2NextF, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
+  mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
+  mux3 #(P.XLEN) pcmux3(PC2NextF, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
 
   ///////////////////////////////////////////
   // CSRWriteValM
@@ -173,20 +178,20 @@ module csr #(parameter
 
   always_comb begin
     // Choose either rs1 or uimm[4:0] as source
-    CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+    CSRSrcM = InstrM[14] ? {{(P.XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
 
     // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
-    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, MIP_REGW_writeable};
+    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(P.XLEN-12){1'b0}}, MIP_REGW_writeable};
     else                                 CSRReadVal2M = CSRReadValM;
 
     // Compute AND/OR modification
-    CSRRWM = CSRSrcM;
-    CSRRSM = CSRReadVal2M | CSRSrcM;
-    CSRRCM = CSRReadVal2M & ~CSRSrcM;
+    CSRRWM =   CSRSrcM;
+    CSRRSM =   CSRReadVal2M | CSRSrcM;
+    CSRRCM =   CSRReadVal2M & ~CSRSrcM;
     case (InstrM[13:12])
-      2'b01:  CSRWriteValM = CSRRWM;
-      2'b10:  CSRWriteValM = CSRRSM;
-      2'b11:  CSRWriteValM = CSRRCM;
+      2'b01:   CSRWriteValM = CSRRWM;
+      2'b10:   CSRWriteValM = CSRRSM;
+      2'b11:   CSRWriteValM = CSRRCM;
       default: CSRWriteValM = CSRReadValM;
     endcase
   end
@@ -197,26 +202,26 @@ module csr #(parameter
 
   assign CSRAdrM = InstrM[31:20];
   assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM;
-  assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
-  assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]};
+  assign NextEPCM = P.C_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
-  assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
+  assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);
   assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
   assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
   assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
-  assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
-  assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
+  assign MTrapM = TrapM & (NextPrivilegeModeM == P.M_MODE);
+  assign STrapM = TrapM & (NextPrivilegeModeM == P.S_MODE) & P.S_SUPPORTED;
 
   ///////////////////////////////////////////
   // CSRs
   ///////////////////////////////////////////
 
-  csri   csri(.clk, .reset,  
+  csri #(P) csri(.clk, .reset,  
     .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
     .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
-    .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
+    .MIDELEG_REGW, .ENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
 
-  csrsr csrsr(.clk, .reset, .StallW, 
+  csrsr #(P) csrsr(.clk, .reset, .StallW, 
     .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
     .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
     .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
@@ -225,26 +230,29 @@ module csr #(parameter
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
     .STATUS_FS, .BigEndianM);
 
-  csrm  csrm(.clk, .reset, 
+  csrm #(P) csrm(.clk, .reset, 
     .UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM,
     .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
     .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
     .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, 
     .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
-    .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
+    .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
+    .MENVCFG_REGW);
 
 
-  if (`S_SUPPORTED) begin:csrs
-    csrs  csrs(.clk, .reset,
+  if (P.S_SUPPORTED) begin:csrs
+    logic STCE; 
+    assign STCE = P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_REGW[1] & ENVCFG_STCE));
+    csrs #(P) csrs(.clk, .reset,
       .CSRSWriteM, .STrapM, .CSRAdrM,
       .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
       .STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
       .CSRWriteValM, .PrivilegeModeW,
       .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
       .SCOUNTEREN_REGW,
-      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT,
-      .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt);
+      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE,
+      .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW);
   end else begin
     assign WriteSSTATUSM = 0;
     assign CSRSReadValM = 0;
@@ -256,8 +264,8 @@ module csr #(parameter
   end
 
   // Floating Point CSRs in User Mode only needed if Floating Point is supported
-  if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
-    csru  csru(.clk, .reset, .InstrValidNotFlushedM, 
+  if (P.F_SUPPORTED | P.D_SUPPORTED) begin:csru
+    csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, 
       .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
       .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
       .IllegalCSRUAccessM);
@@ -267,8 +275,8 @@ module csr #(parameter
     assign IllegalCSRUAccessM = 1;
   end
   
-  if (`ZICOUNTERS_SUPPORTED) begin:counters
-    csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
+  if (P.ZICNTR_SUPPORTED) begin:counters
+    csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
       .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
@@ -281,13 +289,24 @@ module csr #(parameter
     assign IllegalCSRCAccessM = 1; // counters aren't enabled
   end
 
+   // Broadcast appropriate environment configuration based on privilege mode
+  assign ENVCFG_STCE =  MENVCFG_REGW[63]; // supervisor timer counter enable
+  assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
+  assign ENVCFG_CBE =   (PrivilegeModeW == P.M_MODE) ? 4'b1111 : 
+                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : 
+                                                                       (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);
+  // FIOM presently doesn't do anything because Wally fences don't do anything
+  assign ENVCFG_FIOM =  (PrivilegeModeW == P.M_MODE) ? 1'b1 : 
+                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : 
+                                                                       (MENVCFG_REGW[0] & SENVCFG_REGW[0]);
+
   // merge CSR Reads
   assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; 
-  flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
+  flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
 
   // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
-  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) |
-                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
+  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
+                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);
   assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & 
     IllegalCSRSAccessM & IllegalCSRUAccessM |
     InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index 297dcd0fb..2944b1a66 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -1,5 +1,3 @@
-
-
 ///////////////////////////////////////////
 // csrc.sv
 //
@@ -30,59 +28,58 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-module csrc #(parameter 
-  MHPMCOUNTERBASE = 12'hB00,
-  MTIME = 12'hB01,               // this is a memory-mapped register; no such CSR exists, and access should fault
-  MHPMCOUNTERHBASE = 12'hB80,
-  MTIMEH = 12'hB81,               // this is a memory-mapped register; no such CSR exists, and access should fault
-  MHPMEVENTBASE = 12'h320,
-  HPMCOUNTERBASE = 12'hC00,
-  HPMCOUNTERHBASE = 12'hC80,
-  TIME  = 12'hC01,
-  TIMEH = 12'hC81
-) (
-  input  logic             clk, reset,
-  input  logic             StallE, StallM, 
-  input  logic             FlushM, 
-  input  logic             InstrValidNotFlushedM, LoadStallD, StoreStallD, 
-  input  logic             CSRMWriteM, CSRWriteM,
-  input  logic             BPDirPredWrongM,
-  input  logic             BTAWrongM,
-  input  logic             RASPredPCWrongM,
-  input  logic             IClassWrongM,
-  input  logic             BPWrongM,                              // branch predictor is wrong
-  input  logic [3:0]       InstrClassM,
-  input  logic             DCacheMiss,
-  input  logic             DCacheAccess,
-  input  logic             ICacheMiss,
-  input  logic             ICacheAccess,
-  input  logic             ICacheStallF,
-  input  logic             DCacheStallM,
-  input  logic             sfencevmaM,
-  input  logic             InterruptM,
-  input  logic             ExceptionM,
-  input  logic             InvalidateICacheM,
-  input  logic             DivBusyE,                                  // integer divide busy
-  input  logic             FDivBusyE,                                 // floating point divide busy
-  input  logic [11:0]      CSRAdrM,
-  input  logic [1:0]       PrivilegeModeW,
-  input  logic [`XLEN-1:0] CSRWriteValM,
-  input  logic [31:0]      MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
-  input  logic [63:0]      MTIME_CLINT, 
-  output logic [`XLEN-1:0] CSRCReadValM,
-  output logic             IllegalCSRCAccessM
+module csrc  import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
+  input  logic              StallE, StallM, 
+  input  logic              FlushM, 
+  input  logic              InstrValidNotFlushedM, LoadStallD, StoreStallD, 
+  input  logic              CSRMWriteM, CSRWriteM,
+  input  logic              BPDirPredWrongM,
+  input  logic              BTAWrongM,
+  input  logic              RASPredPCWrongM,
+  input  logic              IClassWrongM,
+  input  logic              BPWrongM,                                  // branch predictor is wrong
+  input  logic [3:0]        InstrClassM,
+  input  logic              DCacheMiss,
+  input  logic              DCacheAccess,
+  input  logic              ICacheMiss,
+  input  logic              ICacheAccess,
+  input  logic              ICacheStallF,
+  input  logic              DCacheStallM,
+  input  logic              sfencevmaM,
+  input  logic              InterruptM,
+  input  logic              ExceptionM,
+  input  logic              InvalidateICacheM,
+  input  logic              DivBusyE,                                  // integer divide busy
+  input  logic              FDivBusyE,                                 // floating point divide busy
+  input  logic [11:0]       CSRAdrM,
+  input  logic [1:0]        PrivilegeModeW,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
+  input  logic [31:0]       MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
+  input  logic [63:0]       MTIME_CLINT, 
+  output logic [P.XLEN-1:0] CSRCReadValM,
+  output logic              IllegalCSRCAccessM
 );
 
+  localparam MHPMCOUNTERBASE  = 12'hB00;
+  localparam MTIME            = 12'hB01;               // this is a memory-mapped register; no such CSR exists, and access should faul;
+  localparam MHPMCOUNTERHBASE = 12'hB80;
+  localparam MTIMEH           = 12'hB81;               // this is a memory-mapped register; no such CSR exists, and access should fault
+  localparam MHPMEVENTBASE    = 12'h320;
+  localparam HPMCOUNTERBASE   = 12'hC00;
+  localparam HPMCOUNTERHBASE  = 12'hC80;
+  localparam TIME             = 12'hC01;
+  localparam TIMEH            = 12'hC81;
+
   logic [4:0]              CounterNumM;
-  logic [`XLEN-1:0]        HPMCOUNTER_REGW[`COUNTERS-1:0];
-  logic [`XLEN-1:0]        HPMCOUNTERH_REGW[`COUNTERS-1:0];
+  logic [P.XLEN-1:0]       HPMCOUNTER_REGW[P.COUNTERS-1:0];
+  logic [P.XLEN-1:0]       HPMCOUNTERH_REGW[P.COUNTERS-1:0];
   logic                    LoadStallE, LoadStallM;
   logic                    StoreStallE, StoreStallM;
-  logic [`COUNTERS-1:0]    WriteHPMCOUNTERM;
-  logic [`COUNTERS-1:0]    CounterEvent;
-  logic [63:0]             HPMCOUNTERPlusM[`COUNTERS-1:0];
-  logic [`XLEN-1:0]        NextHPMCOUNTERM[`COUNTERS-1:0];
+  logic [P.COUNTERS-1:0]   WriteHPMCOUNTERM;
+  logic [P.COUNTERS-1:0]   CounterEvent;
+  logic [63:0]             HPMCOUNTERPlusM[P.COUNTERS-1:0];
+  logic [P.XLEN-1:0]       NextHPMCOUNTERM[P.COUNTERS-1:0];
   genvar                   i;
 
   // Interface signals
@@ -90,57 +87,57 @@ module csrc #(parameter
   flopenrc #(2) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d({StoreStallE, LoadStallE}), .q({StoreStallM, LoadStallM}));  
   
   // Determine when to increment each counter
-  assign CounterEvent[0] = 1'b1;                                                        // MCYCLE always increments
-  assign CounterEvent[1] = 1'b0;                                                        // Counter 1 doesn't exist
-  assign CounterEvent[2] = InstrValidNotFlushedM;                                       // MINSTRET instructions retired
-  if(`QEMU) begin: cevent // No other performance counters in QEMU
-    assign CounterEvent[`COUNTERS-1:3] = 0;
-  end else begin: cevent                                                                // User-defined counters
-    assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
-    assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM;  // jump and not return instructions
-    assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
-  assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM;                            // branch predictor wrong
-    assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
-    assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM;                         // branch predictor wrong target
-    assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
-    assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                     // instruction class predictor wrong
-    assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM;                       // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[12] = StoreStallM & InstrValidNotFlushedM;                      //  Store Stall
-    assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM;                     // data cache access
-    assign CounterEvent[14] = DCacheMiss;                                               // data cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[15] = DCacheStallM;                                             // d cache miss cycles
-    assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM;                     // instruction cache access
-    assign CounterEvent[17] = ICacheMiss;                                               // instruction cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[18] = ICacheStallF;                                             // i cache miss cycles
-    assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                        // CSR writes
-    assign CounterEvent[20] = InvalidateICacheM & InstrValidNotFlushedM;                // fence.i
-    assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                       // sfence.vma
-    assign CounterEvent[22] = InterruptM;                                               // interrupt, InstrValidNotFlushedM will be low
-    assign CounterEvent[23] = ExceptionM;                                               // exceptions, InstrValidNotFlushedM will be low
+  assign CounterEvent[0]    = 1'b1;                                                      // MCYCLE always increments
+  assign CounterEvent[1]    = 1'b0;                                                      // Counter 1 doesn't exist
+  assign CounterEvent[2]    = InstrValidNotFlushedM;                                     // MINSTRET instructions retired
+  if (P.ZIHPM_SUPPORTED) begin: cevent                                                   // User-defined counters
+    assign CounterEvent[3]  = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
+    assign CounterEvent[4]  = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM;  // jump and not return instructions
+    assign CounterEvent[5]  = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
+    assign CounterEvent[6]  = BPWrongM & InstrValidNotFlushedM;                          // branch predictor wrong
+    assign CounterEvent[7]  = BPDirPredWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
+    assign CounterEvent[8]  = BTAWrongM & InstrValidNotFlushedM;                         // branch predictor wrong target
+    assign CounterEvent[9]  = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
+    assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
+    assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
+    assign CounterEvent[12] = StoreStallM;                                               //  Store Stall
+    assign CounterEvent[13] = DCacheAccess;                                              // data cache access
+    assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
+    assign CounterEvent[15] = DCacheStallM;                                              // d cache miss cycles
+    assign CounterEvent[16] = ICacheAccess;                                              // instruction cache access
+    assign CounterEvent[17] = ICacheMiss;                                                // instruction cache miss. Miss asserted 1 cycle at start of cache miss
+    assign CounterEvent[18] = ICacheStallF;                                              // i cache miss cycles
+    assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                         // CSR writes
+    assign CounterEvent[20] = InvalidateICacheM & InstrValidNotFlushedM;                 // fence.i
+    assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                        // sfence.vma
+    assign CounterEvent[22] = InterruptM;                                                // interrupt, InstrValidNotFlushedM will be low
+    assign CounterEvent[23] = ExceptionM;                                                // exceptions, InstrValidNotFlushedM will be low
     // coverage off
     // DivBusyE will never be assert high since this configuration uses the FPU to do integer division
-    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                     // division cycles *** RT: might need to be delay until the next cycle
+    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles *** RT: might need to be delay until the next cycle
     // coverage on
-    assign CounterEvent[`COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+    assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+  end else begin: cevent
+    assign CounterEvent[P.COUNTERS-1:3] = 0;
   end
   
   // Counter update and write logic
-  for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
+  for (i = 0; i < P.COUNTERS; i = i+1) begin:cntr
       assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
-      assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
+      assign NextHPMCOUNTERM[i][P.XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][P.XLEN-1:0];
       always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-        if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
-        else       HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
+        if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= #1 0;
+        else       HPMCOUNTER_REGW[i][P.XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
 
-      if (`XLEN==32) begin // write high and low separately
-        logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
-        logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
+      if (P.XLEN==32) begin // write high and low separately
+        logic [P.COUNTERS-1:0] WriteHPMCOUNTERHM;
+        logic [P.XLEN-1:0] NextHPMCOUNTERHM[P.COUNTERS-1:0];
         assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
         assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
         assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
         always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-            if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
-            else       HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
+            if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= #1 0;
+            else       HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
       end else begin // XLEN=64; write entire register
           assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
       end
@@ -149,35 +146,35 @@ module csrc #(parameter
   // Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
   assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
   always_comb 
-    if (PrivilegeModeW == `M_MODE | 
-        MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
+    if (PrivilegeModeW == P.M_MODE | 
+        MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
       IllegalCSRCAccessM = 0;
-      if (`XLEN==64) begin // 64-bit counter reads
+      if (P.XLEN==64) begin // 64-bit counter reads
         // Veri lator doesn't realize this only occurs for XLEN=64
         /* verilator lint_off WIDTH */  
         if      (CSRAdrM == TIME)  CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
         /* verilator lint_on WIDTH */  
-        else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS & CSRAdrM != MTIME) 
+        else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) 
                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-        else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM  < HPMCOUNTERBASE+`COUNTERS)  
+        else if (CSRAdrM >= HPMCOUNTERBASE  & CSRAdrM  < HPMCOUNTERBASE+P.COUNTERS)  
                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
         else begin
             CSRCReadValM = 0;
             IllegalCSRCAccessM = 1;  // requested CSR doesn't exist
         end
       end else begin // 32-bit counter reads
-        // Veri lator doesn't realize this only occurs for XLEN=32
+        // Veril ator doesn't realize this only occurs for XLEN=32
         /* verilator lint_off WIDTH */  
         if      (CSRAdrM == TIME)  CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
         else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
         /* verilator lint_on WIDTH */  
-        else if (CSRAdrM >= MHPMCOUNTERBASE  & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS & CSRAdrM != MTIME)   
+        else if (CSRAdrM >= MHPMCOUNTERBASE  & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)   
                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-        else if (CSRAdrM >= HPMCOUNTERBASE   & CSRAdrM < HPMCOUNTERBASE+`COUNTERS)    
+        else if (CSRAdrM >= HPMCOUNTERBASE   & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS)    
                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-        else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS & CSRAdrM != MTIMEH)  
+        else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH)  
                  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
-        else if (CSRAdrM >= HPMCOUNTERHBASE  & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS)   
+        else if (CSRAdrM >= HPMCOUNTERHBASE  & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS)   
                  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
         else begin
           CSRCReadValM = 0;
diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv
index 0a62b2174..2e5488af7 100644
--- a/src/privileged/csri.sv
+++ b/src/privileged/csri.sv
@@ -27,19 +27,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module csri #(parameter 
-  MIE = 12'h304,
-  MIP = 12'h344,
-  SIE = 12'h104,
-  SIP = 12'h144) (
+module csri import cvw::*;  #(parameter cvw_t P) (
   input  logic              clk, reset, 
   input  logic              CSRMWriteM, CSRSWriteM,
-  input  logic [`XLEN-1:0]  CSRWriteValM,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
   input  logic [11:0]       CSRAdrM,
   input  logic              MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
   input  logic [11:0]       MIDELEG_REGW,
+  input  logic              ENVCFG_STCE,
   output logic [11:0]       MIP_REGW, MIE_REGW,
   output logic [11:0]       MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
 );
@@ -48,6 +43,11 @@ module csri #(parameter
   logic                     WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
   logic                     STIP;
 
+  localparam MIE = 12'h304;
+  localparam MIP = 12'h344;
+  localparam SIE = 12'h104;
+  localparam SIP = 12'h144;
+
   // Interrupt Write Enables
   assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
   assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);
@@ -58,10 +58,10 @@ module csri #(parameter
   // MEIP, MTIP, MSIP are read-only
   // SEIP, STIP, SSIP is writable in MIP if S mode exists
   // SSIP is writable in SIP if S mode exists
-  if (`S_SUPPORTED) begin:mask
-    if (`SSTC_SUPPORTED) begin
+  if (P.S_SUPPORTED) begin:mask
+    if (P.SSTC_SUPPORTED) begin
       assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
-      assign STIP = STimerInt;
+      assign STIP = ENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
     end else begin
       assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
       assign STIP = MIP_REGW_writeable[5];
@@ -82,7 +82,6 @@ module csri #(parameter
     else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
     else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
 
-
   assign MIP_REGW = {MExtInt,   1'b0, SExtInt|MIP_REGW_writeable[9],  1'b0,
                      MTimerInt, 1'b0, STIP,                           1'b0,
                      MSwInt,    1'b0, MIP_REGW_writeable[1],          1'b0};
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
index f0e5f00db..a95ba8299 100644
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@@ -31,89 +31,90 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module csrm #(parameter 
-  // Machine CSRs
-  MVENDORID = 12'hF11,
-  MARCHID = 12'hF12,
-  MIMPID = 12'hF13,
-  MHARTID = 12'hF14,
-  MCONFIGPTR = 12'hF15,
-  MSTATUS = 12'h300,
-  MISA_ADR = 12'h301,
-  MEDELEG = 12'h302,
-  MIDELEG = 12'h303,
-  MIE = 12'h304,
-  MTVEC = 12'h305,
-  MCOUNTEREN = 12'h306,
-  MSTATUSH = 12'h310,
-  MCOUNTINHIBIT = 12'h320,
-  MSCRATCH = 12'h340,
-  MEPC = 12'h341,
-  MCAUSE = 12'h342,
-  MTVAL = 12'h343,
-  MIP = 12'h344,
-  MTINST = 12'h34A,
-  PMPCFG0 = 12'h3A0,
-  // .. up to 15 more at consecutive addresses
-  PMPADDR0 = 12'h3B0,
-  // ... up to 63 more at consecutive addresses
-  TSELECT = 12'h7A0,
-  TDATA1 = 12'h7A1,
-  TDATA2 = 12'h7A2,
-  TDATA3 = 12'h7A3,
-  DCSR = 12'h7B0,
-  DPC = 12'h7B1,
-  DSCRATCH0 = 12'h7B2,
-  DSCRATCH1 = 12'h7B3,
-  // Constants
-  ZERO = {(`XLEN){1'b0}},
-  MEDELEG_MASK = 16'hB3FF,
-  MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
-) (
-  input  logic                    clk, reset, 
-  input  logic                    UngatedCSRMWriteM, CSRMWriteM, MTrapM,
-  input  logic [11:0]             CSRAdrM,
-  input  logic [`XLEN-1:0]        NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
-  input  logic [4:0]              NextCauseM,
-  input  logic [`XLEN-1:0]        CSRWriteValM,
-  input  logic [11:0]             MIP_REGW, MIE_REGW,
-  output logic [`XLEN-1:0]        CSRMReadValM, MTVEC_REGW,
-  output logic [`XLEN-1:0]        MEPC_REGW,    
-  output logic [31:0]             MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-  output logic [15:0]             MEDELEG_REGW,
-  output logic [11:0]             MIDELEG_REGW,
-  output var logic [7:0]          PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
-  output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
-  output logic                    WriteMSTATUSM, WriteMSTATUSHM,
-  output logic                    IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
+module csrm  import cvw::*;  #(parameter cvw_t P) (
+  input  logic                     clk, reset, 
+  input  logic                     UngatedCSRMWriteM, CSRMWriteM, MTrapM,
+  input  logic [11:0]              CSRAdrM,
+  input  logic [P.XLEN-1:0]        NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
+  input  logic [4:0]               NextCauseM,
+  input  logic [P.XLEN-1:0]        CSRWriteValM,
+  input  logic [11:0]              MIP_REGW, MIE_REGW,
+  output logic [P.XLEN-1:0]        CSRMReadValM, MTVEC_REGW,
+  output logic [P.XLEN-1:0]        MEPC_REGW,    
+  output logic [31:0]              MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
+  output logic [15:0]              MEDELEG_REGW,
+  output logic [11:0]              MIDELEG_REGW,
+  output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
+  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
+  output logic                     WriteMSTATUSM, WriteMSTATUSHM,
+  output logic                     IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
+  output logic [63:0]              MENVCFG_REGW
 );
 
-  logic [`XLEN-1:0]               MISA_REGW, MHARTID_REGW;
-  logic [`XLEN-1:0]               MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
-  logic                           WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
-  logic                           WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
-  logic                           WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
+  logic [P.XLEN-1:0]               MISA_REGW, MHARTID_REGW;
+  logic [P.XLEN-1:0]               MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
+  logic [P.XLEN-1:0]               MENVCFGH_REGW;
+  logic                            WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
+  logic                            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
+  logic                            WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
+
+  // Machine CSRs
+  localparam MVENDORID     = 12'hF11;
+  localparam MARCHID       = 12'hF12;
+  localparam MIMPID        = 12'hF13;
+  localparam MHARTID       = 12'hF14;
+  localparam MCONFIGPTR    = 12'hF15;
+  localparam MSTATUS       = 12'h300;
+  localparam MISA_ADR      = 12'h301;
+  localparam MEDELEG       = 12'h302;
+  localparam MIDELEG       = 12'h303;
+  localparam MIE           = 12'h304;
+  localparam MTVEC         = 12'h305;
+  localparam MCOUNTEREN    = 12'h306;
+  localparam MENVCFG       = 12'h30A;
+  localparam MSTATUSH      = 12'h310;
+  localparam MENVCFGH      = 12'h31A;
+  localparam MCOUNTINHIBIT = 12'h320;
+  localparam MSCRATCH      = 12'h340;
+  localparam MEPC          = 12'h341;
+  localparam MCAUSE        = 12'h342;
+  localparam MTVAL         = 12'h343;
+  localparam MIP           = 12'h344;
+  localparam PMPCFG0       = 12'h3A0;
+  // .. up to 15 more at consecutive addresses
+  localparam PMPADDR0      = 12'h3B0;
+  // ... up to 63 more at consecutive addresses
+  localparam TSELECT       = 12'h7A0;
+  localparam TDATA1        = 12'h7A1;
+  localparam TDATA2        = 12'h7A2;
+  localparam TDATA3        = 12'h7A3;
+  localparam DCSR          = 12'h7B0;
+  localparam DPC           = 12'h7B1;
+  localparam DSCRATCH0     = 12'h7B2;
+  localparam DSCRATCH1     = 12'h7B3;
+  // Constants
+  localparam ZERO = {(P.XLEN){1'b0}};
+  localparam MEDELEG_MASK  = 16'hB3FF;
+  localparam MIDELEG_MASK  = 12'h222; // we choose to not make machine interrupts delegable
 
  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
   genvar i;
-  if (`PMP_ENTRIES > 0) begin:pmp
-    logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
-    logic [`PMP_ENTRIES-1:0] WritePMPADDRM ; 
-    logic [`PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
-    for(i=0; i<`PMP_ENTRIES; i++) begin
+  if (P.PMP_ENTRIES > 0) begin:pmp
+    logic [P.PMP_ENTRIES-1:0] WritePMPCFGM;
+    logic [P.PMP_ENTRIES-1:0] WritePMPADDRM ; 
+    logic [P.PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
+    for(i=0; i<P.PMP_ENTRIES; i++) begin
       // when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
       // also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
       assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
-      if (i == `PMP_ENTRIES-1) 
+      if (i == P.PMP_ENTRIES-1) 
         assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
       else
         assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
       
       assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~ADDRLocked[i];
-      flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]);
-      if (`XLEN==64) begin
+      flopenr #(P.PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[P.PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]);
+      if (P.XLEN==64) begin
         assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~CFGLocked[i];
         flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
       end else begin
@@ -123,56 +124,87 @@ module csrm #(parameter
     end
   end
 
-  localparam MISA_26 = (`MISA) & 32'h03ffffff;
+  localparam MISA_26 = (P.MISA) & 32'h03ffffff;
 
   // MISA is hardwired.  Spec says it could be written to disable features, but this is not supported by Wally
-  assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
+  assign MISA_REGW = {(P.XLEN == 32 ? 2'b01 : 2'b10), {(P.XLEN-28){1'b0}}, MISA_26[25:0]};
 
   // MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
   assign MHARTID_REGW = 0;
 
   // Write machine Mode CSRs 
-  assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS);
-  assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH)& (`XLEN==32);
-  assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC);
-  assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG);
-  assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG);
-  assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH);
-  assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC));
-  assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
-  assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
-  assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
+  assign WriteMSTATUSM       = CSRMWriteM & (CSRAdrM == MSTATUS);
+  assign WriteMSTATUSHM      = CSRMWriteM & (CSRAdrM == MSTATUSH) & (P.XLEN==32);
+  assign WriteMTVECM         = CSRMWriteM & (CSRAdrM == MTVEC);
+  assign WriteMEDELEGM       = CSRMWriteM & (CSRAdrM == MEDELEG);
+  assign WriteMIDELEGM       = CSRMWriteM & (CSRAdrM == MIDELEG);
+  assign WriteMSCRATCHM      = CSRMWriteM & (CSRAdrM == MSCRATCH);
+  assign WriteMEPCM          = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC));
+  assign WriteMCAUSEM        = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
+  assign WriteMTVALM         = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
+  assign WriteMCOUNTERENM    = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
   assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
 
   assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
 
   // CSRs
-  flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); 
-  if (`S_SUPPORTED) begin:deleg // DELEG registers should exist
+  flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); 
+  if (P.S_SUPPORTED) begin:deleg // DELEG registers should exist
     flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW);
     flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW);
   end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
 
-  flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
-  flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
-  flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
-  if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration
-  else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
+  flopenr #(P.XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
+  flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
+  flopenr #(P.XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
+  if(P.QEMU) assign MTVAL_REGW = '0; // MTVAL tied to 0 in QEMU configuration
+  else flopenr #(P.XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
   flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
-  if (`U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
+  if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
     flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
   end else assign MCOUNTEREN_REGW = '0;
 
+  // MENVCFG register
+  if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
+    logic WriteMENVCFGM;
+    logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
+    assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
+    // MENVCFG is always 64 bits even for RV32
+    assign MENVCFG_WriteValM = {
+      MENVCFG_PreWriteValM[63]  & P.SSTC_SUPPORTED,
+      MENVCFG_PreWriteValM[62]  & P.SVPBMT_SUPPORTED,
+      54'b0,
+      MENVCFG_PreWriteValM[7]   & P.ZICBOZ_SUPPORTED,
+      MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
+      3'b0,
+      MENVCFG_PreWriteValM[0]   & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
+    };
+    if (P.XLEN == 64) begin
+      assign MENVCFG_PreWriteValM = CSRWriteValM;
+      flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
+      assign MENVCFGH_REGW = 0;
+    end else begin // RV32 has high and low halves
+      logic WriteMENVCFGHM;
+      assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
+      assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
+      flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]);
+      flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
+      assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
+    end
+  end
+
   // Read machine mode CSRs
   // verilator lint_off WIDTH
   logic [5:0] entry;
   always_comb begin
     entry = '0;
-    IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
-    if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
-      CSRMReadValM = {{(`XLEN-(`PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
-    else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
-      if (`XLEN==64) begin
+    CSRMReadValM = 0;
+    IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
+    if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry
+      CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
+    else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + P.PMP_ENTRIES/4 & (P.XLEN==32 | CSRAdrM[0] == 0)) begin
+      // only odd-numbered PMPCFG entries exist in RV64
+      if (P.XLEN==64) begin
         entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
         CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],
                         PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
@@ -182,32 +214,32 @@ module csrm #(parameter
       end
     end
     else case (CSRAdrM) 
-      MISA_ADR:  CSRMReadValM = MISA_REGW;
-      MVENDORID: CSRMReadValM = 0;
-      MARCHID:   CSRMReadValM = 0;
-      MIMPID:    CSRMReadValM = `XLEN'h100; // pipelined implementation
-      MHARTID:   CSRMReadValM = MHARTID_REGW; // hardwired to 0 
-      MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0
-      MSTATUS:   CSRMReadValM = MSTATUS_REGW;
-      MSTATUSH:  CSRMReadValM = MSTATUSH_REGW; 
-      MTVEC:     CSRMReadValM = MTVEC_REGW;
-      MEDELEG:   CSRMReadValM = {{(`XLEN-16){1'b0}}, MEDELEG_REGW};
-      MIDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
-      MIP:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
-      MIE:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
-      MSCRATCH:  CSRMReadValM = MSCRATCH_REGW;
-      MEPC:      CSRMReadValM = MEPC_REGW;
-      MCAUSE:    CSRMReadValM = MCAUSE_REGW;
-      MTVAL:     CSRMReadValM = MTVAL_REGW;
-      MTINST:    CSRMReadValM = 0; // implemented as trivial zero
-      MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
-      MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
-
-      default: begin
-                 CSRMReadValM = 0;
-                 IllegalCSRMAccessM = 1;
-      end
+      MISA_ADR:      CSRMReadValM = MISA_REGW;
+      MVENDORID:     CSRMReadValM = 0;
+      MARCHID:       CSRMReadValM = 0;
+      MIMPID:        CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
+      MHARTID:       CSRMReadValM = MHARTID_REGW; // hardwired to 0 
+      MCONFIGPTR:    CSRMReadValM = 0; // hardwired to 0
+      MSTATUS:       CSRMReadValM = MSTATUS_REGW;
+      MSTATUSH:      if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; 
+                     else IllegalCSRMAccessM = 1;
+      MTVEC:         CSRMReadValM = MTVEC_REGW;
+      MEDELEG:       CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW};
+      MIDELEG:       CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW};
+      MIP:           CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIP_REGW};
+      MIE:           CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIE_REGW};
+      MSCRATCH:      CSRMReadValM = MSCRATCH_REGW;
+      MEPC:          CSRMReadValM = MEPC_REGW;
+      MCAUSE:        CSRMReadValM = MCAUSE_REGW;
+      MTVAL:         CSRMReadValM = MTVAL_REGW;
+      MCOUNTEREN:    CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
+      MENVCFG:       if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
+                     else IllegalCSRMAccessM = 1;
+      MENVCFGH:      if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
+                     else IllegalCSRMAccessM = 1;
+      MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
+      default:       IllegalCSRMAccessM = 1;
     endcase
   end
   // verilator lint_on WIDTH
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index e085232a6..84a4d0a4b 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -28,91 +28,108 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+module csrs import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset, 
+  input  logic              CSRSWriteM, STrapM,
+  input  logic [11:0]       CSRAdrM,
+  input  logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, 
+  input  logic [4:0]        NextCauseM,
+  input  logic              STATUS_TVM,
+  input  logic              MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
+  input  logic [P.XLEN-1:0] CSRWriteValM,
+  input  logic [1:0]        PrivilegeModeW,
+  output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
+  output logic [P.XLEN-1:0] SEPC_REGW,      
+  output logic [31:0]       SCOUNTEREN_REGW, 
+  output logic [P.XLEN-1:0] SATP_REGW,
+  input  logic [11:0]       MIP_REGW, MIE_REGW, MIDELEG_REGW,
+  input  logic [63:0]       MTIME_CLINT,
+  input  logic              STCE,
+  output logic              WriteSSTATUSM,
+  output logic              IllegalCSRSAccessM,
+  output logic              STimerInt,
+  output logic [P.XLEN-1:0] SENVCFG_REGW
 
-module csrs #(parameter 
-  // Supervisor CSRs
-  SSTATUS = 12'h100,
-  SIE = 12'h104,
-  STVEC = 12'h105,
-  SCOUNTEREN = 12'h106,
-  SSCRATCH = 12'h140,
-  SEPC = 12'h141,
-  SCAUSE = 12'h142,
-  STVAL = 12'h143,
-  SIP= 12'h144,
-  STIMECMP = 12'h14D,
-  STIMECMPH = 12'h15D,
-  SATP = 12'h180) (
-  input  logic             clk, reset, 
-  input  logic             CSRSWriteM, STrapM,
-  input  logic [11:0]      CSRAdrM,
-  input  logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, 
-  input  logic [4:0]       NextCauseM,
-  input  logic             STATUS_TVM,
-  input  logic             MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
-  input  logic [`XLEN-1:0] CSRWriteValM,
-  input  logic [1:0]       PrivilegeModeW,
-  output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
-  output logic [`XLEN-1:0] SEPC_REGW,      
-  output logic [31:0]      SCOUNTEREN_REGW, 
-  output logic [`XLEN-1:0] SATP_REGW,
-  input  logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
-  input  logic [63:0]      MTIME_CLINT,
-  output logic             WriteSSTATUSM,
-  output logic             IllegalCSRSAccessM,
-  output logic             STimerInt
 );
 
+  // Supervisor CSRs
+  localparam SSTATUS    = 12'h100;
+  localparam SIE        = 12'h104;
+  localparam STVEC      = 12'h105;
+  localparam SCOUNTEREN = 12'h106;
+  localparam SENVCFG    = 12'h10A;
+  localparam SSCRATCH   = 12'h140;
+  localparam SEPC       = 12'h141;
+  localparam SCAUSE     = 12'h142;
+  localparam STVAL      = 12'h143;
+  localparam SIP        = 12'h144;
+  localparam STIMECMP   = 12'h14D;
+  localparam STIMECMPH  = 12'h15D;
+  localparam SATP       = 12'h180;
   // Constants
-  localparam ZERO = {(`XLEN){1'b0}};
-  localparam SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9);
+  localparam ZERO         = {(P.XLEN){1'b0}};
+  localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
 
   logic                    WriteSTVECM;
   logic                    WriteSSCRATCHM, WriteSEPCM;
   logic                    WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
   logic                    WriteSTIMECMPM, WriteSTIMECMPHM;
-  logic [`XLEN-1:0]        SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
+  logic                    WriteSENVCFGM;
+
+  logic [P.XLEN-1:0]       SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
+  logic [P.XLEN-1:0]       SENVCFG_WriteValM;
+
   logic [63:0]             STIMECMP_REGW;
   
   // write enables
-  assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS);
-  assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC);
-  assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH);
-  assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
-  assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
-  assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
-  assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM);
+  assign WriteSSTATUSM    = CSRSWriteM & (CSRAdrM == SSTATUS);
+  assign WriteSTVECM      = CSRSWriteM & (CSRAdrM == STVEC);
+  assign WriteSSCRATCHM   = CSRSWriteM & (CSRAdrM == SSCRATCH);
+  assign WriteSEPCM       = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
+  assign WriteSCAUSEM     = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
+  assign WriteSTVALM      = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
+  assign WriteSATPM       = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
   assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
-  assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM);
-  assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & (`XLEN == 32);
+  assign WriteSENVCFGM    = CSRSWriteM & (CSRAdrM == SENVCFG);
+  assign WriteSTIMECMPM   = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE;
+  assign WriteSTIMECMPHM  = CSRSWriteM & (CSRAdrM == STIMECMPH) & STCE & (P.XLEN == 32);
 
   // CSRs
-  flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); 
-  flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
-  flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
-  flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW);
-  flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
-  if (`VIRTMEM_SUPPORTED)
-    flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
+  flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); 
+  flopenr #(P.XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
+  flopenr #(P.XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
+  flopenr #(P.XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW);
+  flopenr #(P.XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
+  if (P.VIRTMEM_SUPPORTED)
+    flopenr #(P.XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
   else
     assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
   flopenr #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
-  if (`SSTC_SUPPORTED) begin : sstc
-    if (`XLEN == 64) begin : sstc64
-      flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
+  if (P.SSTC_SUPPORTED) begin : sstc
+    if (P.XLEN == 64) begin : sstc64
+      flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
     end else begin : sstc32
-      flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
-      flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
+      flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
+      flopenl #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
     end
   end else assign STIMECMP_REGW = 0;
 
   // Supervisor timer interrupt logic
   // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs
-  if (`SSTC_SUPPORTED)
-   assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
+  if (P.SSTC_SUPPORTED)
+   assign STimerInt  = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
   else 
     assign STimerInt = 0;
+
+  assign SENVCFG_WriteValM = {
+    {(P.XLEN-8){1'b0}},
+    CSRWriteValM[7]   & P.ZICBOZ_SUPPORTED,
+    CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
+    3'b0,
+    CSRWriteValM[0]   & P.VIRTMEM_SUPPORTED
+  };
+
+  flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW);
     
   // CSR Reads
   always_comb begin:csrr
@@ -120,24 +137,27 @@ module csrs #(parameter
     case (CSRAdrM) 
       SSTATUS:   CSRSReadValM = SSTATUS_REGW;
       STVEC:     CSRSReadValM = STVEC_REGW;
-      SIP:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  
-      SIE:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
+      SIP:       CSRSReadValM = {{(P.XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  
+      SIE:       CSRSReadValM = {{(P.XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
       SSCRATCH:  CSRSReadValM = SSCRATCH_REGW;
       SEPC:      CSRSReadValM = SEPC_REGW;
       SCAUSE:    CSRSReadValM = SCAUSE_REGW;
       STVAL:     CSRSReadValM = STVAL_REGW;
-      SATP:      if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
+      SATP:      if (P.VIRTMEM_SUPPORTED & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
                  else begin
                    CSRSReadValM = 0;
                    IllegalCSRSAccessM = 1;
                  end
-      SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW};
-      STIMECMP:  if (`SSTC_SUPPORTED & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[`XLEN-1:0]; 
+      SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
+      SENVCFG:   CSRSReadValM = SENVCFG_REGW;
+      STIMECMP:  if (STCE) 
+                   CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; 
                  else begin 
                    CSRSReadValM = 0;
                    IllegalCSRSAccessM = 1;
                  end
-      STIMECMPH: if (`SSTC_SUPPORTED & (`XLEN == 32) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM)) CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
+      STIMECMPH: if (STCE) 
+                   CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
                  else begin // not supported for RV64
                    CSRSReadValM = 0;
                    IllegalCSRSAccessM = 1;
@@ -148,4 +168,4 @@ module csrs #(parameter
                end       
     endcase
   end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index 60968a68b..f474627f8 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: Status register
+// Purpose: Status register (and environment configuration register and others shared across modes)
 //          See RISC-V Privileged Mode Specification 20190608 
 // 
 // Documentation: RISC-V System on Chip Design Chapter 5
@@ -27,25 +27,23 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module csrsr (
-  input  logic             clk, reset, StallW,
-  input  logic             WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM, 
-  input  logic             TrapM, FRegWriteM,
-  input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
-  input  logic             mretM, sretM, 
-  input  logic             WriteFRMM, WriteFFLAGSM,
-  input  logic [`XLEN-1:0] CSRWriteValM,
-  input  logic             SelHPTW,
-  output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
-  output logic [1:0]       STATUS_MPP,
-  output logic             STATUS_SPP, STATUS_TSR, STATUS_TW,
-  output logic             STATUS_MIE, STATUS_SIE,
-  output logic             STATUS_MXR, STATUS_SUM,
-  output logic             STATUS_MPRV, STATUS_TVM,
-  output logic [1:0]       STATUS_FS,
-  output logic             BigEndianM
+module csrsr import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset, StallW,
+  input  logic              WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM, 
+  input  logic              TrapM, FRegWriteM,
+  input  logic [1:0]        NextPrivilegeModeM, PrivilegeModeW,
+  input  logic              mretM, sretM, 
+  input  logic              WriteFRMM, WriteFFLAGSM,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
+  input  logic              SelHPTW,
+  output logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
+  output logic [1:0]        STATUS_MPP,
+  output logic              STATUS_SPP, STATUS_TSR, STATUS_TW,
+  output logic              STATUS_MIE, STATUS_SIE,
+  output logic              STATUS_MXR, STATUS_SUM,
+  output logic              STATUS_MPRV, STATUS_TVM,
+  output logic [1:0]        STATUS_FS,
+  output logic              BigEndianM
 );
   
   logic STATUS_SD, STATUS_TW_INT, STATUS_TSR_INT, STATUS_TVM_INT, STATUS_MXR_INT, STATUS_SUM_INT, STATUS_MPRV_INT;
@@ -56,79 +54,81 @@ module csrsr (
   // STATUS REGISTER FIELD
   // See Privileged Spec Section 3.1.6
   // Lower privilege status registers are a subset of the full status register
-  // *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable
-  if (`XLEN==64) begin: csrsr64 // RV64
-    assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
-                          STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-                          STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
-                          STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0,
-                          STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
-    assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {`QEMU ? 2'b0 : STATUS_UXL}, /*9'b0, */ 12'b0,
+  if (P.XLEN==64) begin: csrsr64 // RV64
+    assign MSTATUS_REGW  = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
+                           STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+                           STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
+                           STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0,
+                           STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
+    assign SSTATUS_REGW  = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {P.QEMU ? 2'b0 : STATUS_UXL}, /*9'b0, */ 12'b0,
                           /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
-                          STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
-                          STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
+                           STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
+                           STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
                           /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
     assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value.  Spec is not clear what it should be.
   end else begin: csrsr32 // RV32
-    assign MSTATUS_REGW = {STATUS_SD, 8'b0,
-                          STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-                          STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
-                          STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0, STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
+    assign MSTATUS_REGW  = {STATUS_SD, 8'b0,
+                           STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+                           STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
+                           STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0, STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
     assign MSTATUSH_REGW = {26'b0, STATUS_MBE, STATUS_SBE, 4'b0}; 
-    assign SSTATUS_REGW = {STATUS_SD, 11'b0,
+    assign SSTATUS_REGW  = {STATUS_SD, 11'b0,
                           /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
-                          STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
-                          STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
+                           STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
+                           STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
                           /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
   end
 
   // extract values to write to upper status register on 64/32-bit access
-  if (`XLEN==64) begin:upperstatus
-    assign nextMBE = CSRWriteValM[37] & `BIGENDIAN_SUPPORTED;
-    assign nextSBE = CSRWriteValM[36] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
+  if (P.XLEN==64) begin:upperstatus
+    assign nextMBE = CSRWriteValM[37] & P.BIGENDIAN_SUPPORTED;
+    assign nextSBE = CSRWriteValM[36] & P.S_SUPPORTED & P.BIGENDIAN_SUPPORTED;
   end else begin:upperstatus
     assign nextMBE = STATUS_MBE;
     assign nextSBE = STATUS_SBE;
   end
 
   // harwired STATUS bits
-  assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
-  assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
-/*  assign STATUS_UBE = 0; // little-endian
-  assign STATUS_SBE = 0; // little-endian
-  assign STATUS_MBE = 0; // little-endian */
+  assign STATUS_TSR  = P.S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_TW   = (P.S_SUPPORTED | P.U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
+  assign STATUS_TVM  = P.S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_MXR  = P.S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
+/* assign STATUS_UBE = 0; // little-endian
+  assign STATUS_SBE  = 0; // little-endian
+  assign STATUS_MBE  = 0; // little-endian */
   // SXL and UXL bits only matter for RV64.  Set to 10 for RV64 if mode is supported, or 0 if not
-  assign STATUS_SXL = `S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
-  assign STATUS_UXL = `U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
-  assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
-  assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP  
-  assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
-  assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty
+  assign STATUS_SXL  = P.S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
+  assign STATUS_UXL  = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
+  assign STATUS_SUM  = P.S_SUPPORTED & P.VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_MPRV = P.U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
+  assign STATUS_FS   = (P.S_SUPPORTED & (P.F_SUPPORTED | P.D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP  
+  assign STATUS_SD   = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
+  assign STATUS_XS   = 2'b00; // No additional user-mode state to be dirty
 
   always_comb
-    if      (CSRWriteValM[12:11] == `U_MODE & `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
-    else if (CSRWriteValM[12:11] == `S_MODE & `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
-    else                                                    STATUS_MPP_NEXT = `M_MODE;
+    if      (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
+    else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
+    else                                                    STATUS_MPP_NEXT = P.M_MODE;
 
   ///////////////////////////////////////////
   // Endianness logic Privileged Spec 3.1.6.4
   ///////////////////////////////////////////
 
-  if (`BIGENDIAN_SUPPORTED) begin: endianmux
+  if (P.BIGENDIAN_SUPPORTED) begin: endianmux
     // determine whether big endian accesses should be made
     logic [1:0] EndiannessPrivMode;
     always_comb begin
-      if      (SelHPTW)                                  EndiannessPrivMode = `S_MODE;
-      else if (PrivilegeModeW == `M_MODE & STATUS_MPRV)  EndiannessPrivMode = STATUS_MPP;
+      if      (SelHPTW)                                  EndiannessPrivMode = P.S_MODE;
+      //coverage off -item c 1 -feccondrow 1
+      // status.MPRV always gets reset upon leaving machine mode, so MPRV will never be high when out of machine mode
+      else if (PrivilegeModeW == P.M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP;
+      //coverage on
       else                                               EndiannessPrivMode = PrivilegeModeW;
 
       case (EndiannessPrivMode) 
-        `M_MODE: BigEndianM = STATUS_MBE;
-        `S_MODE: BigEndianM = STATUS_SBE;
-        default: BigEndianM = STATUS_UBE;
+        P.M_MODE: BigEndianM = STATUS_MBE;
+        P.S_MODE: BigEndianM = STATUS_SBE;
+        default: BigEndianM  = STATUS_UBE;
       endcase
     end
   end else begin: endianmux
@@ -139,79 +139,78 @@ module csrsr (
   // complex register with reset, write enable, and the ability to update other bits in certain cases
   always_ff @(posedge clk) //, posedge reset)
     if (reset) begin
-      STATUS_TSR_INT <= #1 0;
-      STATUS_TW_INT <= #1 0;
-      STATUS_TVM_INT <= #1 0;
-      STATUS_MXR_INT <= #1 0;
-      STATUS_SUM_INT <= #1 0;
+      STATUS_TSR_INT  <= #1 0;
+      STATUS_TW_INT   <= #1 0;
+      STATUS_TVM_INT  <= #1 0;
+      STATUS_MXR_INT  <= #1 0;
+      STATUS_SUM_INT  <= #1 0;
       STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
-      STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
-      STATUS_MPP <= #1 0; 
-      STATUS_SPP <= #1 0; 
-      STATUS_MPIE <= #1 0; 
-      STATUS_SPIE <= #1 0; 
-      STATUS_MIE <= #1 0; 
-      STATUS_SIE <= #1 0; 
-      STATUS_MBE <= #1 0;
-      STATUS_SBE <= #1 0;
-      STATUS_UBE <= #1 0;
+      STATUS_FS_INT   <= #1 P.F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
+      STATUS_MPP      <= #1 0; 
+      STATUS_SPP      <= #1 0; 
+      STATUS_MPIE     <= #1 0; 
+      STATUS_SPIE     <= #1 0; 
+      STATUS_MIE      <= #1 0; 
+      STATUS_SIE      <= #1 0; 
+      STATUS_MBE      <= #1 0;
+      STATUS_SBE      <= #1 0;
+      STATUS_UBE      <= #1 0;
     end else if (~StallW) begin
       if (TrapM) begin
         // Update interrupt enables per Privileged Spec p. 21
         // y = PrivilegeModeW
         // x = NextPrivilegeModeM
         // Modes: 11 = Machine, 01 = Supervisor, 00 = User
-        if (NextPrivilegeModeM == `M_MODE) begin
+        if (NextPrivilegeModeM == P.M_MODE) begin
           STATUS_MPIE <= #1 STATUS_MIE;
-          STATUS_MIE <= #1 0;
-          STATUS_MPP <= #1 PrivilegeModeW;
+          STATUS_MIE  <= #1 0;
+          STATUS_MPP  <= #1 PrivilegeModeW;
         end else begin // supervisor mode
           STATUS_SPIE <= #1 STATUS_SIE;
-          STATUS_SIE <= #1 0;
-          STATUS_SPP <= #1 PrivilegeModeW[0];
+          STATUS_SIE  <= #1 0;
+          STATUS_SPP  <= #1 PrivilegeModeW[0];
        end
       end else if (mretM) begin // Privileged 3.1.6.1
-        STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable
-        STATUS_MPIE <= #1 1; // 
-        STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level
-        // STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU
-        STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec.
+        STATUS_MIE      <= #1 STATUS_MPIE; // restore global interrupt enable
+        STATUS_MPIE     <= #1 1; // 
+        STATUS_MPP      <= #1 P.U_SUPPORTED ? P.U_MODE : P.M_MODE; // set MPP to lowest supported privilege level
+        STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == P.M_MODE); // page 21 of privileged spec.
       end else if (sretM) begin
-        STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable
-        STATUS_SPIE <= #1 `S_SUPPORTED; 
-        STATUS_SPP <= #1 0; // set SPP to lowest supported privilege level to catch bugs
+        STATUS_SIE      <= #1 STATUS_SPIE; // restore global interrupt enable
+        STATUS_SPIE     <= #1 P.S_SUPPORTED; 
+        STATUS_SPP      <= #1 0; // set SPP to lowest supported privilege level to catch bugs
         STATUS_MPRV_INT <= #1 0; // always clear MPRV
       end else if (WriteMSTATUSM) begin
-        STATUS_TSR_INT <= #1 CSRWriteValM[22];
-        STATUS_TW_INT <= #1 CSRWriteValM[21];
-        STATUS_TVM_INT <= #1 CSRWriteValM[20];
-        STATUS_MXR_INT <= #1 CSRWriteValM[19];
-        STATUS_SUM_INT <= #1 CSRWriteValM[18];
+        STATUS_TSR_INT  <= #1 CSRWriteValM[22];
+        STATUS_TW_INT   <= #1 CSRWriteValM[21];
+        STATUS_TVM_INT  <= #1 CSRWriteValM[20];
+        STATUS_MXR_INT  <= #1 CSRWriteValM[19];
+        STATUS_SUM_INT  <= #1 CSRWriteValM[18];
         STATUS_MPRV_INT <= #1 CSRWriteValM[17];
-        STATUS_FS_INT <= #1 CSRWriteValM[14:13];
-        STATUS_MPP <= #1 STATUS_MPP_NEXT;
-        STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
-        STATUS_MPIE <= #1 CSRWriteValM[7];
-        STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
-        STATUS_MIE <= #1 CSRWriteValM[3];
-        STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
-        STATUS_UBE <= #1 CSRWriteValM[6]  & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
-        STATUS_MBE <= #1 nextMBE;
-        STATUS_SBE <= #1 nextSBE;
+        STATUS_FS_INT   <= #1 CSRWriteValM[14:13];
+        STATUS_MPP      <= #1 STATUS_MPP_NEXT;
+        STATUS_SPP      <= #1 P.S_SUPPORTED & CSRWriteValM[8];
+        STATUS_MPIE     <= #1 CSRWriteValM[7];
+        STATUS_SPIE     <= #1 P.S_SUPPORTED & CSRWriteValM[5];
+        STATUS_MIE      <= #1 CSRWriteValM[3];
+        STATUS_SIE      <= #1 P.S_SUPPORTED & CSRWriteValM[1];
+        STATUS_UBE      <= #1 CSRWriteValM[6]  & P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED;
+        STATUS_MBE      <= #1 nextMBE;
+        STATUS_SBE      <= #1 nextSBE;
       // coverage off
       // MSTATUSH only exists in 32-bit configurations, will not be hit on rv64gc
       end else if (WriteMSTATUSHM) begin
-        STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED;
-        STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
+        STATUS_MBE      <= #1 CSRWriteValM[5] & P.BIGENDIAN_SUPPORTED;
+        STATUS_SBE      <= #1 CSRWriteValM[4] & P.S_SUPPORTED & P.BIGENDIAN_SUPPORTED;
       // coverage on
       end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
-        STATUS_MXR_INT <= #1 CSRWriteValM[19];
-        STATUS_SUM_INT <= #1 CSRWriteValM[18];
-        STATUS_FS_INT <= #1 CSRWriteValM[14:13];
-        STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
-        STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
-        STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
-        STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
+        STATUS_MXR_INT  <= #1 CSRWriteValM[19];
+        STATUS_SUM_INT  <= #1 CSRWriteValM[18];
+        STATUS_FS_INT   <= #1 CSRWriteValM[14:13];
+        STATUS_SPP      <= #1 P.S_SUPPORTED & CSRWriteValM[8];
+        STATUS_SPIE     <= #1 P.S_SUPPORTED & CSRWriteValM[5];
+        STATUS_SIE      <= #1 P.S_SUPPORTED & CSRWriteValM[1];
+        STATUS_UBE      <= #1 CSRWriteValM[6] & P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED;
       end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; 
     end
 endmodule
diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv
index e474e5967..3a0f8c909 100644
--- a/src/privileged/csru.sv
+++ b/src/privileged/csru.sv
@@ -26,42 +26,41 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module csru #(parameter 
-  FFLAGS = 12'h001,
-  FRM = 12'h002,
-  FCSR = 12'h003) (
-  input  logic             clk, reset, 
-  input  logic             InstrValidNotFlushedM,
-  input  logic             CSRUWriteM,
-  input  logic [11:0]      CSRAdrM,
-  input  logic [`XLEN-1:0] CSRWriteValM,
-  input  logic [1:0]       STATUS_FS,
-  output logic [`XLEN-1:0] CSRUReadValM,  
-  input  logic [4:0]       SetFflagsM,
-  output logic [2:0]       FRM_REGW,
-  output logic             WriteFRMM, WriteFFLAGSM,
-  output logic             IllegalCSRUAccessM
+module csru import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset, 
+  input  logic              InstrValidNotFlushedM,
+  input  logic              CSRUWriteM,
+  input  logic [11:0]       CSRAdrM,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
+  input  logic [1:0]        STATUS_FS,
+  output logic [P.XLEN-1:0] CSRUReadValM,  
+  input  logic [4:0]        SetFflagsM,
+  output logic [2:0]        FRM_REGW,
+  output logic              WriteFRMM, WriteFFLAGSM,
+  output logic              IllegalCSRUAccessM
 );
 
-  logic [4:0]              FFLAGS_REGW;
-  logic [2:0]              NextFRMM;
-  logic [4:0]              NextFFLAGSM;
-  logic                    SetOrWriteFFLAGSM;
+  localparam FFLAGS = 12'h001;
+  localparam FRM    = 12'h002;
+  localparam FCSR   = 12'h003;
+
+  logic [4:0]               FFLAGS_REGW;
+  logic [2:0]               NextFRMM;
+  logic [4:0]               NextFFLAGSM;
+  logic                     SetOrWriteFFLAGSM;
   
   // Write enables
-  assign WriteFRMM =    CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
+  assign WriteFRMM    = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
   assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);
 
   // Write Values
-  assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
-  assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
+  assign NextFRMM          = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
+  assign NextFFLAGSM       = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
   assign SetOrWriteFFLAGSM = WriteFFLAGSM | (|SetFflagsM & InstrValidNotFlushedM);
 
   // CSRs
   flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW);
-  flopenr   #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW); 
+  flopenr #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW); 
 
   // CSR Reads
   always_comb begin
@@ -71,9 +70,9 @@ module csru #(parameter
     end else begin
       IllegalCSRUAccessM = 0;
       case (CSRAdrM) 
-        FFLAGS:    CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW};
-        FRM:       CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW};
-        FCSR:      CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
+        FFLAGS:    CSRUReadValM = {{(P.XLEN-5){1'b0}}, FFLAGS_REGW};
+        FRM:       CSRUReadValM = {{(P.XLEN-3){1'b0}}, FRM_REGW};
+        FCSR:      CSRUReadValM = {{(P.XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
         default: begin
                    CSRUReadValM = 0; 
                    IllegalCSRUAccessM = 1;
diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv
index 21239dc95..a0195f366 100644
--- a/src/privileged/privdec.sv
+++ b/src/privileged/privdec.sv
@@ -27,12 +27,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module privdec (
+module privdec import cvw::*;  #(parameter cvw_t P) (
   input  logic         clk, reset,
   input  logic         StallM,
-  input  logic [31:20] InstrM,                              // privileged instruction function field
+  input  logic [31:15] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
   input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction
   input  logic         IllegalCSRAccessM,                   // Not a legal CSR access
@@ -41,35 +39,51 @@ module privdec (
   output logic         IllegalInstrFaultM,                  // Illegal instruction
   output logic         EcallFaultM, BreakpointFaultM,       // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
   output logic         sretM, mretM,                        // return instructions
-  output logic         wfiM, sfencevmaM                     // wfi / sfence.fma instructions
+  output logic         wfiM, sfencevmaM                     // wfi / sfence.vma / sinval.vma instructions
 );
 
+  logic                rs1zeroM;                            // rs1 field = 0
   logic                IllegalPrivilegedInstrM;             // privileged instruction isn't a legal one or in legal mode
   logic                WFITimeoutM;                         // WFI reaches timeout threshold
   logic                ebreakM, ecallM;                     // ebreak / ecall instructions
+  logic                sinvalvmaM;                          // sinval.vma
+  logic                sfencewinvalM, sfenceinvalirM;       // sfence.w.inval, sfence.inval.ir
+  logic                invalM;                              // any of the svinval instructions
 
   ///////////////////////////////////////////
   // Decode privileged instructions
   ///////////////////////////////////////////
 
-  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & 
-                      (PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR); 
-  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
-  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000);
-  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001);
-  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101);
-  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001) & 
-                      (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); 
+  assign rs1zeroM =    InstrM[19:15] == 5'b0;
+  
+  // svinval instructions
+  // any svinval instruction is treated as sfence.vma on Wally
+  assign sinvalvmaM =     (InstrM[31:25] == 7'b0001001);
+  assign sfencewinvalM  = (InstrM[31:20] == 12'b000110000000) & rs1zeroM;
+  assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM;
+  assign invalM =         P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); 
+
+  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED & 
+                      (PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR); 
+  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
+  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
+  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
+  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;
+  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001 | invalM) & 
+                      (PrivilegeModeW == P.M_MODE | (PrivilegeModeW == P.S_MODE & ~STATUS_TVM)); 
 
   ///////////////////////////////////////////
   // WFI timeout Privileged Spec 3.1.6.5
   ///////////////////////////////////////////
 
-  if (`U_SUPPORTED) begin:wfi
-    logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
+  if (P.U_SUPPORTED) begin:wfi
+    logic [P.WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
     assign WFICountPlus1 = WFICount + 1;
-    floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount);  // count while in WFI
-    assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; 
+    floprc #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount);  // count while in WFI
+  // coverage off -item e 1 -fecexprrow 1
+  // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout.
+    assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; 
+  // coverage on
   end else assign WFITimeoutM = 0;
 
   ///////////////////////////////////////////
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
index 7d34e22fc..46c69f17d 100644
--- a/src/privileged/privileged.sv
+++ b/src/privileged/privileged.sv
@@ -27,106 +27,104 @@
 // SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module privileged (
-  input  logic             clk, reset,
-  input  logic             StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, FlushW, 
+module privileged import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
+  input  logic              StallD, StallE, StallM, StallW,
+  input  logic              FlushD, FlushE, FlushM, FlushW, 
   // CSR Reads and Writes, and values needed for traps
-  input  logic             CSRReadM, CSRWriteM,                            // Read or write CSRs
-  input  logic [`XLEN-1:0] SrcAM,                                          // GPR register to write
-  input  logic [31:0]      InstrM,                                         // Instruction
-  input  logic [31:0]      InstrOrigM,                                     // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [`XLEN-1:0] IEUAdrM,                                        // address from IEU
-  input  logic [`XLEN-1:0] PCM, PC2NextF,                                  // program counter, next PC going to trap/return PC logic
+  input  logic              CSRReadM, CSRWriteM,                            // Read or write CSRs
+  input  logic [P.XLEN-1:0] SrcAM,                                          // GPR register to write
+  input  logic [31:0]       InstrM,                                         // Instruction
+  input  logic [31:0]       InstrOrigM,                                     // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
+  input  logic [P.XLEN-1:0] IEUAdrM,                                        // address from IEU
+  input  logic [P.XLEN-1:0] PCM, PC2NextF,                                  // program counter, next PC going to trap/return PC logic
   // control signals                                                       
-  input  logic             InstrValidM,                                    // Current instruction is valid (not flushed)
-  input  logic             CommittedM, CommittedF,                         // current instruction is using bus; don't interrupt
-  input  logic             PrivilegedM,                                    // privileged instruction
+  input  logic              InstrValidM,                                    // Current instruction is valid (not flushed)
+  input  logic              CommittedM, CommittedF,                         // current instruction is using bus; don't interrupt
+  input  logic              PrivilegedM,                                    // privileged instruction
   // processor events for performance counter logging                      
-  input  logic             FRegWriteM,                                     // instruction will write floating-point registers
-  input  logic             LoadStallD,                                     // load instruction is stalling
-  input  logic             StoreStallD,                                    // store instruction is stalling
-  input  logic             ICacheStallF,                                   // I cache stalled
-  input  logic             DCacheStallM,                                   // D cache stalled
-  input  logic             BPDirPredWrongM,                                // branch predictor guessed wrong direction
-  input  logic             BTAWrongM,                                      // branch predictor guessed wrong target
-  input  logic             RASPredPCWrongM,                                // return adddress stack guessed wrong target
-  input  logic             IClassWrongM,                                   // branch predictor guessed wrong instruction class
-  input  logic             BPWrongM,                                       // branch predictor is wrong
-  input  logic [3:0]       InstrClassM,                                    // actual instruction class
-  input  logic             DCacheMiss,                                     // data cache miss
-  input  logic             DCacheAccess,                                   // data cache accessed (hit or miss)
-  input  logic             ICacheMiss,                                     // instruction cache miss
-  input  logic             ICacheAccess,                                   // instruction cache access
-  input  logic             DivBusyE,                                       // integer divide busy
-  input  logic             FDivBusyE,                                      // floating point divide busy
+  input  logic              FRegWriteM,                                     // instruction will write floating-point registers
+  input  logic              LoadStallD,                                     // load instruction is stalling
+  input  logic              StoreStallD,                                    // store instruction is stalling
+  input  logic              ICacheStallF,                                   // I cache stalled
+  input  logic              DCacheStallM,                                   // D cache stalled
+  input  logic              BPDirPredWrongM,                                // branch predictor guessed wrong direction
+  input  logic              BTAWrongM,                                      // branch predictor guessed wrong target
+  input  logic              RASPredPCWrongM,                                // return adddress stack guessed wrong target
+  input  logic              IClassWrongM,                                   // branch predictor guessed wrong instruction class
+  input  logic              BPWrongM,                                       // branch predictor is wrong
+  input  logic [3:0]        InstrClassM,                                    // actual instruction class
+  input  logic              DCacheMiss,                                     // data cache miss
+  input  logic              DCacheAccess,                                   // data cache accessed (hit or miss)
+  input  logic              ICacheMiss,                                     // instruction cache miss
+  input  logic              ICacheAccess,                                   // instruction cache access
+  input  logic              DivBusyE,                                       // integer divide busy
+  input  logic              FDivBusyE,                                      // floating point divide busy
   // fault sources                                                         
-  input  logic             InstrAccessFaultF,                              // instruction access fault
-  input  logic             LoadAccessFaultM, StoreAmoAccessFaultM,         // load or store access fault
-  input  logic             HPTWInstrAccessFaultF,                          // hardware page table access fault while fetching instruction PTE
-  input  logic             InstrPageFaultF,                                // page faults
-  input  logic             LoadPageFaultM, StoreAmoPageFaultM,             // page faults
-  input  logic             InstrMisalignedFaultM,                          // misaligned instruction fault
-  input  logic             LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
-  input  logic             IllegalIEUFPUInstrD,                            // illegal instruction from IEU or FPU
-  input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,            // interrupt sources
-  input  logic [63:0]      MTIME_CLINT,                                    // timer value from CLINT
-  input  logic [4:0]       SetFflagsM,                                     // set FCSR flags from FPU
-  input  logic             SelHPTW,                                        // HPTW in use.  Causes system to use S-mode endianness for accesses
+  input  logic              InstrAccessFaultF,                              // instruction access fault
+  input  logic              LoadAccessFaultM, StoreAmoAccessFaultM,         // load or store access fault
+  input  logic              HPTWInstrAccessFaultF,                          // hardware page table access fault while fetching instruction PTE
+  input  logic              InstrPageFaultF,                                // page faults
+  input  logic              LoadPageFaultM, StoreAmoPageFaultM,             // page faults
+  input  logic              InstrMisalignedFaultM,                          // misaligned instruction fault
+  input  logic              LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
+  input  logic              IllegalIEUFPUInstrD,                            // illegal instruction from IEU or FPU
+  input  logic              MTimerInt, MExtInt, SExtInt, MSwInt,            // interrupt sources
+  input  logic [63:0]       MTIME_CLINT,                                    // timer value from CLINT
+  input  logic [4:0]        SetFflagsM,                                     // set FCSR flags from FPU
+  input  logic              SelHPTW,                                        // HPTW in use.  Causes system to use S-mode endianness for accesses
   // CSR outputs                                                           
-  output logic [`XLEN-1:0] CSRReadValW,                                    // Value read from CSR
-  output logic [1:0]       PrivilegeModeW,                                 // current privilege mode
-  output logic [`XLEN-1:0] SATP_REGW,                                      // supervisor address translation register
-  output logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,            // status register bits
-  output logic [1:0]       STATUS_MPP, STATUS_FS,                          // status register bits
-  output var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],            // PMP configuration entries to MMU
-  output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],   // PMP address entries to MMU
-  output logic [2:0]       FRM_REGW,                                       // FPU rounding mode
+  output logic [P.XLEN-1:0] CSRReadValW,                                    // Value read from CSR
+  output logic [1:0]        PrivilegeModeW,                                 // current privilege mode
+  output logic [P.XLEN-1:0] SATP_REGW,                                      // supervisor address translation register
+  output logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,            // status register bits
+  output logic [1:0]        STATUS_MPP, STATUS_FS,                          // status register bits
+  output var logic [7:0]    PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],           // PMP configuration entries to MMU
+  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],  // PMP address entries to MMU
+  output logic [2:0]        FRM_REGW,                                       // FPU rounding mode
+  output logic [3:0]        ENVCFG_CBE,                                     // Cache block operation enables
   // PC logic output in privileged unit                                    
-  output logic [`XLEN-1:0] UnalignedPCNextF,                               // Next PC from trap/return PC logic
+  output logic [P.XLEN-1:0] UnalignedPCNextF,                               // Next PC from trap/return PC logic
   // control outputs                                                       
-  output logic             RetM, TrapM,                                    // return instruction, or trap
-  output logic             sfencevmaM,                                     // sfence.vma instruction
-  input  logic             InvalidateICacheM,                                         // fence instruction
-  output logic             BigEndianM,                                     // Use big endian in current privilege mode
+  output logic              RetM, TrapM,                                    // return instruction, or trap
+  output logic              sfencevmaM,                                     // sfence.vma instruction
+  input  logic              InvalidateICacheM,                              // fence instruction
+  output logic              BigEndianM,                                     // Use big endian in current privilege mode
   // Fault outputs                                                         
-  output logic             BreakpointFaultM, EcallFaultM,                  // breakpoint and Ecall traps should retire
-  output logic             wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
+  output logic              BreakpointFaultM, EcallFaultM,                  // breakpoint and Ecall traps should retire
+  output logic              wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
 );                                                                         
                                                                            
-  logic [3:0]              CauseM;                                         // trap cause
-  logic [15:0]             MEDELEG_REGW;                                   // exception delegation CSR
-  logic [11:0]             MIDELEG_REGW;                                   // interrupt delegation CSR
-  logic                    sretM, mretM;                                   // supervisor / machine return instruction
-  logic                    IllegalCSRAccessM;                              // Illegal access to CSR
-  logic                    IllegalIEUFPUInstrM;                            // Illegal IEU or FPU instruction, delayed to Mem stage
-  logic                    InstrPageFaultM;                                // Instruction page fault, delayed to Mem stage
-  logic                    InstrAccessFaultM;                              // Instruction access fault, delayed to Mem stages
-  logic                    IllegalInstrFaultM;                             // Illegal instruction fault
-  logic                    STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;  // Status bits needed within privileged unit
-  logic                    STATUS_MIE, STATUS_SIE;                         // status bits: interrupt enables
-  logic [11:0]             MIP_REGW, MIE_REGW;                             // interrupt pending and enable bits
-  logic [1:0]              NextPrivilegeModeM;                             // next privilege mode based on trap or return
-  logic                    DelegateM;                                      // trap should be delegated
-  logic                    InterruptM;                                     // interrupt occuring
-  logic                    ExceptionM;                                     // Memory stage instruction caused a fault
-  logic                    HPTWInstrAccessFaultM;                          // Hardware page table access fault while fetching instruction PTE
+  logic [3:0]               CauseM;                                         // trap cause
+  logic [15:0]              MEDELEG_REGW;                                   // exception delegation CSR
+  logic [11:0]              MIDELEG_REGW;                                   // interrupt delegation CSR
+  logic                     sretM, mretM;                                   // supervisor / machine return instruction
+  logic                     IllegalCSRAccessM;                              // Illegal access to CSR
+  logic                     IllegalIEUFPUInstrM;                            // Illegal IEU or FPU instruction, delayed to Mem stage
+  logic                     InstrPageFaultM;                                // Instruction page fault, delayed to Mem stage
+  logic                     InstrAccessFaultM;                              // Instruction access fault, delayed to Mem stages
+  logic                     IllegalInstrFaultM;                             // Illegal instruction fault
+  logic                     STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;  // Status bits needed within privileged unit
+  logic                     STATUS_MIE, STATUS_SIE;                         // status bits: interrupt enables
+  logic [11:0]              MIP_REGW, MIE_REGW;                             // interrupt pending and enable bits
+  logic [1:0]               NextPrivilegeModeM;                             // next privilege mode based on trap or return
+  logic                     DelegateM;                                      // trap should be delegated
+  logic                     InterruptM;                                     // interrupt occuring
+  logic                     ExceptionM;                                     // Memory stage instruction caused a fault
+  logic                     HPTWInstrAccessFaultM;                          // Hardware page table access fault while fetching instruction PTE
   
- 
   // track the current privilege level
-  privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
+  privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
     .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
 
   // decode privileged instructions
-  privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
+  privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:15]), 
     .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
     .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
 
   // Control and Status Registers
-  csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
+  csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
     .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
@@ -139,7 +137,7 @@ module privileged (
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
     .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .SetFflagsM, .FRM_REGW, 
+    .SetFflagsM, .FRM_REGW, .ENVCFG_CBE,
     .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
 
   // pipeline early-arriving trap sources
@@ -148,7 +146,7 @@ module privileged (
     .InstrPageFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalIEUFPUInstrM);
 
   // trap logic
-  trap trap(.reset,
+  trap #(P) trap(.reset,
     .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
     .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
     .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
@@ -158,8 +156,3 @@ module privileged (
     .InstrValidM, .CommittedM, .CommittedF,
     .TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
 endmodule
-
-
-
-
-
diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv
index 615f30439..5ac4cae78 100644
--- a/src/privileged/privmode.sv
+++ b/src/privileged/privmode.sv
@@ -26,9 +26,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module privmode (
+module privmode import cvw::*;  #(parameter cvw_t P) (
   input  logic             clk, reset,
   input  logic             StallW, 
   input  logic             TrapM,               // Trap 
@@ -40,20 +38,20 @@ module privmode (
   output logic [1:0]       PrivilegeModeW       // current privilege mode
 ); 
   
-  if (`U_SUPPORTED) begin:privmode
+  if (P.U_SUPPORTED) begin:privmode
     // PrivilegeMode FSM
     always_comb begin
       if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
-        if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE;
-        else                          NextPrivilegeModeM = `M_MODE;
-      end else if (mretM)             NextPrivilegeModeM = STATUS_MPP;
-      else     if (sretM)             NextPrivilegeModeM = {1'b0, STATUS_SPP};
-      else                            NextPrivilegeModeM = PrivilegeModeW;
+        if (P.S_SUPPORTED & DelegateM) NextPrivilegeModeM = P.S_MODE;
+        else                           NextPrivilegeModeM = P.M_MODE;
+      end else if (mretM)              NextPrivilegeModeM = STATUS_MPP;
+      else     if (sretM)              NextPrivilegeModeM = {1'b0, STATUS_SPP};
+      else                             NextPrivilegeModeM = PrivilegeModeW;
     end
 
-    flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
+    flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, P.M_MODE, PrivilegeModeW);
   end else begin  // only machine mode supported
-    assign NextPrivilegeModeM = `M_MODE;
-    assign PrivilegeModeW = `M_MODE;
+    assign NextPrivilegeModeM = P.M_MODE;
+    assign PrivilegeModeW = P.M_MODE;
   end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
index 684b0ad73..be1a238ad 100644
--- a/src/privileged/privpiperegs.sv
+++ b/src/privileged/privpiperegs.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module privpiperegs (
   input  logic         clk, reset,  
   input  logic         StallD, StallE, StallM,
diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv
index 96b404ef9..2720570de 100644
--- a/src/privileged/trap.sv
+++ b/src/privileged/trap.sv
@@ -26,9 +26,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module trap (
+module trap import cvw::*;  #(parameter cvw_t P) (
   input  logic                 reset, 
   input  logic                 InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM,
   input  logic                 BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
@@ -63,16 +61,16 @@ module trap (
   // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
   ///////////////////////////////////////////
 
-  assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
-  assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
-  assign PendingIntsM = MIP_REGW & MIE_REGW;
-  assign IntPendingM = |PendingIntsM;
-  assign Committed = CommittedM | CommittedF;
-  assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
-  assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
-  assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
-  assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
-                     (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
+  assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
+  assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
+  assign PendingIntsM  = MIP_REGW & MIE_REGW;
+  assign IntPendingM   = |PendingIntsM;
+  assign Committed     = CommittedM | CommittedF;
+  assign EnabledIntsM  = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
+  assign ValidIntsM    = {12{~Committed}} & EnabledIntsM;
+  assign InterruptM    = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
+  assign DelegateM     = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
+                     (PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
 
   ///////////////////////////////////////////
   // Trigger Traps and RET
@@ -90,7 +88,7 @@ module trap (
                       LoadAccessFaultM | StoreAmoAccessFaultM;
   // coverage on
   assign TrapM = ExceptionM | InterruptM; 
-  assign RetM = mretM | sretM;
+  assign RetM  = mretM | sretM;
 
   ///////////////////////////////////////////
   // Cause priority defined in table 3.7 of 20190608 privileged spec
diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
index 011356ba2..381297f00 100644
--- a/src/uncore/ahbapbbridge.sv
+++ b/src/uncore/ahbapbbridge.sv
@@ -25,31 +25,30 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module ahbapbbridge #(PERIPHS = 2) (
-  input  logic                HCLK, HRESETn,
-  input  logic [PERIPHS-1:0]  HSEL,  
-  input  logic [`PA_BITS-1:0] HADDR, 
-  input  logic [`XLEN-1:0]    HWDATA,
-  input  logic [`XLEN/8-1:0]  HWSTRB,
-  input  logic                HWRITE,
-  input  logic [1:0]          HTRANS,
-  input  logic                HREADY,
+module ahbapbbridge import cvw::*;  #(parameter cvw_t P, 
+                                      parameter PERIPHS = 2) (
+  input  logic                 HCLK, HRESETn,
+  input  logic [PERIPHS-1:0]   HSEL,  
+  input  logic [P.PA_BITS-1:0] HADDR, 
+  input  logic [P.XLEN-1:0]    HWDATA,
+  input  logic [P.XLEN/8-1:0]  HWSTRB,
+  input  logic                 HWRITE,
+  input  logic [1:0]           HTRANS,
+  input  logic                 HREADY,
 //  input  logic [3:0]        HPROT, // not used
-  output logic [`XLEN-1:0]    HRDATA,
-  output logic                HRESP, HREADYOUT,
-  output logic                PCLK, PRESETn,
-  output logic [PERIPHS-1:0]  PSEL,
-  output logic                PWRITE,
-  output logic                PENABLE,
-  output logic [31:0]         PADDR,
-  output logic [`XLEN-1:0]    PWDATA,
+  output logic [P.XLEN-1:0]    HRDATA,
+  output logic                 HRESP, HREADYOUT,
+  output logic                 PCLK, PRESETn,
+  output logic [PERIPHS-1:0]   PSEL,
+  output logic                 PWRITE,
+  output logic                 PENABLE,
+  output logic [31:0]          PADDR,
+  output logic [P.XLEN-1:0]    PWDATA,
 //  output logic [2:0]        PPROT, // not used
-  output logic [`XLEN/8-1:0]  PSTRB,
+  output logic [P.XLEN/8-1:0]  PSTRB,
 //  output logic              PWAKEUP // not used
-  input  logic [PERIPHS-1:0]  PREADY,
-  input  var   [PERIPHS-1:0][`XLEN-1:0] PRDATA
+  input  logic [PERIPHS-1:0]   PREADY,
+  input  var   [PERIPHS-1:0][P.XLEN-1:0] PRDATA
 );
 
   logic                       initTrans, initTransSel, initTransSelD;
@@ -57,15 +56,15 @@ module ahbapbbridge #(PERIPHS = 2) (
   logic                       PREADYOUT;
 
   // convert AHB to APB signals
-  assign PCLK = HCLK;
+  assign PCLK    = HCLK;
   assign PRESETn = HRESETn;
 
   // identify start of a transaction
-  assign initTrans = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
+  assign initTrans    = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
   assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected
 
   // delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time
-  flopen #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
+  flopen  #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
   flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE); 
   flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL); 
   // PPROT[2:0] = {Data/InstrB, Secure, Privileged};
@@ -74,7 +73,7 @@ module ahbapbbridge #(PERIPHS = 2) (
 
   // AHB Data phase signal doesn't need delay.  Note that they are guaranteed to remain stable until READY is asserted
   assign PWDATA = HWDATA;
-  assign PSTRB = HWSTRB;
+  assign PSTRB  = HWSTRB;
 
   // enable logic: goes high a cycle after initTrans, then back low on cycle after desired PREADY is asserted
   // cycle1: AHB puts HADDR, HWRITE, HSEL on bus.  initTrans is 1, and these are captured
@@ -104,4 +103,3 @@ assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before a
   // resp logic
   assign HRESP = 0; // bridge never indicates errors
 endmodule
-
diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
index 7b6bf676b..6e35ffdaf 100644
--- a/src/uncore/clint_apb.sv
+++ b/src/uncore/clint_apb.sv
@@ -27,17 +27,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module clint_apb (
+module clint_apb import cvw::*;  #(parameter cvw_t P) (
   input  logic                PCLK, PRESETn,
   input  logic                PSEL,
   input  logic [15:0]         PADDR, 
-  input  logic [`XLEN-1:0]    PWDATA,
-  input  logic [`XLEN/8-1:0]  PSTRB,
+  input  logic [P.XLEN-1:0]   PWDATA,
+  input  logic [P.XLEN/8-1:0] PSTRB,
   input  logic                PWRITE,
   input  logic                PENABLE,
-  output logic [`XLEN-1:0]    PRDATA,
+  output logic [P.XLEN-1:0]   PRDATA,
   output logic                PREADY,
   output logic [63:0] MTIME, 
   output logic                MTimerInt, MSwInt
@@ -50,11 +48,11 @@ module clint_apb (
   integer                     i, j;
   
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
+  assign PREADY   = 1'b1;                     // CLINT never takes >1 cycle to respond
 
   // word aligned reads
-  if (`XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000};
-  else           assign #2 entry = {PADDR[15:2], 2'b00}; 
+  if (P.XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000};
+  else            assign #2 entry = {PADDR[15:2], 2'b00}; 
   
   // DH 2/20/21: Eventually allow MTIME to run off a separate clock
   // This will require synchronizing MTIME to the system clock
@@ -63,7 +61,7 @@ module clint_apb (
   // Use req and ack signals synchronized across the clock domains.
 
   // register access
-  if (`XLEN==64) begin:clint // 64-bit
+  if (P.XLEN==64) begin:clint // 64-bit
     always @(posedge PCLK) begin
       case(entry)
         16'h0000: PRDATA <= {63'b0, MSIP};
@@ -79,7 +77,7 @@ module clint_apb (
       end else if (memwrite) begin
         if (entry == 16'h0000) MSIP <= PWDATA[0];
         if (entry == 16'h4000) begin
-          for(i=0;i<`XLEN/8;i++)
+          for(i=0;i<P.XLEN/8;i++)
             if(PSTRB[i])
               MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
         end
@@ -93,7 +91,7 @@ module clint_apb (
         MTIME <= 0;
       end else if (memwrite & entry == 16'hBFF8) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        for(j=0;j<`XLEN/8;j++)
+        for(j=0;j<P.XLEN/8;j++)
           if(PSTRB[j])
             MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8];
       end else MTIME <= MTIME + 1; 
@@ -116,11 +114,11 @@ module clint_apb (
       end else if (memwrite) begin
         if (entry == 16'h0000) MSIP <= PWDATA[0];
         if (entry == 16'h4000) 
-          for(j=0;j<`XLEN/8;j++)
+          for(j=0;j<P.XLEN/8;j++)
             if(PSTRB[j])
               MTIMECMP[j*8 +: 8] <= PWDATA[j*8 +: 8];
         if (entry == 16'h4004) 
-          for(j=0;j<`XLEN/8;j++)
+          for(j=0;j<P.XLEN/8;j++)
             if(PSTRB[j])
               MTIMECMP[32 + j*8 +: 8] <= PWDATA[j*8 +: 8];
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
@@ -133,12 +131,12 @@ module clint_apb (
         MTIME <= 0;
         // MTIMECMP is not reset
       end else if (memwrite & (entry == 16'hBFF8)) begin
-        for(i=0;i<`XLEN/8;i++)
+        for(i=0;i<P.XLEN/8;i++)
           if(PSTRB[i])
             MTIME[i*8 +: 8] <= PWDATA[i*8 +: 8];
       end else if (memwrite & (entry == 16'hBFFC)) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        for(i=0;i<`XLEN/8;i++)
+        for(i=0;i<P.XLEN/8;i++)
           if(PSTRB[i])
             MTIME[32 + i*8 +: 8]<= PWDATA[i*8 +: 8];
       end else MTIME <= MTIME + 1;
@@ -151,37 +149,37 @@ module clint_apb (
 
 endmodule
 
-module timeregsync(
-  input  logic clk, resetn, 
-  input  logic             we0, we1,
-  input  logic [`XLEN-1:0] wd,
-  output logic [63:0]      q);
+module timeregsync  import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, resetn, 
+  input  logic              we0, we1,
+  input  logic [P.XLEN-1:0] wd,
+  output logic [63:0]       q);
 
-  if (`XLEN==64) 
+  if (P.XLEN==64) 
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn) q <= 0;
+      if (~resetn)  q <= 0;
       else if (we0) q <= wd;
       else          q <= q + 1;
   else
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn) q <= 0;
+      if (~resetn)  q <= 0;
       else if (we0) q[31:0] <= wd;
       else if (we1) q[63:32] <= wd;
       else          q <= q + 1;
 endmodule
 
-module timereg(
-  input  logic PCLK, PRESETn, TIMECLK,
-  input  logic             we0, we1,
-  input  logic [`XLEN-1:0] PWDATA,
-  output logic [63:0]      MTIME,
-  output logic             done);
+module timereg  import cvw::*;  #(parameter cvw_t P) (
+  input  logic              PCLK, PRESETn, TIMECLK,
+  input  logic              we0, we1,
+  input  logic [P.XLEN-1:0] PWDATA,
+  output logic [63:0]       MTIME,
+  output logic              done);
 
-//  if (`TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
+//  if (P.TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
   if (1) begin:timereg // use PCLK for MTIME
     timregsync timeregsync(.clk(PCLK), .resetn(PRESETn), .we0, .we1, .wd(PWDATA), .q(MTIME));
-    assign done = 1; // immediately completes
-  end else begin // use asynchronous TIMECLK 
+    assign done = 1;   // immediately completes
+  end else begin       // use asynchronous TIMECLK 
     // TIME counter runs on TIMECLK but bus interface runs on PCLK
     // Need to synchronize reads and writes
     // This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits
@@ -192,7 +190,7 @@ module timereg(
     // There is no back pressure on instructions, so if multiple counter writes occur ***
 
     logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
-    logic [`XLEN-1:0] wd_stored;
+    logic [P.XLEN-1:0] wd_stored;
     logic [63:0] time_int, time_int_gc, time_gc, MTIME_GC;
 
     // When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
@@ -216,7 +214,7 @@ module timereg(
     // synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered
     sync async(PCLK, req_sync, ack);
 
-    timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
+    timeregsync #(P) timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
     binarytogray b2g(time_int, time_int_gc);
     flop gcreg(TIMECLK, time_int_gc, time_gc);
 
@@ -225,7 +223,7 @@ module timereg(
   end
 endmodule
 
-module binarytogray #(parameter N = `XLEN) (
+module binarytogray #(parameter N) (
   input  logic [N-1:0] b,
   output logic [N-1:0] g);
 
@@ -234,7 +232,7 @@ module binarytogray #(parameter N = `XLEN) (
   assign g = b ^ {1'b0, b[N-1:1]};
 endmodule
 
-module graytobinary #(parameter N = `XLEN) (
+module graytobinary #(parameter N) (
   input  logic [N-1:0] g,
   output logic [N-1:0] b);
 
diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
index 869f1bbdd..baab83088 100644
--- a/src/uncore/gpio_apb.sv
+++ b/src/uncore/gpio_apb.sv
@@ -28,81 +28,79 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module gpio_apb (
-  input  logic              PCLK, PRESETn,
-  input  logic              PSEL,
-  input  logic [7:0]        PADDR, 
-  input  logic [`XLEN-1:0]  PWDATA,
-  input  logic [`XLEN/8-1:0] PSTRB,
-  input  logic              PWRITE,
-  input  logic              PENABLE,
-  output logic [`XLEN-1:0]  PRDATA,
-  output logic              PREADY,
-  input  logic [31:0]       iof0, iof1,
-  input  logic [31:0]       GPIOIN,
-  output logic [31:0]       GPIOOUT, GPIOEN,
-  output logic              GPIOIntr
+module gpio_apb import cvw::*;  #(parameter cvw_t P) (
+  input  logic                PCLK, PRESETn,
+  input  logic                PSEL,
+  input  logic [7:0]          PADDR, 
+  input  logic [P.XLEN-1:0]   PWDATA,
+  input  logic [P.XLEN/8-1:0] PSTRB,
+  input  logic                PWRITE,
+  input  logic                PENABLE,
+  output logic [P.XLEN-1:0]   PRDATA,
+  output logic                PREADY,
+  input  logic [31:0]         iof0, iof1,
+  input  logic [31:0]         GPIOIN,
+  output logic [31:0]         GPIOOUT, GPIOEN,
+  output logic                GPIOIntr
 );
 
-  logic [31:0]              input0d, input1d, input2d, input3d;
-  logic [31:0]              input_val, input_en, output_en, output_val;
-  logic [31:0]              rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; 
-  logic [31:0]              out_xor, iof_en, iof_sel, iof_out, gpio_out;
-  logic [7:0]               entry;
-  logic [31:0]              Din, Dout;
-  logic                     memwrite;
+  logic [31:0]                input0d, input1d, input2d, input3d;
+  logic [31:0]                input_val, input_en, output_en, output_val;
+  logic [31:0]                rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; 
+  logic [31:0]                out_xor, iof_en, iof_sel, iof_out, gpio_out;
+  logic [7:0]                 entry;
+  logic [31:0]                Din, Dout;
+  logic                       memwrite;
   
   // APB I/O
-  assign entry = {PADDR[7:2],2'b00};  // 32-bit word-aligned accesses
+  assign entry    = {PADDR[7:2],2'b00};       // 32-bit word-aligned accesses
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
+  assign PREADY   = 1'b1;                     // GPIO never takes >1 cycle to respond
 
   // account for subword read/write circuitry
   // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
   //    (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
-  if (`XLEN == 64) begin
-    assign Din =    entry[2] ? PWDATA[63:32] : PWDATA[31:0];
+  if (P.XLEN == 64) begin
+    assign Din    = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
     assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
   end else begin // 32-bit
-    assign Din = PWDATA[31:0];
+    assign Din    = PWDATA[31:0];
     assign PRDATA = Dout;
   end
 
   // register access
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin // asynch reset
-      input_en <= 0;
+      input_en  <= 0;
       output_en <= 0;
       // *** synch reset not yet implemented [DH: can we delete this comment?  Check if a sync reset is required]
       output_val <= #1 0;
-      rise_ie <= #1 0;
-      rise_ip <= #1 0;
-      fall_ie <= #1 0;
-      fall_ip <= #1 0;
-      high_ie <= #1 0;
-      high_ip <= #1 0;
-      low_ie <= #1 0;
-      low_ip <= #1 0;
-      iof_en <= #1 0;
-      iof_sel <= #1 0;
-      out_xor <= #1 0;
+      rise_ie    <= #1 0;
+      rise_ip    <= #1 0;
+      fall_ie    <= #1 0;
+      fall_ip    <= #1 0;
+      high_ie    <= #1 0;
+      high_ip    <= #1 0;
+      low_ie     <= #1 0;
+      low_ip     <= #1 0;
+      iof_en     <= #1 0;
+      iof_sel    <= #1 0;
+      out_xor    <= #1 0;
     end else begin     // writes
         // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
         /* verilator lint_off CASEINCOMPLETE */
       if (memwrite) 
         case(entry)
-          8'h04: input_en <= #1 Din;
-          8'h08: output_en <= #1 Din;
+          8'h04: input_en   <= #1 Din;
+          8'h08: output_en  <= #1 Din;
           8'h0C: output_val <= #1 Din;
-          8'h18: rise_ie <= #1 Din;
-          8'h20: fall_ie <= #1 Din;
-          8'h28: high_ie <= #1 Din;
-          8'h30: low_ie  <= #1 Din;
-          8'h38: iof_en  <= #1 Din;
-          8'h3C: iof_sel <= #1 Din;
-          8'h40: out_xor <= #1 Din;
+          8'h18: rise_ie    <= #1 Din;
+          8'h20: fall_ie    <= #1 Din;
+          8'h28: high_ie    <= #1 Din;
+          8'h30: low_ie     <= #1 Din;
+          8'h38: iof_en     <= #1 Din;
+          8'h3C: iof_sel    <= #1 Din;
+          8'h40: out_xor    <= #1 Din;
         endcase
         /* verilator lint_on CASEINCOMPLETE */
 
@@ -117,40 +115,39 @@ module gpio_apb (
       else                             low_ip  <= low_ip  | ~input3d;
 
       case(entry) // flop to sample inputs
-        8'h00: Dout <= #1 input_val;
-        8'h04: Dout <= #1 input_en;
-        8'h08: Dout <= #1 output_en;
-        8'h0C: Dout <= #1 output_val;
-        8'h18: Dout <= #1 rise_ie;
-        8'h1C: Dout <= #1 rise_ip;
-        8'h20: Dout <= #1 fall_ie;
-        8'h24: Dout <= #1 fall_ip;
-        8'h28: Dout <= #1 high_ie;
-        8'h2C: Dout <= #1 high_ip;
-        8'h30: Dout <= #1 low_ie;
-        8'h34: Dout <= #1 low_ip;
-        8'h38: Dout <= #1 iof_en;
-        8'h3C: Dout <= #1 iof_sel;
-        8'h40: Dout <= #1 out_xor; 
+        8'h00: Dout   <= #1 input_val;
+        8'h04: Dout   <= #1 input_en;
+        8'h08: Dout   <= #1 output_en;
+        8'h0C: Dout   <= #1 output_val;
+        8'h18: Dout   <= #1 rise_ie;
+        8'h1C: Dout   <= #1 rise_ip;
+        8'h20: Dout   <= #1 fall_ie;
+        8'h24: Dout   <= #1 fall_ip;
+        8'h28: Dout   <= #1 high_ie;
+        8'h2C: Dout   <= #1 high_ip;
+        8'h30: Dout   <= #1 low_ie;
+        8'h34: Dout   <= #1 low_ip;
+        8'h38: Dout   <= #1 iof_en;
+        8'h3C: Dout   <= #1 iof_sel;
+        8'h40: Dout   <= #1 out_xor; 
         default: Dout <= #1 0;
       endcase
     end
 
   // chip i/o
   // connect OUT to IN for loopback testing
-  if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en;
-  else                     assign input0d = GPIOIN & input_en;
+  if (P.GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en;
+  else                      assign input0d = GPIOIN & input_en;
 
   // synchroninzer for inputs
   flop #(32) sync1(PCLK,input0d,input1d);
   flop #(32) sync2(PCLK,input1d,input2d);
   flop #(32) sync3(PCLK,input2d,input3d);
   assign input_val = input3d;
-  assign iof_out = iof_sel & iof1 | ~iof_sel & iof0;         // per-bit mux between iof1 and iof0
-  assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
-  assign GPIOOUT = gpio_out ^ out_xor;                   // per-bit flip output polarity
-  assign GPIOEN = output_en;
+  assign iof_out   = iof_sel & iof1 | ~iof_sel & iof0;        // per-bit mux between iof1 and iof0
+  assign gpio_out  = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
+  assign GPIOOUT   = gpio_out ^ out_xor;                      // per-bit flip output polarity
+  assign GPIOEN    = output_en;
 
-  assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
+  assign GPIOIntr  = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
 endmodule
-
diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
index 7231f609b..36de7f396 100644
--- a/src/uncore/plic_apb.sv
+++ b/src/uncore/plic_apb.sv
@@ -31,9 +31,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-`define N `PLIC_NUM_SRC
 // number of interrupt sources
 // does not include source 0, which does not connect to anything according to spec
 // up to 63 sources supported; in the future, allow up to 1023 sources
@@ -42,51 +39,53 @@
 // number of conexts
 // hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts
 
-module plic_apb (
-  input  logic               PCLK, PRESETn,
-  input  logic               PSEL,
-  input  logic [27:0]        PADDR, 
-  input  logic [`XLEN-1:0]   PWDATA,
-  input  logic [`XLEN/8-1:0] PSTRB,
-  input  logic               PWRITE,
-  input  logic               PENABLE,
-  output logic [`XLEN-1:0]   PRDATA,
-  output logic               PREADY,
-  input  logic               UARTIntr,GPIOIntr,
-  output logic               MExtInt, SExtInt
+module plic_apb import cvw::*;  #(parameter cvw_t P) (
+  input  logic                PCLK, PRESETn,
+  input  logic                PSEL,
+  input  logic [27:0]         PADDR, 
+  input  logic [P.XLEN-1:0]   PWDATA,
+  input  logic [P.XLEN/8-1:0] PSTRB,
+  input  logic                PWRITE,
+  input  logic                PENABLE,
+  output logic [P.XLEN-1:0]   PRDATA,
+  output logic                PREADY,
+  input  logic                UARTIntr,GPIOIntr,
+  output logic                MExtInt, SExtInt
 );
 
-  logic                      memwrite, memread;
-  logic [23:0]               entry;
-  logic [31:0]               Din, Dout;
+  logic                       memwrite, memread;
+  logic [23:0]                entry;
+  logic [31:0]                Din, Dout;
 
   // context-independent signals
-  logic [`N:1]               requests;
-  logic [`N:1][2:0]          intPriority;
-  logic [`N:1]               intInProgress, intPending, nextIntPending;
+  logic [P.PLIC_NUM_SRC:1]               requests;
+  logic [P.PLIC_NUM_SRC:1][2:0]          intPriority;
+  logic [P.PLIC_NUM_SRC:1]               intInProgress, intPending, nextIntPending;
   
   // context-dependent signals
   logic [`C-1:0][2:0]        intThreshold;
-  logic [`C-1:0][`N:1]       intEn;
+  logic [`C-1:0][P.PLIC_NUM_SRC:1]       intEn;
   logic [`C-1:0][5:0]        intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1]  irqMatrix;
+  logic [`C-1:0][7:1][P.PLIC_NUM_SRC:1]  irqMatrix;
   logic [`C-1:0][7:1]        priorities_with_irqs;
   logic [`C-1:0][7:1]        max_priority_with_irqs;
-  logic [`C-1:0][`N:1]       irqs_at_max_priority;
+  logic [`C-1:0][P.PLIC_NUM_SRC:1]       irqs_at_max_priority;
   logic [`C-1:0][7:1]        threshMask;
+  logic [P.PLIC_NUM_SRC-1:0] One;
 
   // =======
   // AHB I/O
   // =======
 
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign memread  = ~PWRITE & PSEL;  // read at start of access phase.  PENABLE hasn't set up before this
-  assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond
-  assign entry = {PADDR[23:2],2'b0};
+  assign memread  = ~PWRITE & PSEL;           // read at start of access phase.  PENABLE hasn't set up before this
+  assign PREADY   = 1'b1;                     // PLIC never takes >1 cycle to respond
+  assign entry    = {PADDR[23:2],2'b0};
+  assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment.
 
   // account for subword read/write circuitry
   // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
-  if (`XLEN == 64) begin
+  if (P.XLEN == 64) begin
     assign Din    = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
     assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
   end else begin // 32-bit
@@ -97,81 +96,81 @@ module plic_apb (
   // ==================
   // Register Interface
   // ==================
+  localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31;
+    
   always @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
-      intPriority   <= #1 {`N{3'b0}};
-      intEn         <= #1 {2{`N'b0}};
-      intThreshold  <= #1 {2{3'b0}};
-      intInProgress <= #1 `N'b0;
+      intPriority   <= #1 '0;
+      intEn         <= #1 '0;
+      intThreshold  <= #1 '0;
+      intInProgress <= #1 '0;
     // writing
     end else begin
       if (memwrite)
         casez(entry)
           24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0];
-          `ifdef PLIC_NUM_SRC_LT_32 // eventually switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources
-          24'h002000: intEn[0][`N:1] <= #1 Din[`N:1];
-          24'h002080: intEn[1][`N:1] <= #1 Din[`N:1];
-          `endif
-          `ifndef PLIC_NUM_SRC_LT_32
-          24'h002000: intEn[0][31:1] <= #1 Din[31:1];
-          24'h002004: intEn[0][`N:32] <= #1 Din[31:0];
-          24'h002080: intEn[1][31:1] <= #1 Din[31:1];
-          24'h002084: intEn[1][`N:32] <= #1 Din[31:0];
-          `endif
-          24'h200000: intThreshold[0] <= #1 Din[2:0];
-          24'h200004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion 
-          24'h201000: intThreshold[1] <= #1 Din[2:0];
-          24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1];
+          24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1];
+
+          // verilator lint_off SELRANGE  
+          // *** RT: Long term we want to factor out these variable number of registers as a generate loop
+          // I think this won't work as a case statement.
+          24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32]         <= #1 Din[P.PLIC_NUM_SRC-32:0];
+          24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32]         <= #1 Din[P.PLIC_NUM_SRC-32:0];
+          // verilator lint_on SELRANGE
+          24'h200000: intThreshold[0]         <= #1 Din[2:0];
+          24'h200004: intInProgress           <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h201000: intThreshold[1]         <= #1 Din[2:0];
+          24'h201004: intInProgress           <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
         endcase
       // Read synchronously because a read can have side effect of changing intInProgress
-      if (memread)
+      if (memread) begin
         casez(entry)
           24'h000000: Dout <= #1 32'b0;  // there is no intPriority[0]
           24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};      
-          `ifdef PLIC_NUM_SRC_LT_32
-          24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
-          24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};
-          24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0};
-          `endif
-          `ifndef PLIC_NUM_SRC_LT_32
-          24'h001000: Dout <= #1 {intPending[31:1],1'b0};
-          24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]};
-          24'h002000: Dout <= #1 {intEn[0][31:1],1'b0};
-          24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]};
-          24'h002080: Dout <= #1 {intEn[0][31:1],1'b0};
-          24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]};
-          `endif
+          24'h001000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0};
+          24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0};
+
+          // verilator lint_off SELRANGE
+          // verilator lint_off WIDTHTRUNC 
+          24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]};
+          24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]};
+          // verilator lint_on SELRANGE 
+          // verilator lint_on WIDTHTRUNC 
+
+          24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0};
+          // verilator lint_off SELRANGE
+          // verilator lint_off WIDTHTRUNC 
+          24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]};
+          // verilator lint_on SELRANGE
+          // verilator lint_on WIDTHTRUNC 
           24'h200000: Dout <= #1 {29'b0,intThreshold[0]};
           24'h200004: begin
             Dout <= #1 {26'b0,intClaim[0]};
-            intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
+            intInProgress <= #1 intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
           24'h201000: Dout <= #1 {29'b0,intThreshold[1]};
           24'h201004: begin
             Dout <= #1 {26'b0,intClaim[1]};
-            intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
+            intInProgress <= #1 intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
           default: Dout <= #1 32'h0; // invalid access
         endcase
-      else Dout <= #1 32'h0;
+      end else Dout <= #1 32'h0;
    end
   end
 
   // connect sources to requests
   always_comb begin
-    requests = `N'b0;
-    `ifdef PLIC_GPIO_ID
-      requests[`PLIC_GPIO_ID] = GPIOIntr;
-    `endif
-    `ifdef PLIC_UART_ID
-      requests[`PLIC_UART_ID] = UARTIntr;
-    `endif
+    requests = {P.PLIC_NUM_SRC{1'b0}};
+    if(P.PLIC_GPIO_ID != 0) requests[P.PLIC_GPIO_ID] = GPIOIntr;
+    if(P.PLIC_UART_ID != 0) requests[P.PLIC_UART_ID] = UARTIntr;
   end
 
-  // pending interrupt requests
+  // pending interrupt request
   assign nextIntPending = (intPending | requests) & ~intInProgress; 
-  flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
+  flopr #(P.PLIC_NUM_SRC) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
 
   // context-dependent signals
   genvar ctx;
@@ -184,7 +183,7 @@ module plic_apb (
     //   ("active" meaning it is enabled in context <ctx> and is pending)
     genvar src, pri;
     for (pri=1; pri<=7; pri++) begin
-      for (src=1; src<=`N; src++) begin
+      for (src=1; src<=P.PLIC_NUM_SRC; src++) begin
         assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src];
       end
     end
@@ -213,14 +212,14 @@ module plic_apb (
 
     // of the sources at the highest priority level that has active requests,
     // which sources have active requests?
-    assign irqs_at_max_priority[ctx][`N:1] =
-      ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
-      ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
-      ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
-      ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
-      ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
-      ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
-      ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
+    assign irqs_at_max_priority[ctx][P.PLIC_NUM_SRC:1] =
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
 
     // of the sources at the highest priority level that has active requests,
     // choose the source with the lowest source ID to be the most urgent
@@ -228,7 +227,7 @@ module plic_apb (
     integer k;
     always_comb begin
       intClaim[ctx] = 6'b0;
-      for (k=`N; k>0; k--) begin
+      for (k=P.PLIC_NUM_SRC; k>0; k--) begin
         if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0];
       end
     end
@@ -249,4 +248,3 @@ module plic_apb (
   assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
   assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
 endmodule
-
diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
index 7a332bfad..78de50aa1 100644
--- a/src/uncore/ram_ahb.sv
+++ b/src/uncore/ram_ahb.sv
@@ -26,40 +26,40 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 `define RAM_LATENCY 0
 
-module ram_ahb #(parameter BASE=0, RANGE = 65535) (
-  input  logic                HCLK, HRESETn, 
-  input  logic                HSELRam,
-  input  logic [`PA_BITS-1:0] HADDR,
-  input  logic                HWRITE,
-  input  logic                HREADY,
-  input  logic [1:0]          HTRANS,
-  input  logic [`XLEN-1:0]    HWDATA,
-  input  logic [`XLEN/8-1:0]  HWSTRB,
-  output logic [`XLEN-1:0]    HREADRam,
-  output logic                HRESPRam, HREADYRam
+module ram_ahb import cvw::*;  #(parameter cvw_t P, 
+                                 parameter BASE=0, RANGE = 65535) (
+  input  logic                 HCLK, HRESETn, 
+  input  logic                 HSELRam,
+  input  logic [P.PA_BITS-1:0] HADDR,
+  input  logic                 HWRITE,
+  input  logic                 HREADY,
+  input  logic [1:0]           HTRANS,
+  input  logic [P.XLEN-1:0]    HWDATA,
+  input  logic [P.XLEN/8-1:0]  HWSTRB,
+  output logic [P.XLEN-1:0]    HREADRam,
+  output logic                 HRESPRam, HREADYRam
 );
 
-  localparam               ADDR_WIDTH = $clog2(RANGE/8);
-  localparam               OFFSET = $clog2(`XLEN/8);   
+  localparam                   ADDR_WIDTH = $clog2(RANGE/8);
+  localparam                   OFFSET = $clog2(P.XLEN/8);   
 
-  logic [`XLEN/8-1:0]         ByteMask;
-  logic [`PA_BITS-1:0]        HADDRD, RamAddr;
-  logic                       initTrans;
-  logic                       memwrite, memwriteD, memread;
-  logic                       nextHREADYRam;
-  logic                       DelayReady;
+  logic [P.XLEN/8-1:0]         ByteMask;
+  logic [P.PA_BITS-1:0]        HADDRD, RamAddr;
+  logic                        initTrans;
+  logic                        memwrite, memwriteD, memread;
+  logic                        nextHREADYRam;
+  logic                        DelayReady;
 
   // a new AHB transactions starts when HTRANS requests a transaction, 
   // the peripheral is selected, and the previous transaction is completing
   assign initTrans = HREADY & HSELRam & HTRANS[1] ; 
-  assign memwrite = initTrans & HWRITE;  
-  assign memread = initTrans & ~HWRITE;
+  assign memwrite  = initTrans & HWRITE;  
+  assign memread   = initTrans & ~HWRITE;
  
   flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); 
-  flopenr #(`PA_BITS)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
+  flopenr #(P.PA_BITS)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
 
   // Stall on a read after a write because the RAM can't take both adddresses on the same cycle
   assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady;
@@ -68,13 +68,12 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   assign HRESPRam = 0; // OK
 
   // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
-  mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
+  mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
 
   // single-ported RAM
-  ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), 
+  ram1p1rwbe #(.P(P), .DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), 
     .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
   
-
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
   if(`RAM_LATENCY > 0) begin
     logic [7:0]       NextCycle, Cycle;
@@ -89,15 +88,15 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
     
     always_ff @(posedge HCLK)
       if (~HRESETn)    CurrState <= #1 READY;
-      else CurrState <= #1 NextState;  
+      else             CurrState <= #1 NextState;  
 
     always_comb begin
     case(CurrState)
       READY: if(initTrans & ~CycleFlag) NextState = DELAY;
-        else                          NextState = READY;
-        DELAY: if(CycleFlag)                  NextState = READY;
-    else                          NextState = DELAY;
-      default:                                      NextState = READY;
+        else                            NextState = READY;
+        DELAY: if(CycleFlag)            NextState = READY;
+    else                                NextState = DELAY;
+      default:                          NextState = READY;
     endcase
     end
 
@@ -110,4 +109,3 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   end
 
 endmodule
-  
diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
index b009185ba..0c09191be 100644
--- a/src/uncore/rom_ahb.sv
+++ b/src/uncore/rom_ahb.sv
@@ -26,27 +26,25 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module rom_ahb #(parameter BASE=0, RANGE = 65535) (
-  input  logic             HCLK, HRESETn, 
-  input  logic             HSELRom,
-  input  logic [`PA_BITS-1:0]  HADDR,
-  input  logic             HREADY,
-  input  logic [1:0]       HTRANS,
-  output logic [`XLEN-1:0] HREADRom,
-  output logic             HRESPRom, HREADYRom
+module rom_ahb import cvw::*;  #(parameter cvw_t P, 
+                                 parameter BASE=0, RANGE = 65535) (
+  input  logic                 HCLK, HRESETn, 
+  input  logic                 HSELRom,
+  input  logic [P.PA_BITS-1:0] HADDR,
+  input  logic                 HREADY,
+  input  logic [1:0]           HTRANS,
+  output logic [P.XLEN-1:0]    HREADRom,
+  output logic                 HRESPRom, HREADYRom
 );
 
   localparam ADDR_WIDTH = $clog2(RANGE/8);
-  localparam OFFSET = $clog2(`XLEN/8);   
+  localparam OFFSET     = $clog2(P.XLEN/8);   
  
   // Never stalls
   assign HREADYRom = 1'b1;
-  assign HRESPRom = 0; // OK
+  assign HRESPRom  = 0; // OK
 
   // single-ported ROM
-  rom1p1r #(ADDR_WIDTH, `XLEN, `FPGA)
+  rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
     memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule
-  
diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
index a2255af5d..ad1e0f259 100644
--- a/src/uncore/uartPC16550D.sv
+++ b/src/uncore/uartPC16550D.sv
@@ -7,11 +7,11 @@
 // Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs
 //          Emulates interface of Texas Instruments PC16550D
 //          https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf
-//          Compatible with UART in Imperas Virtio model ***
+//          Compatible with UART in Imperas Virtio model
 //
 //  Compatible with most of PC16550D with the following known exceptions:
 //   Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
-//   Timeout not yet implemented***
+//   Timeout not yet implemented
 // 
 // Documentation: RISC-V System on Chip Design Chapter 15
 //
@@ -33,10 +33,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 /* verilator lint_off UNOPTFLAT */
 
-module uartPC16550D(
+module uartPC16550D #(parameter UART_PRESCALE) (
   // Processor Interface
   input  logic       PCLK, PRESETn,                  // UART clock and active low reset
   input  logic [2:0] A,                              // address input (8 registers)
@@ -46,7 +45,7 @@ module uartPC16550D(
   output logic       INTR, TXRDYb, RXRDYb,           // interrupt and ready lines
   // Clocks
   output logic       BAUDOUTb,                       // active low baud clock
-  input logic         RCLK,                           // usually BAUDOUTb tied to RCLK externally
+  input logic        RCLK,                           // usually BAUDOUTb tied to RCLK externally
   // E1A Driver
   input  logic       SIN, DSRb, DCDb, CTSb, RIb,     // UART external serial and flow-control inputs
   output logic       SOUT, RTSb, DTRb, OUT1b, OUT2b  // UART external serial and flow-control outputs
@@ -72,9 +71,9 @@ module uartPC16550D(
   logic        DLAB; // Divisor Latch Access Bit (LCR bit 7)
 
   // Baud and rx/tx timing
-  logic        baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
-  logic [16+`UART_PRESCALE-1:0] baudcount;
-  logic [3:0]                   rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
+  logic                         baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
+  logic [16+UART_PRESCALE-1:0]  baudcount;
+  logic [3:0]                   rxoversampledcnt, txoversampledcnt;  // count oversampled-by-16
   logic [3:0]                   rxbitsreceived, txbitssent;
   statetype rxstate, txstate;
 
@@ -123,6 +122,7 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // Input synchronization: 2-stage synchronizer
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK) begin
     {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
     {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
@@ -133,11 +133,12 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // Register interface (Table 1, note some are read only and some write only)
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn) 
     if (~PRESETn) begin // Table 3 Reset Configuration
       IER <= #1 4'b0;
       FCR <= #1 8'b0;
-      if (`QEMU) LCR <= #1 8'b0; else LCR <= #1 8'b11; // fpga only **** BUG
+      LCR <= #1 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed.
       MCR <= #1 5'b0;
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
@@ -163,13 +164,13 @@ module uartPC16550D(
       if (~MEMWb & (A == 3'b101))
         LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3
       else begin
-        LSR[0] <= #1 rxdataready; // Data ready
-        LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error
-        LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error
-        LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error
-        LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator
-        LSR[5] <= #1 THRE; // THRE
-        LSR[6] <= #1 ~txsrfull & THRE; //  TEMT
+        LSR[0]   <= #1 rxdataready; // Data ready
+        LSR[1]   <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error
+        LSR[2]   <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error
+        LSR[3]   <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error
+        LSR[4]   <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator
+        LSR[5]   <= #1 THRE; // THRE
+        LSR[6]   <= #1 ~txsrfull & THRE; //  TEMT
         if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error
       end
 
@@ -205,10 +206,11 @@ module uartPC16550D(
   // consider switching to same fixed-frequency reference clock used for TIME register
   // prescale by factor of 2^UART_PRESCALE to allow for high-frequency reference clock
   // Unlike PC16550D, this unit is hardwired with same rx and tx baud clock
-  // *** add table of scale factors to get 16x uart clk
+  // For example, with PCLK = 320 MHz, UART_PRESCALE = 5, DLM = 0, DLL = 65, 
+  // 320 MHz system clock is divided by 65 x 2^5.  The UART clock 16x oversamples
+  // the data, so the baud rate is 320x10^6 / (65 x 2^5 x 16) = 9615 Hz, which is
+  // close enough to 9600 baud to stay synchronized over the duration of one character.
   ///////////////////////////////////////////
-  // Ross Thompson: Found a bug.  If the baud rate dividers DLM, and DLL are reloaded
-  // the baudcount is not reset to  {DLM, DLL, UART_PRESCALE}
   always_ff @(posedge PCLK, negedge PRESETn) 
     if (~PRESETn) begin
       baudcount <= #1 1;
@@ -225,7 +227,7 @@ module uartPC16550D(
       baudcount <= #1 baudpulseComb ? 1 :  baudcount +1;
     end
 
-  assign baudpulseComb = (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}});
+  assign baudpulseComb = (baudcount == {DLM, DLL, {(UART_PRESCALE){1'b0}}});
   
   assign txbaudpulse = baudpulse;
   assign BAUDOUTb = ~baudpulse;
@@ -234,17 +236,18 @@ module uartPC16550D(
   ///////////////////////////////////////////
   // receive timing and control
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
-      rxoversampledcnt <= #1 0;
-      rxstate <= #1 UART_IDLE;
-      rxbitsreceived <= #1 0;
-      rxtimeoutcnt <= #1 0;
+      rxoversampledcnt   <= #1 0;
+      rxstate            <= #1 UART_IDLE;
+      rxbitsreceived     <= #1 0;
+      rxtimeoutcnt       <= #1 0;
     end else begin
       if (rxstate == UART_IDLE & ~SINsync) begin // got start bit
-        rxstate <= #1 UART_ACTIVE;
+        rxstate          <= #1 UART_ACTIVE;
         rxoversampledcnt <= #1 0;
-        rxbitsreceived <= #1 0;
+        rxbitsreceived   <= #1 0;
         if (~rxfifotimeout) rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf
       end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin
         rxoversampledcnt <= #1 rxoversampledcnt + 1;  // 16x oversampled counter
@@ -256,18 +259,17 @@ module uartPC16550D(
       end
       // timeout counting
       if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= #1 0; // reset timeout on read
-      else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
+      else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // may not be right
     end
 
-  // ***explain why
-  if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10);  // implies rxstate = UART_ACTIVE
-  else      assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000);     // implies rxstate = UART_ACTIVE      
+  assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000);     // implies rxstate = UART_ACTIVE      
  
   assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit 
   
   ///////////////////////////////////////////
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
     else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
@@ -283,11 +285,11 @@ module uartPC16550D(
   assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit
 
   // ERROR CONDITIONS
-  assign rxparity = ^rxdata;
-  assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
+  assign rxparity     = ^rxdata;
+  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
   assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full 
   assign rxframingerr = ~rxstopbit; // framing error if no stop bit
-  assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
+  assign rxbreak      = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
 
   // receive FIFO and register
   always_ff @(posedge PCLK)
@@ -299,7 +301,7 @@ module uartPC16550D(
       end else if (rxstate == UART_DONE) begin
         RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
         if (rxoverrunerr) $warning("UART RX Overrun Err\n");
-        if (rxparityerr) $warning("UART RX Parity Err\n");
+        if (rxparityerr)  $warning("UART RX Parity Err\n");
         if (rxframingerr) $warning("UART RX Framing Err\n");
         if (fifoenabled) begin
           rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
@@ -327,7 +329,7 @@ module uartPC16550D(
                          (rxfifohead + 16 - rxfifotail);
   // verilator lint_on WIDTH
   assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
-  assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; *** probably not right yet
+  assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet
   //assign rxfifotimeout = 0; // disabled pending fix
 
   // detect any errors in rx fifo
@@ -340,14 +342,14 @@ module uartPC16550D(
     else        assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
   end
   for (i=0; i<16; i++) begin:rx
-    assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
+    assign RXerrbit[i]  = |rxfifo[i][10:8]; // are any of the error conditions set?
     assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
   /*      if (i > 0)
       assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
       else
       assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
   end
-  assign rxfifohaserr = |(RXerrbit & rxfullbit);
+  assign rxfifohaserr   = |(RXerrbit & rxfullbit);
 
   // receive buffer register and ready bit
   always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
@@ -362,22 +364,23 @@ module uartPC16550D(
       if (fifodmamodesel) RXRDYb = ~rxfifodmaready;
       else                RXRDYb = rxfifoempty;
     end else begin
-      RBR = RXBR;
+      RBR    = RXBR;
       RXRDYb = ~rxdataready;
     end
 
   ///////////////////////////////////////////
   // transmit timing and control
   ///////////////////////////////////////////
+  
   always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
       txoversampledcnt <= #1 0;
-      txstate <= #1 UART_IDLE;
-      txbitssent <= #1 0;
+      txstate          <= #1 UART_IDLE;
+      txbitssent       <= #1 0;
     end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting
-      txstate <= #1 UART_ACTIVE;
+      txstate          <= #1 UART_ACTIVE;
       txoversampledcnt <= #1 1;
-      txbitssent <= #1 0;
+      txbitssent       <= #1 0;
     end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
       txoversampledcnt <= #1 txoversampledcnt + 1; 
       if (txnextbit) begin // transmit at end of phase
@@ -389,17 +392,16 @@ module uartPC16550D(
     end
 
   assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) - 1
-  // *** explain; is this necessary?
-  if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00);  // implies txstate = UART_ACTIVE
-  else       assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
+  assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
 
   ///////////////////////////////////////////
   // transmit holding register, shift register, FIFO
   ///////////////////////////////////////////
+  
   always_comb begin // compute value for parity and tx holding register
     nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
     case (LCR[1:0]) // compute parity from appropriate number of bits
-      2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; // *** check polarity
+      2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; 
       2'b01: txparity = ^nexttxdata[5:0] ^ ~evenparitysel; 
       2'b10: txparity = ^nexttxdata[6:0] ^ ~evenparitysel; 
       2'b11: txparity = ^nexttxdata[7:0] ^ ~evenparitysel; 
@@ -427,9 +429,9 @@ module uartPC16550D(
       if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo
         if (fifoenabled) begin
           txfifo[txfifohead] <= #1 Din;
-          txfifohead <= #1 txfifohead + 1;          
+          txfifohead         <= #1 txfifohead + 1;          
         end else begin 
-          TXHR <= #1 Din;
+          TXHR     <= #1 Din;
           txhrfull <= #1 1;
         end
         $write("%c",Din); // for testbench
@@ -437,12 +439,12 @@ module uartPC16550D(
       if (txstate == UART_IDLE) begin // move data into tx shift register if available
         if (fifoenabled) begin 
           if (~txfifoempty & ~txsrfull) begin
-            txsr <= #1 txdata;
+            txsr       <= #1 txdata;
             txfifotail <= #1 txfifotail+1;
-            txsrfull <= #1 1;
+            txsrfull   <= #1 1;
           end
         end else if (txhrfull) begin
-          txsr <= #1 txdata;
+          txsr     <= #1 txdata;
           txhrfull <= #1 0;
           txsrfull <= #1 1;
         end
@@ -471,12 +473,11 @@ module uartPC16550D(
     HeadPointerLastMove <= 1'b0;
   end
 
-  assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove;
+  assign txfifoempty   = (txfifohead == txfifotail) & ~HeadPointerLastMove;
   // verilator lint_off WIDTH
   assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : 
                          (txfifohead + 16 - txfifotail);
   // verilator lint_on WIDTH
-  //assign txfifofull = (txfifoentries == 4'b1111);
   assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove;
 
   // transmit buffer ready bit
@@ -491,11 +492,12 @@ module uartPC16550D(
 
   // Transmitter pin 
   assign SOUTbit = txsr[11]; // transmit most significant bit
-  assign SOUT = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break 
+  assign SOUT    = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break 
 
   ///////////////////////////////////////////
   // interrupts
   ///////////////////////////////////////////
+  
   assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
   assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
   assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready; 
@@ -534,15 +536,15 @@ module uartPC16550D(
   // modem control logic
   ///////////////////////////////////////////
 
-  assign loop = MCR[4]; 
+  assign loop  = MCR[4]; 
   assign DTRb  = ~MCR[0] | loop; // disable modem signals in loopback mode
   assign RTSb  = ~MCR[1] | loop;
   assign OUT1b = ~MCR[2] | loop;
   assign OUT2b = ~MCR[3] | loop;
 
   assign DLAB = LCR[7];
-  assign evenparitysel = LCR[4];
-  assign fifoenabled = FCR[0];
+  assign evenparitysel  = LCR[4];
+  assign fifoenabled    = FCR[0];
   assign fifodmamodesel = FCR[3];
   always_comb
     case (FCR[7:6]) 
diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
index 5c0ec1bd5..130d7503e 100644
--- a/src/uncore/uart_apb.sv
+++ b/src/uncore/uart_apb.sv
@@ -28,21 +28,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module uart_apb (
-  input  logic             PCLK, PRESETn,
-  input  logic             PSEL,
-  input  logic [2:0]       PADDR, 
-  input  logic [`XLEN-1:0] PWDATA,
-  input  logic [`XLEN/8-1:0] PSTRB,
-  input  logic             PWRITE,
-  input  logic             PENABLE,
-  output logic [`XLEN-1:0] PRDATA,
-  output logic             PREADY,
-  input  logic             SIN, DSRb, DCDb, CTSb, RIb,    // from E1A driver from RS232 interface
-  output logic             SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
-  output logic             OUT1b, OUT2b, INTR, TXRDYb, RXRDYb);         // to CPU
+module uart_apb import cvw::*; #(parameter cvw_t P) (
+  input  logic                PCLK, PRESETn,
+  input  logic                PSEL,
+  input  logic [2:0]          PADDR, 
+  input  logic [P.XLEN-1:0]   PWDATA,
+  input  logic [P.XLEN/8-1:0] PSTRB,
+  input  logic                PWRITE,
+  input  logic                PENABLE,
+  output logic [P.XLEN-1:0]   PRDATA,
+  output logic                PREADY,
+  input  logic                SIN, DSRb, DCDb, CTSb, RIb,           // from E1A driver from RS232 interface
+  output logic                SOUT, RTSb, DTRb,                     // to E1A driver to RS232 interface
+  output logic                OUT1b, OUT2b, INTR, TXRDYb, RXRDYb);  // to CPU
 
   // UART interface signals
   logic [2:0]      entry;
@@ -51,12 +49,12 @@ module uart_apb (
 
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
   assign memread  = ~PWRITE & PENABLE & PSEL;  
-  assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
-  assign entry = PADDR[2:0];
-  assign MEMRb = ~memread;
-  assign MEMWb = ~memwrite;
+  assign PREADY   = 1'b1; // CLINT never takes >1 cycle to respond
+  assign entry    = PADDR[2:0];
+  assign MEMRb    = ~memread;
+  assign MEMWb    = ~memwrite;
 
-  if (`XLEN == 64) begin:uart
+  if (P.XLEN == 64) begin:uart
     always_comb begin
       PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
       case (entry)
@@ -83,8 +81,7 @@ module uart_apb (
   end
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
-  // *** make sure reads don't occur on UART unless fully selected because they could change state.  This applies to all peripherals
-  uartPC16550D u(  
+  uartPC16550D #(P.UART_PRESCALE) u(  
     // Processor Interface
     .PCLK, .PRESETn,
     .A(entry), .Din, 
@@ -99,4 +96,3 @@ module uart_apb (
 );
 
 endmodule
-
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index 4f00a3da4..b703d72fe 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -27,118 +27,116 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module uncore (
+module uncore import cvw::*;  #(parameter cvw_t P)(
   // AHB Bus Interface
-  input  logic                HCLK, HRESETn,
-  input  logic                TIMECLK,
-  input  logic [`PA_BITS-1:0] HADDR,
-  input  logic [`AHBW-1:0]    HWDATA,
-  input  logic [`XLEN/8-1:0]  HWSTRB,
-  input  logic                HWRITE,
-  input  logic [2:0]          HSIZE,
-  input  logic [2:0]          HBURST,
-  input  logic [3:0]          HPROT,
-  input  logic [1:0]          HTRANS,
-  input  logic                HMASTLOCK,
-  input  logic [`AHBW-1:0]    HRDATAEXT,
-  input  logic                HREADYEXT, HRESPEXT,
-  output logic [`AHBW-1:0]    HRDATA,
-  output logic                HREADY, HRESP,
-  output logic                HSELEXT,
+  input  logic                 HCLK, HRESETn,
+  input  logic                 TIMECLK,
+  input  logic [P.PA_BITS-1:0] HADDR,
+  input  logic [P.AHBW-1:0]    HWDATA,
+  input  logic [P.XLEN/8-1:0]  HWSTRB,
+  input  logic                 HWRITE,
+  input  logic [2:0]           HSIZE,
+  input  logic [2:0]           HBURST,
+  input  logic [3:0]           HPROT,
+  input  logic [1:0]           HTRANS,
+  input  logic                 HMASTLOCK,
+  input  logic [P.AHBW-1:0]    HRDATAEXT,
+  input  logic                 HREADYEXT, HRESPEXT,
+  output logic [P.AHBW-1:0]    HRDATA,
+  output logic                 HREADY, HRESP,
+  output logic                 HSELEXT,
   // peripheral pins          
-  output logic                MTimerInt, MSwInt,         // Timer and software interrupts from CLINT
-  output logic                MExtInt, SExtInt,          // External interrupts from PLIC
-  output logic [63:0]         MTIME_CLINT,               // MTIME, from CLINT
-  input  logic [31:0]         GPIOIN,                // GPIO pin input value
-  output logic [31:0]         GPIOOUT, GPIOEN,   // GPIO pin output value and enable
-  input  logic                UARTSin,                   // UART serial input
-  output logic                UARTSout,                  // UART serial output
-  output logic                SDCCmdOut,                 // SD Card command output
-  output logic                SDCCmdOE,                  // SD Card command output enable
-  input  logic                SDCCmdIn,                  // SD Card command input
-  input  logic [3:0]          SDCDatIn,                  // SD Card data input
-  output logic                SDCCLK                     // SD Card clock
+  output logic                 MTimerInt, MSwInt,         // Timer and software interrupts from CLINT
+  output logic                 MExtInt, SExtInt,          // External interrupts from PLIC
+  output logic [63:0]          MTIME_CLINT,               // MTIME, from CLINT
+  input  logic [31:0]          GPIOIN,                    // GPIO pin input value
+  output logic [31:0]          GPIOOUT, GPIOEN,           // GPIO pin output value and enable
+  input  logic                 UARTSin,                   // UART serial input
+  output logic                 UARTSout,                  // UART serial output
+  output logic                 SDCCmdOut,                 // SD Card command output
+  output logic                 SDCCmdOE,                  // SD Card command output enable
+  input  logic                 SDCCmdIn,                  // SD Card command input
+  input  logic [3:0]           SDCDatIn,                  // SD Card data input
+  output logic                 SDCCLK                     // SD Card clock
 );
   
-  logic [`XLEN-1:0]           HREADRam, HREADSDC;
+  logic [P.XLEN-1:0]           HREADRam, HREADSDC;
 
-  logic [10:0]                HSELRegions;
-  logic                       HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
-  logic                       HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
-  logic                       HRESPRam,  HRESPSDC;
-  logic                       HREADYRam, HRESPSDCD;
-  logic [`XLEN-1:0]           HREADBootRom; 
-  logic                       HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
-  logic                       HSELNoneD;
-  logic                       UARTIntr,GPIOIntr;
-  logic                       SDCIntM;
+  logic [10:0]                 HSELRegions;
+  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
+  logic                        HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
+  logic                        HRESPRam,  HRESPSDC;
+  logic                        HREADYRam, HRESPSDCD;
+  logic [P.XLEN-1:0]           HREADBootRom; 
+  logic                        HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
+  logic                        HSELNoneD;
+  logic                        UARTIntr,GPIOIntr;
+  logic                        SDCIntM;
   
-  logic                       PCLK, PRESETn, PWRITE, PENABLE;
-  logic [3:0]                 PSEL, PREADY;
-  logic [31:0]                PADDR;
-  logic [`XLEN-1:0]           PWDATA;
-  logic [`XLEN/8-1:0]         PSTRB;
-  logic [3:0][`XLEN-1:0]      PRDATA;
-  logic [`XLEN-1:0]           HREADBRIDGE;
-  logic                       HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
+  logic                        PCLK, PRESETn, PWRITE, PENABLE;
+  logic [3:0]                  PSEL, PREADY;
+  logic [31:0]                 PADDR;
+  logic [P.XLEN-1:0]           PWDATA;
+  logic [P.XLEN/8-1:0]         PSTRB;
+  logic [3:0][P.XLEN-1:0]      PRDATA;
+  logic [P.XLEN-1:0]           HREADBRIDGE;
+  logic                        HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
 
   // Determine which region of physical memory (if any) is being accessed
   // Use a trimmed down portion of the PMA checker - only the address decoders
   // Set access types to all 1 as don't cares because the MMU has already done access checking
-  adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
+  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
   assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1];
 
   // AHB -> APB bridge
-  ahbapbbridge #(4) ahbapbbridge (
+  ahbapbbridge #(P, 4) ahbapbbridge (
     .HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
     .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
     .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
   assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected
                 
   // on-chip RAM
-  if (`UNCORE_RAM_SUPPORTED) begin : ram
-    ram_ahb #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
+  if (P.UNCORE_RAM_SUPPORTED) begin : ram
+    ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE)) ram (
       .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
       .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
   end
 
- if (`BOOTROM_SUPPORTED) begin : bootrom
-    rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
+ if (P.BOOTROM_SUPPORTED) begin : bootrom
+    rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE))
     bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
       .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
   end
 
   // memory-mapped I/O peripherals
-  if (`CLINT_SUPPORTED == 1) begin : clint
-    clint_apb clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+  if (P.CLINT_SUPPORTED == 1) begin : clint
+    clint_apb #(P) clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
   end else begin : clint
     assign MTIME_CLINT = 0;
     assign MTimerInt = 0; assign MSwInt = 0;
   end
 
-  if (`PLIC_SUPPORTED == 1) begin : plic
-    plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+  if (P.PLIC_SUPPORTED == 1) begin : plic
+    plic_apb #(P) plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .MExtInt, .SExtInt);
   end else begin : plic
     assign MExtInt = 0;
     assign SExtInt = 0;
   end
 
-  if (`GPIO_SUPPORTED == 1) begin : gpio
-    gpio_apb gpio(
+  if (P.GPIO_SUPPORTED == 1) begin : gpio
+    gpio_apb #(P) gpio(
       .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), 
       .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr);
   end else begin : gpio
     assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0;
   end
-  if (`UART_SUPPORTED == 1) begin : uart
-    uart_apb uart(
+  if (P.UART_SUPPORTED == 1) begin : uart
+    uart_apb #(P) uart(
       .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), 
       .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
@@ -147,8 +145,8 @@ module uncore (
   end else begin : uart
     assign UARTSout = 0; assign UARTIntr = 0; 
   end
-  if (`SDC_SUPPORTED == 1) begin : sdc
-    SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
+  if (P.SDC_SUPPORTED == 1) begin : sdc
+    SDC #(P) SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
       .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
       // sdc interface
       .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
@@ -156,17 +154,17 @@ module uncore (
       .SDCIntM        
       );
   end else begin : sdc
-    assign SDCCLK = 0; 
+    assign SDCCLK    = 0; 
     assign SDCCmdOut = 0;
-    assign SDCCmdOE = 0;
+    assign SDCCmdOE  = 0;
   end
 
   // AHB Read Multiplexer
-  assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
-                  ({`XLEN{HSELEXTD}} & HRDATAEXT) |   
-                  ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
-                  ({`XLEN{HSELBootRomD}} & HREADBootRom) |
-                  ({`XLEN{HSELSDCD}} & HREADSDC);
+  assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
+                  ({P.XLEN{HSELEXTD}} & HRDATAEXT) |   
+                  ({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) |
+                  ({P.XLEN{HSELBootRomD}} & HREADBootRom) |
+                  ({P.XLEN{HSELSDCD}} & HREADSDC);
 
   assign HRESP = HSELRamD & HRESPRam |
                  HSELEXTD & HRESPEXT |
@@ -191,4 +189,3 @@ module uncore (
     HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
   flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
 endmodule
-
diff --git a/src/wally/cvw.sv b/src/wally/cvw.sv
deleted file mode 100644
index eb6146283..000000000
--- a/src/wally/cvw.sv
+++ /dev/null
@@ -1,215 +0,0 @@
-//////////////////////////////////////////
-// cvw.sv
-//
-// Written: David_Harris@hmc.edu 27 January 2022
-//
-// Purpose: package with shared CORE-V-Wally global parameters
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// Usiing global `define statements isn't ideal in a large SystemVerilog system because
-// of the risk of `define name conflicts across different subsystems.
-// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
-// that is referenced by all Wally modules but not by other subsystems.
-
-// Load configuration-specific information
-`include "wally-config.vh"
-
-// Place configuration in a package
-package cvw;
-  parameter XLEN = `XLEN;
-  parameter FPGA = `FPGA;
-  parameter QEMU = `QEMU;
-  parameter IEEE754 = `IEEE754;
-  parameter MISA = `MISA;
-  parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
-  parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED;
-  parameter COUNTERS = `COUNTERS;
-  parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
-  parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
-  parameter BUS_SUPPORTED = `BUS_SUPPORTED;
-  parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED;
-  parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED;
-  parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
-  parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
-  parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
-  parameter ITLB_ENTRIES = `ITLB_ENTRIES;
-  parameter DTLB_ENTRIES = `DTLB_ENTRIES;
-  parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS;
-  parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES;
-  parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS;
-  parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS;
-  parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES;
-  parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS;
-  parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE;
-  parameter IDIV_ON_FPU = `IDIV_ON_FPU;
-  parameter PMP_ENTRIES = `PMP_ENTRIES;
-  parameter RESET_VECTOR = `RESET_VECTOR;
-  parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT;
-  parameter DTIM_SUPPORTED = `DTIM_SUPPORTED;
-  parameter DTIM_BASE = `DTIM_BASE;
-  parameter DTIM_RANGE = `DTIM_RANGE;
-  parameter IROM_SUPPORTED = `IROM_SUPPORTED;
-  parameter IROM_BASE = `IROM_BASE;
-  parameter IROM_RANGE = `IROM_RANGE;
-  parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED;
-  parameter BOOTROM_BASE = `BOOTROM_BASE;
-  parameter BOOTROM_RANGE = `BOOTROM_RANGE;
-  parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED;
-  parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE;
-  parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE;
-  parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED;
-  parameter EXT_MEM_BASE = `EXT_MEM_BASE;
-  parameter EXT_MEM_RANGE = `EXT_MEM_RANGE;
-  parameter CLINT_SUPPORTED = `CLINT_SUPPORTED;
-  parameter CLINT_BASE = `CLINT_BASE;
-  parameter CLINT_RANGE = `CLINT_RANGE;
-  parameter GPIO_SUPPORTED = `GPIO_SUPPORTED;
-  parameter GPIO_BASE = `GPIO_BASE;
-  parameter GPIO_RANGE = `GPIO_RANGE;
-  parameter UART_SUPPORTED = `UART_SUPPORTED;
-  parameter UART_BASE = `UART_BASE;
-  parameter UART_RANGE = `UART_RANGE;
-  parameter PLIC_SUPPORTED = `PLIC_SUPPORTED;
-  parameter PLIC_BASE = `PLIC_BASE;
-  parameter PLIC_RANGE = `PLIC_RANGE;
-  parameter SDC_SUPPORTED = `SDC_SUPPORTED;
-  parameter SDC_BASE = `SDC_BASE;
-  parameter SDC_RANGE = `SDC_RANGE;
-  parameter AHBW = `AHBW;
-  parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
-  parameter UART_PRESCALE = `UART_PRESCALE;
-  parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
-  parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
-  parameter PLIC_UART_ID = `PLIC_UART_ID;
-  parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
-  parameter BPRED_TYPE = `BPRED_TYPE;
-  parameter BPRED_SIZE = `BPRED_SIZE;
-  parameter SVADU_SUPPORTED = `SVADU_SUPPORTED;
-//  parameter  = `;
-
-
-  // Shared parameters
-
-  // constants defining different privilege modes
-  // defined in Table 1.1 of the privileged spec
-  parameter M_MODE = (2'b11);
-  parameter S_MODE = (2'b01);
-  parameter U_MODE = (2'b00);
-
-  // Virtual Memory Constants
-  parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9);
-  parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS));
-  parameter PPN_BITS = (`XLEN==32 ? 22 : 44);
-  parameter PA_BITS = (`XLEN==32 ? 34 : 56);
-  parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4);
-  parameter ASID_BASE = (`XLEN==32 ? 22 : 44);
-  parameter ASID_BITS = (`XLEN==32 ? 9 : 16);
-
-  // constants to check SATP_MODE against
-  // defined in Table 4.3 of the privileged spec
-  parameter NO_TRANSLATE = 0;
-  parameter SV32 = 1;
-  parameter SV39 = 8;
-  parameter SV48 = 9;
-
-  // macros to define supported modes
-  parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1);
-  parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA
-  parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1);
-  parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1);
-  parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1);
-  parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1);
-  parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1);
-  parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1);
-  parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1);
-  parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1);
-  parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1);
-  // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-
-  // logarithm of XLEN, used for number of index bits to select
-  parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6);
-
-  // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
-  parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8);
-
-  // Floating point constants for Quad, Double, Single, and Half precisions
-  parameter Q_LEN = 32'd128;
-  parameter Q_NE = 32'd15;
-  parameter Q_NF = 32'd112;
-  parameter Q_BIAS = 32'd16383;
-  parameter Q_FMT = 2'd3;
-  parameter D_LEN = 32'd64;
-  parameter D_NE = 32'd11;
-  parameter D_NF = 32'd52;
-  parameter D_BIAS = 32'd1023;
-  parameter D_FMT = 2'd1;
-  parameter S_LEN = 32'd32;
-  parameter S_NE = 32'd8;
-  parameter S_NF = 32'd23;
-  parameter S_BIAS = 32'd127;
-  parameter S_FMT = 2'd0;
-  parameter H_LEN = 32'd16;
-  parameter H_NE = 32'd5;
-  parameter H_NF = 32'd10;
-  parameter H_BIAS = 32'd15;
-  parameter H_FMT = 2'd2;
-
-  // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
-  parameter FLEN = (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `S_LEN);
-  parameter NE   = (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `S_NE);
-  parameter NF   = (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `S_NF);
-  parameter FMT  = (`Q_SUPPORTED ? 2'd3    : `D_SUPPORTED ? 2'd1    : 2'd0);
-  parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS);
-  
-  // Floating point constants needed for FPU paramerterization
-  parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED));
-  parameter FMTBITS = ((32)'(`FPSIZES>=3)+1);
-  parameter LEN1  = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN  : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN  : `H_LEN);
-  parameter NE1   = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE   : `H_NE);
-  parameter NF1   = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF   : `H_NF);
-  parameter FMT1  = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1    : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0    : 2'd2);
-  parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS);
-  parameter LEN2  = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN  : `H_LEN);
-  parameter NE2   = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE   : `H_NE);
-  parameter NF2   = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF   : `H_NF);
-  parameter FMT2  = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0    : 2'd2);
-  parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS);
-
-  // largest length in IEU/FPU
-  parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF));
-  parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN));
-  parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1));
-  parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)));
-  parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ));
-  parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)));
-
-  // division constants
-
-  parameter DIVN        = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input
-  parameter LOGR        = ($clog2(`RADIX));            // r = log(R)
-  parameter RK          = (`LOGR*`DIVCOPIES);          // r*k used for intdiv preproc
-  parameter LOGRK       = ($clog2(`RK));               // log2(r*k)
-  parameter FPDUR       = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4));
-  parameter DURLEN      = ($clog2(`FPDUR+1));
-  parameter DIVb        = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b)
-  parameter DIVBLEN     = ($clog2(`DIVb+1)-1);
-  parameter DIVa        = (`DIVb+1-`XLEN);             // used for idiv on fpu
-
-endpackage
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index ee5df5956..793ea5777 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -26,21 +26,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-//import cvw::*;  // global CORE-V-Wally parameters
-`include "wally-config.vh"
-
-module wallypipelinedcore (
+module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    input  logic                  clk, reset,
    // Privileged
    input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
    input  logic [63:0]           MTIME_CLINT, 
    // Bus Interface
-   input  logic [`AHBW-1:0]      HRDATA,
+   input  logic [P.AHBW-1:0]     HRDATA,
    input  logic                  HREADY, HRESP,
    output logic                  HCLK, HRESETn,
-   output logic [`PA_BITS-1:0]   HADDR,
-   output logic [`AHBW-1:0]      HWDATA,
-   output logic [`XLEN/8-1:0]    HWSTRB,
+   output logic [P.PA_BITS-1:0]  HADDR,
+   output logic [P.AHBW-1:0]     HWDATA,
+   output logic [P.XLEN/8-1:0]   HWSTRB,
    output logic                  HWRITE,
    output logic [2:0]            HSIZE,
    output logic [2:0]            HBURST,
@@ -58,15 +55,15 @@ module wallypipelinedcore (
   logic                          IntDivE, W64E;
   logic                          CSRReadM, CSRWriteM, PrivilegedM;
   logic [1:0]                    AtomicM;
-  logic [`XLEN-1:0]              ForwardedSrcAE, ForwardedSrcBE;
-  logic [`XLEN-1:0]              SrcAM;
+  logic [P.XLEN-1:0]             ForwardedSrcAE, ForwardedSrcBE;
+  logic [P.XLEN-1:0]             SrcAM;
   logic [2:0]                    Funct3E;
   logic [31:0]                   InstrD;
   logic [31:0]                   InstrM, InstrOrigM;
-  logic [`XLEN-1:0]              PCSpillF, PCE, PCLinkE;
-  logic [`XLEN-1:0]              PCM;
-  logic [`XLEN-1:0]              CSRReadValW, MDUResultW;
-  logic [`XLEN-1:0]              UnalignedPCNextF, PC2NextF;
+  logic [P.XLEN-1:0]             PCSpillF, PCE, PCLinkE;
+  logic [P.XLEN-1:0]             PCM;
+  logic [P.XLEN-1:0]             CSRReadValW, MDUResultW;
+  logic [P.XLEN-1:0]             UnalignedPCNextF, PC2NextF;
   logic [1:0]                    MemRWM;
   logic                          InstrValidD, InstrValidE, InstrValidM;
   logic                          InstrMisalignedFaultM;
@@ -80,38 +77,42 @@ module wallypipelinedcore (
   logic                          DivBusyE;
   logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
   logic                          SquashSCW;
+  logic                          MDUActiveE;                      // Mul/Div instruction being executed
+  logic [3:0]                    ENVCFG_CBE;                      // Cache Block operation enables
+  logic [3:0]                    CMOpM;                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  logic                          IFUPrefetchE, LSUPrefetchM;      // instruction / data prefetch hints
 
   // floating point unit signals
   logic [2:0]                    FRM_REGW;
   logic [4:0]                    RdE, RdM, RdW;
   logic                          FPUStallD;
   logic                          FWriteIntE;
-  logic [`FLEN-1:0]              FWriteDataM;
-  logic [`XLEN-1:0]              FIntResM;  
-  logic [`XLEN-1:0]              FCvtIntResW; 
+  logic [P.FLEN-1:0]             FWriteDataM;
+  logic [P.XLEN-1:0]             FIntResM;  
+  logic [P.XLEN-1:0]             FCvtIntResW; 
   logic                          FCvtIntW; 
   logic                          FDivBusyE;
   logic                          FRegWriteM;
   logic                          FCvtIntStallD;
   logic                          FpLoadStoreM;
   logic [4:0]                    SetFflagsM;
-  logic [`XLEN-1:0]              FIntDivResultW;
+  logic [P.XLEN-1:0]             FIntDivResultW;
 
   // memory management unit signals
   logic                          ITLBWriteF;
   logic                          ITLBMissF;
-  logic [`XLEN-1:0]              SATP_REGW;
+  logic [P.XLEN-1:0]             SATP_REGW;
   logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
   logic [1:0]                    STATUS_MPP, STATUS_FS;
   logic [1:0]                    PrivilegeModeW;
-  logic [`XLEN-1:0]              PTE;
+  logic [P.XLEN-1:0]             PTE;
   logic [1:0]                    PageType;
   logic                          sfencevmaM;
   logic                          SelHPTW;
 
   // PMA checker signals
-  var logic [`PA_BITS-3:0]       PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0];
-  var logic [7:0]                PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
+  var logic [P.PA_BITS-3:0]      PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
+  var logic [7:0]                PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
 
   // IMem stalls
   logic                          IFUStallF;
@@ -119,14 +120,14 @@ module wallypipelinedcore (
 
   // cpu lsu interface
   logic [2:0]                    Funct3M;
-  logic [`XLEN-1:0]              IEUAdrE;
-  logic [`XLEN-1:0]              WriteDataM;
-  logic [`XLEN-1:0]              IEUAdrM;  
-  logic [`LLEN-1:0]              ReadDataW;  
+  logic [P.XLEN-1:0]             IEUAdrE;
+  logic [P.XLEN-1:0]             WriteDataM;
+  logic [P.XLEN-1:0]             IEUAdrM;  
+  logic [P.LLEN-1:0]             ReadDataW;  
   logic                          CommittedM;
 
   // AHB ifu interface
-  logic [`PA_BITS-1:0]           IFUHADDR;
+  logic [P.PA_BITS-1:0]          IFUHADDR;
   logic [2:0]                    IFUHBURST;
   logic [1:0]                    IFUHTRANS;
   logic [2:0]                    IFUHSIZE;
@@ -134,9 +135,9 @@ module wallypipelinedcore (
   logic                          IFUHREADY;
   
   // AHB LSU interface
-  logic [`PA_BITS-1:0]           LSUHADDR;
-  logic [`XLEN-1:0]              LSUHWDATA;
-  logic [`XLEN/8-1:0]            LSUHWSTRB;
+  logic [P.PA_BITS-1:0]          LSUHADDR;
+  logic [P.XLEN-1:0]             LSUHWDATA;
+  logic [P.XLEN/8-1:0]           LSUHWSTRB;
   logic                          LSUHWRITE;
   logic                          LSUHREADY;
   
@@ -165,7 +166,7 @@ module wallypipelinedcore (
   logic                          wfiM, IntPendingM;
 
   // instruction fetch unit: PC, branch prediction, instruction cache
-  ifu ifu(.clk, .reset,
+  ifu #(P) ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
     .InstrValidM, .InstrValidE, .InstrValidD,
     .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
@@ -188,64 +189,64 @@ module wallypipelinedcore (
     .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); 
     
   // integer execution unit: integer register file, datapath and controller
-  ieu ieu(.clk, .reset,
+  ieu #(P) ieu(.clk, .reset,
      // Decode Stage interface
-     .InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
+     .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
+     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
      // Memory stage interface
-     .SquashSCW, // from LSU
-     .MemRWM, // read/write control goes to LSU
-     .AtomicM, // atomic control goes to LSU
+     .SquashSCW,  // from LSU
+     .MemRWM,     // read/write control goes to LSU
+     .AtomicM,    // atomic control goes to LSU
      .WriteDataM, // Write data to LSU
-     .Funct3M, // size and signedness to LSU
-     .SrcAM, // to privilege and fpu
+     .Funct3M,    // size and signedness to LSU
+     .SrcAM,      // to privilege and fpu
      .RdE, .RdM, .FIntResM, .FlushDCacheM,
      .BranchD, .BranchE, .JumpD, .JumpE,
      // Writeback stage
-     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
+     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[P.XLEN-1:0]),
      .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
      .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
      .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); 
 
-  lsu lsu(
+  lsu #(P) lsu(
     .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
     // CPU interface
     .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
     .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
     .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
-    .ReadDataW, .FlushDCacheM,
+    .ReadDataW, .FlushDCacheM, .CMOpM, .LSUPrefetchM,
     // connected to ahb (all stay the same)
     .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
     .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
     // connect to csr or privilege and stay the same.
-    .PrivilegeModeW, .BigEndianM,          // connects to csr
-    .PMPCFG_ARRAY_REGW,     // connects to csr
-    .PMPADDR_ARRAY_REGW,    // connects to csr
+    .PrivilegeModeW, .BigEndianM, // connects to csr
+    .PMPCFG_ARRAY_REGW,           // connects to csr
+    .PMPADDR_ARRAY_REGW,          // connects to csr
     // hptw keep i/o
-    .SATP_REGW, // from csr
-    .STATUS_MXR, // from csr
-    .STATUS_SUM,  // from csr
-    .STATUS_MPRV,  // from csr            
-    .STATUS_MPP,  // from csr      
-    .sfencevmaM,                   // connects to privilege
-    .DCacheStallM,                  // connects to privilege
-    .LoadPageFaultM,   // connects to privilege
-    .StoreAmoPageFaultM, // connects to privilege
-    .LoadMisalignedFaultM, // connects to privilege
-    .LoadAccessFaultM,         // connects to privilege
-    .HPTWInstrAccessFaultF,         // connects to privilege
-    .StoreAmoMisalignedFaultM, // connects to privilege
-    .StoreAmoAccessFaultM,     // connects to privilege
+    .SATP_REGW,                   // from csr
+    .STATUS_MXR,                  // from csr
+    .STATUS_SUM,                  // from csr
+    .STATUS_MPRV,                 // from csr            
+    .STATUS_MPP,                  // from csr      
+    .sfencevmaM,                  // connects to privilege
+    .DCacheStallM,                // connects to privilege
+    .LoadPageFaultM,              // connects to privilege
+    .StoreAmoPageFaultM,          // connects to privilege
+    .LoadMisalignedFaultM,        // connects to privilege
+    .LoadAccessFaultM,            // connects to privilege
+    .HPTWInstrAccessFaultF,       // connects to privilege
+    .StoreAmoMisalignedFaultM,    // connects to privilege
+    .StoreAmoAccessFaultM,        // connects to privilege
     .InstrUpdateDAF,
     .PCSpillF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
     .LSUStallM);                    
 
-  if(`BUS_SUPPORTED) begin : ebu
-    ebu ebu(// IFU connections
+  if(P.BUS_SUPPORTED) begin : ebu
+    ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections
       .clk, .reset,
       // IFU interface
       .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
@@ -272,8 +273,8 @@ module wallypipelinedcore (
     .FlushD, .FlushE, .FlushM, .FlushW);    
 
   // privileged unit
-  if (`ZICSR_SUPPORTED) begin:priv
-    privileged priv(
+  if (P.ZICSR_SUPPORTED) begin:priv
+    privileged #(P) priv(
       .clk, .reset,
       .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
       .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF,
@@ -291,67 +292,67 @@ module wallypipelinedcore (
       .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
       .InstrAccessFaultF, .HPTWInstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
       .PrivilegeModeW, .SATP_REGW,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
+      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
+      .FRM_REGW, .ENVCFG_CBE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
-    assign CSRReadValW = 0;
+    assign CSRReadValW      = 0;
     assign UnalignedPCNextF = PC2NextF;
-    assign RetM = 0;
-    assign TrapM = 0;
-    assign wfiM = 0;
-    assign IntPendingM = 0;
-    assign sfencevmaM = 0;
-    assign BigEndianM = 0;
+    assign RetM             = 0;
+    assign TrapM            = 0;
+    assign wfiM             = 0;
+    assign IntPendingM      = 0;
+    assign sfencevmaM       = 0;
+    assign BigEndianM       = 0;
   end
 
   // multiply/divide unit
-  if (`M_SUPPORTED | `ZMMUL_SUPPORTED) begin:mdu
-    mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
+  if (P.M_SUPPORTED | P.ZMMUL_SUPPORTED) begin:mdu
+    mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
       .ForwardedSrcAE, .ForwardedSrcBE, 
-      .Funct3E, .Funct3M, .IntDivE, .W64E,
+      .Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
       .MDUResultW, .DivBusyE); 
   end else begin // no M instructions supported
     assign MDUResultW = 0; 
-    assign DivBusyE = 0;
+    assign DivBusyE   = 0;
   end
 
   // floating point unit
-  if (`F_SUPPORTED) begin:fpu
-    fpu fpu(
+  if (P.F_SUPPORTED) begin:fpu
+    fpu #(P) fpu(
       .clk, .reset,
-      .FRM_REGW, // Rounding mode from CSR
-      .InstrD, // instruction from IFU
-      .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
-      .ForwardedSrcAE, // Integer input being processed (from IEU)
-      .StallE, .StallM, .StallW, // stall signals from HZU
-      .FlushE, .FlushM, .FlushW, // flush signals from HZU
-      .RdE, .RdM, .RdW, // which FP register to write to (from IEU)
-      .STATUS_FS, // is floating-point enabled?
-      .FRegWriteM, // FP register write enable
+      .FRM_REGW,                           // Rounding mode from CSR
+      .InstrD,                             // instruction from IFU
+      .ReadDataW(ReadDataW[P.FLEN-1:0]),   // Read data from memory
+      .ForwardedSrcAE,                     // Integer input being processed (from IEU)
+      .StallE, .StallM, .StallW,           // stall signals from HZU
+      .FlushE, .FlushM, .FlushW,           // flush signals from HZU
+      .RdE, .RdM, .RdW,                    // which FP register to write to (from IEU)
+      .STATUS_FS,                          // is floating-point enabled?
+      .FRegWriteM,                         // FP register write enable
       .FpLoadStoreM,
-      .ForwardedSrcBE, // Integer input for intdiv
+      .ForwardedSrcBE,                     // Integer input for intdiv
       .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
-      .FPUStallD, // Stall the decode stage
-      .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
-      .FWriteDataM, // Data to be written to memory
-      .FIntResM, // data to be written to integer register
-      .FCvtIntResW, // fp -> int conversion result to be stored in int register
-      .FCvtIntW,   // fpu result selection
-      .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
-      .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
-      .SetFflagsM,        // FPU flags (to privileged unit)
+      .FPUStallD,                          // Stall the decode stage
+      .FWriteIntE, .FCvtIntE,              // integer register write enable, conversion operation
+      .FWriteDataM,                        // Data to be written to memory
+      .FIntResM,                           // data to be written to integer register
+      .FCvtIntResW,                        // fp -> int conversion result to be stored in int register
+      .FCvtIntW,                           // fpu result selection
+      .FDivBusyE,                          // Is the divide/sqrt unit busy (stall execute stage)
+      .IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
+      .SetFflagsM,                         // FPU flags (to privileged unit)
       .FIntDivResultW); 
-  end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign FPUStallD = 0;
-    assign FWriteIntE = 0; 
-    assign FCvtIntE = 0;
-    assign FIntResM = 0;
-    assign FCvtIntW = 0;
-    assign FDivBusyE = 0;
+  end else begin                           // no F_SUPPORTED or D_SUPPORTED; tie outputs low
+    assign FPUStallD        = 0;
+    assign FWriteIntE       = 0; 
+    assign FCvtIntE         = 0;
+    assign FIntResM         = 0;
+    assign FCvtIntW         = 0;
+    assign FDivBusyE        = 0;
     assign IllegalFPUInstrD = 1;
-    assign SetFflagsM = 0;
-    assign FpLoadStoreM = 0;
+    assign SetFflagsM       = 0;
+    assign FpLoadStoreM     = 0;
   end
   
 endmodule
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index 0e3632451..014b93687 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -26,22 +26,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-//import cvw::*;  // global CORE-V-Wally parameters
-`include "wally-config.vh"
-
-module wallypipelinedsoc (
+module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   input  logic                clk, 
   input  logic                reset_ext,        // external asynchronous reset pin
   output logic                reset,            // reset synchronized to clk to prevent races on release
   // AHB Interface
-  input  logic [`AHBW-1:0]    HRDATAEXT,
+  input  logic [P.AHBW-1:0]     HRDATAEXT,
   input  logic                HREADYEXT, HRESPEXT,
   output logic                HSELEXT,
   // outputs to external memory, shared with uncore memory
   output logic                HCLK, HRESETn,
-  output logic [`PA_BITS-1:0] HADDR,
-  output logic [`AHBW-1:0]    HWDATA,
-  output logic [`XLEN/8-1:0]  HWSTRB,
+  output logic [P.PA_BITS-1:0]  HADDR,
+  output logic [P.AHBW-1:0]     HWDATA,
+  output logic [P.XLEN/8-1:0]   HWSTRB,
   output logic                HWRITE,
   output logic [2:0]          HSIZE,
   output logic [2:0]          HBURST,
@@ -51,9 +48,9 @@ module wallypipelinedsoc (
   output logic                HREADY,
   // I/O Interface
   input  logic                TIMECLK,          // optional for CLINT MTIME counter
-  input  logic [31:0]         GPIOIN,       // inputs from GPIO
-  output logic [31:0]         GPIOOUT,      // output values for GPIO
-  output logic [31:0]         GPIOEN,       // output enables for GPIO
+  input  logic [31:0]         GPIOIN,           // inputs from GPIO
+  output logic [31:0]         GPIOOUT,          // output values for GPIO
+  output logic [31:0]         GPIOEN,           // output enables for GPIO
   input  logic                UARTSin,          // UART serial data input
   output logic                UARTSout,         // UART serial data output
   input  logic                SDCCmdIn,         // SDC Command input
@@ -64,7 +61,7 @@ module wallypipelinedsoc (
 );
 
   // Uncore signals
-  logic [`AHBW-1:0]           HRDATA;           // from AHB mux in uncore
+  logic [P.AHBW-1:0]            HRDATA;           // from AHB mux in uncore
   logic                       HRESP;            // response from AHB
   logic                       MTimerInt, MSwInt;// timer and software interrupts from CLINT
   logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
@@ -74,15 +71,15 @@ module wallypipelinedsoc (
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
    
   // instantiate processor and internal memories
-  wallypipelinedcore core(.clk, .reset,
+  wallypipelinedcore #(P) core(.clk, .reset,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
     .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
    );
 
   // instantiate uncore if a bus interface exists
-  if (`BUS_SUPPORTED) begin : uncore
-    uncore uncore(.HCLK, .HRESETn, .TIMECLK,
+  if (P.BUS_SUPPORTED) begin : uncore
+    uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
       .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, 
diff --git a/testbench/common/checksignature.sv b/testbench/common/checksignature.sv
new file mode 100644
index 000000000..7fb589bb6
--- /dev/null
+++ b/testbench/common/checksignature.sv
@@ -0,0 +1,26 @@
+///////////////////////////////////////////
+// checksignature.sv
+//
+// Written: David Harris David_Harris@hmc.edu
+// Modified: 14 June 2023
+//
+// Purpose: Verifies the memory signature.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv
index c986c2e51..7aebedea8 100644
--- a/testbench/common/functionName.sv
+++ b/testbench/common/functionName.sv
@@ -1,6 +1,8 @@
 ///////////////////////////////////////////
 // functionName.sv
 //
+// Written: Ross Thompson ross1728@gmail.com
+// 
 // Purpose: decode name of function
 // 
 // A component of the Wally configurable RISC-V project.
@@ -21,21 +23,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
+module FunctionName import cvw::*; #(parameter cvw_t P) (
+  input logic reset,
+  input logic clk,
+  input string ProgramAddrMapFile,
+  input string ProgramLabelMapFile
+  );
   
-  input logic reset;
-  input logic clk;
-  input string ProgramAddrMapFile;
-  input string ProgramLabelMapFile;
-
-  logic [`XLEN-1:0] ProgramAddrMapMemory [];
+  logic [P.XLEN-1:0] ProgramAddrMapMemory [];
   string 	    ProgramLabelMapMemory [integer];
   string 	    FunctionName;
   
 
-  logic [`XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
+  logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
   logic 	    StallD, StallE, StallM, FlushD, FlushE, FlushM;
   logic 		InstrValidM;
   integer 	    ProgramAddrIndex, ProgramAddrIndexQ;
@@ -53,21 +53,20 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not
   // erroneously change.
   // also need to hold the old value not an erroneously fetched PC.
-  flopenr #(`XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
-  flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
-  flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
-  flopenr #(`XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
+  flopenr #(P.XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
+  flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
+  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
+  flopenr #(P.XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
   assign PCM = InstrValidM ? PCM_temp : PCMOld;
-  
 
   task automatic bin_search_min;
-    input logic [`XLEN-1:0] pc;
-    input logic [`XLEN-1:0] length;
-    ref logic [`XLEN-1:0]   array [];
-    output logic [`XLEN-1:0] minval;
-    output     logic [`XLEN-1:0] mid;
+    input logic [P.XLEN-1:0] pc;
+    input logic [P.XLEN-1:0] length;
+    ref logic [P.XLEN-1:0]   array [];
+    output logic [P.XLEN-1:0] minval;
+    output     logic [P.XLEN-1:0] mid;
 
-    logic [`XLEN-1:0] 	     left, right;
+    logic [P.XLEN-1:0] 	     left, right;
 
     begin
       if ( pc == 0 ) begin
@@ -120,8 +119,8 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
 //  initial begin
   always @ (negedge reset) begin
 	// clear out the old mapping between programs.
-	foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i);	
-	foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i);
+    ProgramAddrMapMemory.delete();
+    ProgramLabelMapMemory.delete();
 
     $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
     // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
@@ -170,8 +169,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0;
   initial ProgramAddrIndex = '0;
 
-  assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
-  
+  always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
 
 endmodule // function_radix
 
diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
index dd993e715..8f6fbe869 100644
--- a/testbench/common/instrNameDecTB.sv
+++ b/testbench/common/instrNameDecTB.sv
@@ -30,13 +30,14 @@ module instrNameDecTB(
   logic [2:0] funct3;
   logic [6:0] funct7;
   logic [11:0] imm;
-  logic [4:0] rs2;
+  logic [4:0] rs2, rd;
 
   assign op = instr[6:0];
   assign funct3 = instr[14:12];
   assign funct7 = instr[31:25];
   assign imm = instr[31:20];
   assign rs2 = instr[24:20];
+  assign rd = instr[11:7];
 
   // it would be nice to add the operands to the name 
   // create another variable called decoded
@@ -54,14 +55,33 @@ module instrNameDecTB(
       10'b0010011_000: if (instr[31:15] == 0 & instr[11:7] ==0) name = "NOP/FLUSH";
                        else                                      name = "ADDI";
       10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
-                       else                      name = "ILLEGAL";
+                       else if (funct7[6:1] == 6'b010010) name = "BCLRI";
+                       else if (funct7[6:1] == 6'b011010) name = "BINVI";
+                       else if (funct7[6:1] == 6'b001010) name = "BSETI";
+                       else if (funct7 == 7'b0110000) begin
+                         case (rs2)
+                           5'b00000: name = "CLZ";
+                           5'b00010: name = "CPOP";
+                           5'b00001: name = "CTZ";
+                           5'b00100: name = "SEXT.B";
+                           5'b00101: name = "SEXT.H";
+                           default:  name = "ILLEGAL";
+                         endcase
+                       end else                      name = "ILLEGAL";
       10'b0010011_010: name = "SLTI";
       10'b0010011_011: name = "SLTIU";
       10'b0010011_100: name = "XORI";
       10'b0010011_101: if (funct7[6:1] == 6'b000000)      name = "SRLI";
                        else if (funct7[6:1] == 6'b010000) name = "SRAI"; 
+                       else if (funct7[6:1] == 6'b011010 & rs2 == 5'b11000) name = "REV8";
+                       else if (funct7[6:1] == 6'b011000) name = "RORI";
+                       else if (funct7[6:1] == 6'b010010) name = "BEXTI";
+                       else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
                        else                           name = "ILLEGAL"; 
-      10'b0010011_110: name = "ORI";
+      10'b0010011_110: if      (rd == 0 & rs2 == 0) name = "PREFETCH.I";
+                       else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
+                       else if (rd == 0 & rs2 == 3) name = "PREFETCH.W";
+                       else                         name = "ORI";
       10'b0010011_111: name = "ANDI";
       10'b0010111_???: name = "AUIPC";
       10'b0100011_000: name = "SB";
@@ -69,22 +89,41 @@ module instrNameDecTB(
       10'b0100011_010: name = "SW";
       10'b0100011_011: name = "SD";
       10'b0011011_000: name = "ADDIW";
-      10'b0011011_001: name = "SLLIW";
+      10'b0011011_001: if      (funct7 == 7'b0000000 )name = "SLLIW";
+                       else if (funct7[6:1] == 6'b000010) name = "SLLI.UW";
+                       else if (funct7 == 7'b0110000) begin
+                         case (rs2)
+                           5'b00000:                  name = "CLZW";
+                           5'b00010:                  name = "CPOPW";
+                           5'b00001:                  name = "CTZW";
+                           default:                   name = "ILLEGAL";
+                         endcase
+                       end else                       name = "ILLEGAL";
       10'b0011011_101: if      (funct7 == 7'b0000000) name = "SRLIW";
                        else if (funct7 == 7'b0100000) name = "SRAIW";
+                       else if (funct7 == 7'b0110000) name = "RORIW";
                        else                           name = "ILLEGAL";
       10'b0111011_000: if      (funct7 == 7'b0000000) name = "ADDW";
                        else if (funct7 == 7'b0100000) name = "SUBW";
                        else if (funct7 == 7'b0000001) name = "MULW";
+                       else if (funct7 == 7'b0000100) name = "ADD.UW";
                        else                           name = "ILLEGAL";
       10'b0111011_001: if      (funct7 == 7'b0000000) name = "SLLW";
                        else if (funct7 == 7'b0000001) name = "DIVW";
+                       else if (funct7 == 7'b0110000) name = "ROLW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_010: if      (funct7 == 7'b0010000) name = "SH1ADD.UW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_100: if      (funct7 == 7'b0010000) name = "SH2ADD.UW";
+                       else if (funct7 == 7'b0000100) name = "ZEXT.H";
                        else                           name = "ILLEGAL";
       10'b0111011_101: if      (funct7 == 7'b0000000) name = "SRLW";
                        else if (funct7 == 7'b0100000) name = "SRAW";
                        else if (funct7 == 7'b0000001) name = "DIVUW";
+                       else if (funct7 == 7'b0110000) name = "RORW";
                        else                           name = "ILLEGAL";
       10'b0111011_110: if      (funct7 == 7'b0000001) name = "REMW";
+                       else if (funct7 == 7'b0010000) name = "SH3ADD.UW";
                        else                           name = "ILLEGAL";
       10'b0111011_111: if      (funct7 == 7'b0000001) name = "REMUW";
                        else                           name = "ILLEGAL";
@@ -94,25 +133,45 @@ module instrNameDecTB(
                        else                           name = "ILLEGAL"; 
       10'b0110011_001: if      (funct7 == 7'b0000000) name = "SLL";
                        else if (funct7 == 7'b0000001) name = "MULH";
+                       else if (funct7 == 7'b0110000) name = "ROL";
+                       else if (funct7 == 7'b0000101) name = "CLMUL";
+                       else if (funct7 == 7'b0100100) name = "BCLR";
+                       else if (funct7 == 7'b0110100) name = "BINV";
+                       else if (funct7 == 7'b0010100) name = "BSET";
                        else                           name = "ILLEGAL";
       10'b0110011_010: if      (funct7 == 7'b0000000) name = "SLT";
                        else if (funct7 == 7'b0000001) name = "MULHSU";
+                       else if (funct7 == 7'b0010000) name = "SH1ADD";
+                       else if (funct7 == 7'b0000101) name = "CLMULR";
                        else                           name = "ILLEGAL";
       10'b0110011_011: if      (funct7 == 7'b0000000) name = "SLTU";
                        else if (funct7 == 7'b0000001) name = "MULHU";
+                       else if (funct7 == 7'b0000101) name = "CLMULH";
                        else                           name = "ILLEGAL";
       10'b0110011_100: if      (funct7 == 7'b0000000) name = "XOR";
                        else if (funct7 == 7'b0000001) name = "DIV";
+                       else if (funct7 == 7'b0010000) name = "SH2ADD";
+                       else if (funct7 == 7'b0000101) name = "MIN";
+                       else if (funct7 == 7'b0100000) name = "ORN";
+                       else if (funct7 == 7'b0000100) name = "ZEXT.H";
                        else                           name = "ILLEGAL";
       10'b0110011_101: if      (funct7 == 7'b0000000) name = "SRL";
                        else if (funct7 == 7'b0000001) name = "DIVU";
                        else if (funct7 == 7'b0100000) name = "SRA";
+                       else if (funct7 == 7'b0000101) name = "MINU";
+                       else if (funct7 == 7'b0110000) name = "ROR";
+                       else if (funct7 == 7'b0100100) name = "BEXT";
                        else                           name = "ILLEGAL";
       10'b0110011_110: if      (funct7 == 7'b0000000) name = "OR";
                        else if (funct7 == 7'b0000001) name = "REM";
+                       else if (funct7 == 7'b0010000) name = "SH3ADD";
+                       else if (funct7 == 7'b0000101) name = "MAX";
+                       else if (funct7 == 7'b0100000) name = "XNOR";
                        else                           name = "ILLEGAL";
       10'b0110011_111: if      (funct7 == 7'b0000000) name = "AND";
                        else if (funct7 == 7'b0000001) name = "REMU";
+                       else if (funct7 == 7'b0000101) name = "MAXU";
+                       else if (funct7 == 7'b0100000) name = "ANDN";
                        else                           name = "ILLEGAL";
       10'b0110111_???: name = "LUI";
       10'b1100011_000: name = "BEQ";
@@ -160,7 +219,13 @@ module instrNameDecTB(
                        else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
                        else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
                        else                              name = "ILLEGAL";
-      10'b0001111_???: name = "FENCE";
+      10'b0001111_000: name = "FENCE";
+      10'b0001111_001: name = "FENCE.I";
+      10'b0001111_010: if      (instr[31:20] == 12'd0) name = "CBO.INVAL";
+                       else if (instr[31:20] == 12'd1) name = "CBO.CLEAN";
+                       else if (instr[31:20] == 12'd2) name = "CBO.FLUSH";
+                       else if (instr[31:20] == 12'd4) name = "CBO.ZERO";    
+                       else                            name = "ILLEGAL";                   
       10'b1000011_???: name = "FMADD";
       10'b1000111_???: name = "FMSUB";
       10'b1001011_???: name = "FNMSUB";
@@ -250,7 +315,10 @@ module instrNameDecTB(
                        else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
                        else if (funct7[6:2] == 5'b10100) name = "FEQ";
                        else                              name = "ILLEGAL";
+      /* verilator lint_off CASEOVERLAP */
+      // *** RT: definitely take a look at this.  This overlaps with 10'b1010011_000
       10'b1010011_???: if      (funct7[6:2] == 5'b00000) name = "FADD";
+      /* verilator lint_on CASEOVERLAP */
                        else if (funct7[6:2] == 5'b00001) name = "FSUB";
                        else if (funct7[6:2] == 5'b00010) name = "FMUL";
                        else if (funct7[6:2] == 5'b00011) name = "FDIV";
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
new file mode 100644
index 000000000..9dd2a7950
--- /dev/null
+++ b/testbench/common/loggers.sv
@@ -0,0 +1,240 @@
+///////////////////////////////////////////
+// loggers.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+// 
+// Purpose: Log branch instructions, log instruction fetches,
+//          log I$ misses, log data memory accesses, log D$ misses, and
+//          log other related operations
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module loggers import cvw::*; #(parameter cvw_t P,
+                                parameter TEST,
+                                parameter PrintHPMCounters,
+                                parameter I_CACHE_ADDR_LOGGER,
+                                parameter D_CACHE_ADDR_LOGGER,
+                                parameter BPRED_LOGGER) (
+  input logic  clk,
+  input logic  reset,
+  input logic  DCacheFlushStart,
+  input logic  DCacheFlushDone,                                                         
+//  input logic BeginSample,
+//  input logic StartSample,
+//  input logic EndSample,
+  input string memfilename
+  );
+  
+  // performance counter logging 
+  logic        BeginSample;
+  logic StartSample, EndSample;
+  if(PrintHPMCounters & P.ZICNTR_SUPPORTED) begin : HPMCSample
+    integer           HPMCindex;
+    logic             StartSampleFirst;
+    logic             StartSampleDelayed, BeginDelayed;
+    logic             EndSampleFirst, EndSampleDelayed;
+    logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
+
+    string  HPMCnames[] = '{"Mcycle",
+                            "------",
+                            "InstRet",
+                            "Br Count",
+                            "Jump Not Return",
+                            "Return",
+                            "BP Wrong",
+                            "BP Dir Wrong",
+                            "BP Target Wrong",
+                            "RAS Wrong",
+                            "Instr Class Wrong",
+                            "Load Stall",
+                            "Store Stall",
+                            "D Cache Access",
+                            "D Cache Miss",
+                            "D Cache Cycles",
+                            "I Cache Access",
+                            "I Cache Miss",
+                            "I Cache Cycles",
+                            "CSR Write",
+                            "FenceI",
+                            "SFenceVMA",
+                            "Interrupt",
+                            "Exception",
+                            "Divide Cycles"
+                          };
+
+    if(TEST == "embench") begin
+      // embench runs warmup then runs start_trigger
+      // embench end with stop_trigger.
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+
+    end else if(TEST == "coremark") begin
+      // embench runs warmup then runs start_trigger
+	    // embench end with stop_trigger.
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+
+    end else begin
+      // default start condiction is reset
+      // default end condiction is end of test (DCacheFlushDone)
+      assign StartSampleFirst = reset;
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
+
+      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
+      assign BeginSample = StartSampleFirst & ~BeginDelayed;
+
+    end
+    always @(negedge clk) begin
+      if(StartSample) begin
+        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
+          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
+        end
+      end
+      if(EndSample) begin
+        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
+          // unlikely to have more than 10M in any counter.
+          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
+        end
+      end
+    end
+  end
+
+  if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
+    int    file;
+    string LogFile;
+    logic  resetD, resetEdge;
+    logic  Enable;
+    logic  InvalDelayed, InvalEdge;
+    
+    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
+                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
+                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
+                    dut.core.ifu.bus.icache.icache.cachefsm.CacheEn &
+                    ~reset;
+    flop #(1) ResetDReg(clk, reset, resetD);
+    assign resetEdge = ~reset & resetD;
+
+    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
+    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
+
+    initial begin
+      LogFile = "ICache.log";
+      file = $fopen(LogFile, "w");
+      $fwrite(file, "BEGIN %s\n", memfilename);
+    end
+    string AccessTypeString, HitMissString;
+    always @(*) begin
+      HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
+                      dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
+    end
+    always @(posedge clk) begin
+    if(resetEdge) $fwrite(file, "TRAIN\n");
+    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
+    if(Enable) begin  // only log i cache reads
+      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
+    end
+    if(InvalEdge) $fwrite(file, "0 I X\n");
+    if(EndSample) $fwrite(file, "END %s\n", memfilename);
+    end
+  end
+
+
+  if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
+    int    file;
+    string LogFile;
+    logic  resetD, resetEdge;
+    logic  Enabled;
+    string AccessTypeString, HitMissString;
+
+    flop #(1) ResetDReg(clk, reset, resetD);
+    assign resetEdge = ~reset & resetD;
+    always @(*) begin
+      HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
+                      (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
+                      dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
+      AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
+                         dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
+                         dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
+                         dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
+                         "NULL";
+    end
+
+    assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
+                     ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
+                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
+                     dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &
+                     (AccessTypeString != "NULL");
+
+    initial begin
+      LogFile = "DCache.log";
+      file = $fopen(LogFile, "w");
+      $fwrite(file, "BEGIN %s\n", memfilename);
+    end
+    always @(posedge clk) begin
+      if(resetEdge) $fwrite(file, "TRAIN\n");
+      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
+      if(Enabled) begin
+        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
+      end
+      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
+      if(EndSample) $fwrite(file, "END %s\n", memfilename);
+    end
+  end
+
+  if (P.BPRED_SUPPORTED) begin : BranchLogger
+    if (BPRED_LOGGER) begin
+      string direction;
+      int    file;
+      logic  PCSrcM;
+      string LogFile;
+      logic  resetD, resetEdge;
+      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
+      flop #(1) ResetDReg(clk, reset, resetD);
+      assign resetEdge = ~reset & resetD;
+      initial begin
+        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
+        //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
+        file = $fopen(LogFile, "w");
+      end
+      always @(posedge clk) begin
+        if(resetEdge) $fwrite(file, "TRAIN\n");
+        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
+        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+          direction = PCSrcM ? "t" : "n";
+          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
+        end
+        if(EndSample) $fwrite(file, "END %s\n", memfilename);
+      end
+    end
+  end
+
+endmodule
diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv
new file mode 100644
index 000000000..987bbefea
--- /dev/null
+++ b/testbench/common/ramxdetector.sv
@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+// ramxdetector.sv
+//
+// Written: David_Harris@hmc.edu
+// Modified: 2 July 2023
+//
+// Purpose: Detects if the processor is attempting to read unitialized RAM
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ramxdetector #(parameter XLEN, LLEN) (
+  input  logic            clk,
+  input  logic            MemReadM,
+  input  logic            LSULoadAccessFaultM,
+  input  logic [LLEN-1:0] ReadDataM,
+  input  logic [XLEN-1:0] PCM,
+  input  logic [31:0]     InstrM,
+  input  logic [XLEN-1:0] IEUAdrM,
+  input  string           InstrMName
+);
+
+  always_ff @(posedge clk)
+    if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
+      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
+      $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
+      //$stop;
+    end
+  
+endmodule
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index b3bc8f96f..d1007ec41 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -19,45 +19,48 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module riscvassertions;
+module riscvassertions import cvw::*; #(parameter cvw_t P);
   initial begin
-    assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (`S_SUPPORTED || `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
-    assert (`IDIV_BITSPERCYCLE == 1 || `IDIV_BITSPERCYCLE==2 || `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
-    assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
-    assert (`D_SUPPORTED || ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
-    assert (`F_SUPPORTED || ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (`DCACHE_SUPPORTED || ~`F_SUPPORTED || `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
-    assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
-    assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
-    assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
-    assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
-    assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
-    assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
-    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
-	  assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
-    assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
-    assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
-    assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
-    assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
-    assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
-    assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
-    assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
-    assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
-    assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
+    assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
+    assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
+    assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
+    assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
+    assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
+    assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported");
+    assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
+    assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
+    assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
+    assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
+	  assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
+    assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+    assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
+    assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
+    assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
+    assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
+    assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
+    assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
+    assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
+    assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
+    assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM required DCACHE_SUPPORTED");
+    assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ required DCACHE_SUPPORTED");
+    assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP required DCACHE_SUPPORTED");
   end
 
 endmodule
diff --git a/testbench/common/shadowmem.sv b/testbench/common/shadowmem.sv
new file mode 100644
index 000000000..19884390d
--- /dev/null
+++ b/testbench/common/shadowmem.sv
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// shadowmem.sv
+//
+// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+//
+// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty
+//          line before the end of test.  Signature based regression tests need to check the L1 data cache
+//          in addition to the main memory.  These modules create a shadow memory with a projection of the
+//          D$ contents.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) 
+  (input logic clk,
+   input logic reset,
+   input logic start,
+   output logic done);
+
+  genvar adr;
+
+  logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
+  logic         startD;
+  
+  if(P.DCACHE_SUPPORTED) begin
+    localparam numlines       = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS;
+    localparam numways        = P.DCACHE_NUMWAYS;
+    localparam linelen        = P.DCACHE_LINELENINBITS;
+    localparam linebytelen    = linelen/8;
+    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+    localparam numwords       = sramlen/P.XLEN;
+    localparam lognumlines    = $clog2(numlines);
+    localparam loglinebytelen = $clog2(linebytelen);
+    localparam lognumways     = $clog2(numways);
+    localparam tagstart       = lognumlines + loglinebytelen;
+    
+    genvar               index, way, cacheWord;
+    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [sramlen-1:0]  cacheline;
+    logic [P.XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [P.PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    for(index = 0; index < numlines; index++) begin
+      for(way = 0; way < numways; way++) begin
+        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
+          copyShadow #(.P(P), .tagstart(tagstart),
+          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
+          copyShadow(.clk,
+          .start,
+          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]),
+          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
+          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
+                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
+          .index(index),
+          .cacheWord(cacheWord),
+          .CacheData(CacheData[way][index][cacheWord]),
+          .CacheAdr(CacheAdr[way][index][cacheWord]),
+          .CacheTag(CacheTag[way][index][cacheWord]),
+          .CacheValid(CacheValid[way][index][cacheWord]),
+          .CacheDirty(CacheDirty[way][index][cacheWord]));
+        end
+      end
+    end
+
+    integer i, j, k, l;
+
+    always @(posedge clk) begin
+      if (startD) begin 
+        for(i = 0; i < numlines; i++) begin
+          for(j = 0; j < numways; j++) begin
+            for(l = 0; l < cachesramwords; l++) begin
+              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
+                for(k = 0; k < numwords; k++) begin
+                  //cacheline = CacheData[j][i][0];
+                  // does not work with modelsim
+                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
+                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
+                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
+                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
+                end
+              end
+            end
+          end
+        end
+      end
+    end  
+  end
+  flop #(1) doneReg1(.clk, .d(start), .q(startD));
+  flop #(1) doneReg2(.clk, .d(startD), .q(done));
+endmodule
+
+module copyShadow import cvw::*; #(parameter cvw_t P,
+  parameter tagstart, loglinebytelen, sramlen)
+  (input  logic                       clk,
+   input  logic                       start,
+   input  logic [P.PA_BITS-1:tagstart] tag,
+   input  logic                       valid, dirty,
+   input  logic [sramlen-1:0]         data,
+   input  logic [32-1:0]              index,
+   input  logic [32-1:0]              cacheWord,
+   output logic [sramlen-1:0]         CacheData,
+   output logic [P.PA_BITS-1:0]        CacheAdr,
+   output logic [P.XLEN-1:0]           CacheTag,
+   output logic                       CacheValid,
+   output logic                       CacheDirty);
+  
+
+  always_ff @(posedge clk) begin
+    if(start) begin
+      CacheTag = tag;
+      CacheValid = valid;
+      CacheDirty = dirty;
+      CacheData = data;
+      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
+    end
+  end
+  
+endmodule
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 221c8d7f8..42f55bf09 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -19,7 +19,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
 `define NUM_REGS 32
 `define NUM_CSRS 4096
@@ -29,9 +28,10 @@
 `define PRINT_ALL 0
 `define PRINT_CSRS 0
 
-module wallyTracer(rvviTrace rvvi);
 
-  localparam NUMREGS = `E_SUPPORTED ? 16 : 32;
+module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
+
+  localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
   
   // wally specific signals
   logic 						 reset;
@@ -39,8 +39,8 @@ module wallyTracer(rvviTrace rvvi);
   logic                          InstrValidD, InstrValidE;
   logic                          StallF, StallD;
   logic                          STATUS_SXL, STATUS_UXL;
-  logic [`XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
-  logic [`XLEN-1:0] 			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
+  logic [P.XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
+  logic [P.XLEN-1:0] 			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
   logic 						 InstrValidM, InstrValidW;
   logic 						 StallE, StallM, StallW;
   logic 						 FlushD, FlushE, FlushM, FlushW;
@@ -48,20 +48,22 @@ module wallyTracer(rvviTrace rvvi);
   logic 						 IntrF, IntrD, IntrE, IntrM, IntrW;
   logic 						 HaltM, HaltW;
   logic [1:0] 					 PrivilegeModeW;
-  logic [`XLEN-1:0] 			 rf[NUMREGS];
+  logic [P.XLEN-1:0] 			 rf[NUMREGS];
   logic [NUMREGS-1:0] 			 rf_wb;
   logic [4:0] 					 rf_a3;
   logic 						 rf_we3;
-  logic [`XLEN-1:0] 			 frf[32];
+  logic [P.XLEN-1:0] 			 frf[32];
   logic [`NUM_REGS-1:0] 		 frf_wb;
   logic [4:0] 					 frf_a4;
   logic 						 frf_we4;
-  logic [`XLEN-1:0]              CSRArray [logic[11:0]];
-  logic [`XLEN-1:0] 			 CSRArrayOld [logic[11:0]];
+  logic [P.XLEN-1:0]              CSRArray [logic[11:0]];
+  logic [P.XLEN-1:0] 			 CSRArrayOld [logic[11:0]];
   logic [`NUM_CSRS-1:0] 		 CSR_W;
   logic 						 CSRWriteM, CSRWriteW;
   logic [11:0] 					 CSRAdrM, CSRAdrW;
-  
+  logic                          wfiM;
+  logic                          InterruptM;
+    
   assign clk = testbench.dut.clk;
   //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
   assign InstrValidD    = testbench.dut.core.ieu.c.InstrValidD;
@@ -88,6 +90,9 @@ module wallyTracer(rvviTrace rvvi);
   assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
   assign STATUS_SXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
   assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
+  assign wfiM           = testbench.dut.core.priv.priv.wfiM;
+  assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
+  
 
   logic valid;
   int csrid;
@@ -102,8 +107,8 @@ module wallyTracer(rvviTrace rvvi);
 	
       // PMPCFG  space is 0-15 3a0 - 3af
 	  int i, i4, i8, csrid;
-      logic [`XLEN-1:0] pmp;
-      for (i=0; i<`PMP_ENTRIES; i+=8) begin
+      logic [P.XLEN-1:0] pmp;
+      for (i=0; i<P.PMP_ENTRIES; i+=8) begin
         i4 = i / 4;
         i8 = (i / 8) * 8;
         pmp = 0;
@@ -121,7 +126,7 @@ module wallyTracer(rvviTrace rvvi);
       end
 
       // PMPADDR space is 0-63 3b0 - 3ef
-      for (i=0; i<`PMP_ENTRIES; i++) begin
+      for (i=0; i<P.PMP_ENTRIES; i++) begin
         pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
         
         csrid = 12'h3B0 + i;
@@ -139,13 +144,14 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
 	  CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
 	  CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
+	  CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
 	  CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
 	  CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
 	  CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
 	  CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
 	  CSRArray[12'hF11] = 0;
 	  CSRArray[12'hF12] = 0;
-	  CSRArray[12'hF13] = `XLEN'h100;
+	  CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
 	  CSRArray[12'hF15] = 0;
 	  CSRArray[12'h34A] = 0;
 	  // MCYCLE and MINSTRET
@@ -157,11 +163,12 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
 	  CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
 	  CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
+	  CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
 	  CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
 	  CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
 	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
-	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
 	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
 	  // user CSRs
 	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
@@ -189,6 +196,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h344] = CSRArrayOld[12'h344];
 	  CSRArray[12'h304] = CSRArrayOld[12'h304];
 	  CSRArray[12'h301] = CSRArrayOld[12'h301];
+	  CSRArray[12'h30A] = CSRArrayOld[12'h30A];
 	  CSRArray[12'hF14] = CSRArrayOld[12'hF14];
 	  CSRArray[12'h340] = CSRArrayOld[12'h340];
 	  CSRArray[12'h342] = CSRArrayOld[12'h342];
@@ -207,6 +215,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h105] = CSRArrayOld[12'h105];
 	  CSRArray[12'h141] = CSRArrayOld[12'h141];
 	  CSRArray[12'h106] = CSRArrayOld[12'h106];
+	  CSRArray[12'h10A] = CSRArrayOld[12'h10A];
 	  CSRArray[12'h180] = CSRArrayOld[12'h180];
 	  CSRArray[12'h140] = CSRArrayOld[12'h140];
 	  CSRArray[12'h143] = CSRArrayOld[12'h143];
@@ -250,10 +259,10 @@ module wallyTracer(rvviTrace rvvi);
   assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
   
   // pipeline to writeback stage
-  flopenrc #(`XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
-  flopenrc #(`XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(`XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(`XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
+  flopenrc #(P.XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
+  flopenrc #(P.XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
+  flopenrc #(P.XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
+  flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
   flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
   flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
   flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
@@ -308,6 +317,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h344] = CSRArray[12'h344];
     CSRArrayOld[12'h304] = CSRArray[12'h304];
     CSRArrayOld[12'h301] = CSRArray[12'h301];
+    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
     CSRArrayOld[12'hF14] = CSRArray[12'hF14];
     CSRArrayOld[12'h340] = CSRArray[12'h340];
     CSRArrayOld[12'h342] = CSRArray[12'h342];
@@ -326,6 +336,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h105] = CSRArray[12'h105];
     CSRArrayOld[12'h141] = CSRArray[12'h141];
     CSRArrayOld[12'h106] = CSRArray[12'h106];
+    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
     CSRArrayOld[12'h180] = CSRArray[12'h180];
     CSRArrayOld[12'h140] = CSRArray[12'h140];
     CSRArrayOld[12'h143] = CSRArray[12'h143];
@@ -352,6 +363,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
   assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
   assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
+  assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
   assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
   assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
   assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
@@ -374,6 +386,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
   assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
   assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
+  assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
   assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
   assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
   assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
@@ -394,6 +407,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
   assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
   assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
+  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
   assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
   assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
   assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
@@ -411,6 +425,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
   assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
   assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
+  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
   assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
   assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
   assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
@@ -431,6 +446,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h303]    = CSRArray[12'h303];
   assign rvvi.csr[0][0][12'h344]    = CSRArray[12'h344];
   assign rvvi.csr[0][0][12'h304]    = CSRArray[12'h304];
+  assign rvvi.csr[0][0][12'h30A]    = CSRArray[12'h30A];
   assign rvvi.csr[0][0][12'h301]    = CSRArray[12'h301];
   assign rvvi.csr[0][0][12'hF14]    = CSRArray[12'hF14];
   assign rvvi.csr[0][0][12'h340]    = CSRArray[12'h340];
@@ -448,6 +464,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h105]    = CSRArray[12'h105];
   assign rvvi.csr[0][0][12'h141]    = CSRArray[12'h141];
   assign rvvi.csr[0][0][12'h106]    = CSRArray[12'h106];
+  assign rvvi.csr[0][0][12'h10A]    = CSRArray[12'h10A];
   assign rvvi.csr[0][0][12'h180]    = CSRArray[12'h180];
   assign rvvi.csr[0][0][12'h140]    = CSRArray[12'h140];
   assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv
new file mode 100644
index 000000000..51ed8c30f
--- /dev/null
+++ b/testbench/common/watchdog.sv
@@ -0,0 +1,52 @@
+///////////////////////////////////////////
+// watchdog.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+//
+// Purpose: Detects if the processor is stuck and halts the simulation
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module watchdog #(parameter XLEN, WatchDogTimerThreshold) 
+  (input clk,
+   input reset
+   );
+  
+  // check for hang up.
+  logic [XLEN-1:0]    PCW;
+  flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  logic [XLEN-1:0]    OldPCW;
+  integer               WatchDogTimerCount;
+  logic                 WatchDogTimeOut;
+  always_ff @(posedge clk) begin
+    OldPCW <= PCW;
+    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
+    else WatchDogTimerCount = '0;
+  end
+
+  always_comb begin
+    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
+    if(WatchDogTimeOut) begin
+      $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
+      $stop;
+	end
+  end
+
+endmodule
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index b7fcc237f..08d674f1d 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -1,10 +1,8 @@
 ///////////////////////////////////////////
 //
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-// Modified: 4/2/2023
+// Written: me@KatherineParry.com, james.stine@okstate.edu
 //
-// Purpose: Testbench for Testfloat
+// Purpose: Testbench for UCB Testfloat on Wally
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -23,1323 +21,1385 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
+
+`include "config.vh"
 `include "tests-fp.vh"
 
+import cvw::*;
+
 module testbenchfp;
-  parameter TEST="none";
+   // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
+   // to run specific precisions (e.g., quad or all)
+   parameter TEST="none";
+   parameter TEST_SIZE="none";
 
-  string                       Tests[];                    // list of tests to be run
-  logic [2:0]                  OpCtrl[];                   // list of op controls
-  logic [2:0]                  Unit[];                     // list of units being tested
-  logic                        WriteInt[];                 // Is being written to integer resgiter
-  logic [2:0]                  Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
-  logic [1:0]                  Fmt[];                      // list of formats for the other units  
+  `include "parameter-defs.vh"   
 
-  logic                        clk=0;
-  logic [31:0]                 TestNum=0;                  // index for the test
-  logic [31:0]                 OpCtrlNum=0;                // index for OpCtrl
-  logic [31:0]                 errors=0;                   // how many errors
-  logic [31:0]                 VectorNum=0;                // index for test vector
-  logic [31:0]                 FrmNum=0;                   // index for rounding mode
-  logic [`FLEN*4+7:0]          TestVectors[8388609:0];     // list of test vectors
+   // FIXME: needs cleaning of unused variables (jes)
+   string                       Tests[];                    // list of tests to be run
+   logic [2:0] 			OpCtrl[];                   // list of op controls
+   logic [2:0] 			Unit[];                     // list of units being tested
+   logic                        WriteInt[];                 // Is being written to integer resgiter
+   logic [2:0] 			Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
+   logic [1:0] 			Fmt[];                      // list of formats for the other units  
 
-  logic [1:0]                  FmtVal;                     // value of the current Fmt
-  logic [2:0]                  UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
-  logic                        WriteIntVal;                // value of the current WriteInt
-  logic [`FLEN-1:0]            X, Y, Z;                    // inputs read from TestFloat
-  logic [`FLEN-1:0] 	       XPostBox;                   // inputs read from TestFloat
-  logic [`XLEN-1:0]            SrcA;                       // integer input
-  logic [`FLEN-1:0]	       Ans;                        // correct answer from TestFloat
-  logic [`FLEN-1:0]	       Res;                        // result from other units
-  logic [4:0]	 	       AnsFlg;                     // correct flags read from testfloat
-  logic [4:0]	 	       ResFlg, Flg;                // Result flags
-  logic	[`FMTBITS-1:0]         ModFmt;                     // format - 10 = half, 00 = single, 01 = double, 11 = quad
-  logic [`FLEN-1:0]            FpRes, FpCmpRes;            // Results from each unit
-  logic [`XLEN-1:0]            IntRes, CmpRes;             // Results from each unit
-  logic [4:0]                  FmaFlg, CvtFlg, DivFlg, CmpFlg;  // Outputed flags
-  logic                        AnsNaN, ResNaN, NaNGood;
-  logic                        Xs, Ys, Zs;                 // sign of the inputs
-  logic [`NE-1:0]              Xe, Ye, Ze;                 // exponent of the inputs
-  logic [`NF:0]                Xm, Ym, Zm;                 // mantissas of the inputs
-  logic                        XNaN, YNaN, ZNaN;           // is the input NaN
-  logic                        XSNaN, YSNaN, ZSNaN;        // is the input a signaling NaN
-  logic                        XSubnorm, ZSubnorm;         // is the input denormalized
-  logic                        XInf, YInf, ZInf;           // is the input infinity
-  logic                        XZero, YZero, ZZero;        // is the input zero
-  logic                        XExpMax, YExpMax, ZExpMax;  // is the input's exponent all ones  
-  logic  [`CVTLEN-1:0]         CvtLzcInE;                  // input to the Leading Zero Counter (priority encoder)
-  logic                        IntZero;
-  logic                        CvtResSgnE;
-  logic [`NE:0]                CvtCalcExpE;                // the calculated expoent
-  logic [`LOGCVTLEN-1:0]       CvtShiftAmtE;               // how much to shift by
-  logic [`DIVb:0]              Quot;
-  logic                        CvtResSubnormUfE;
-  logic                        DivStart, FDivBusyE, OldFDivBusyE;
-  logic                        reset = 1'b0;
-  logic [$clog2(`NF+2)-1:0]    XZeroCnt, YZeroCnt;
-  logic [`DURLEN-1:0]          Dur;
+   logic                        clk=0;
+   logic [31:0] 		TestNum=0;                  // index for the test
+   logic [31:0] 		OpCtrlNum=0;                // index for OpCtrl
+   logic [31:0] 		errors=0;                   // how many errors
+   logic [31:0] 		VectorNum=0;                // index for test vector
+   logic [31:0] 		FrmNum=0;                   // index for rounding mode
+   logic [P.FLEN*4+7:0] 	TestVectors[8388609:0];     // list of test vectors
 
-  // in-between FMA signals
-  logic                        Mult;
-  logic                        Ss;
-  logic [`NE+1:0]	       Pe;
-  logic [`NE+1:0]	       Se;
-  logic 		       ASticky;
-  logic 		       KillProd; 
-  logic [$clog2(3*`NF+5)-1:0]  SCnt;
-  logic [3*`NF+3:0]	       Sm;       
-  logic 		       InvA;
-  logic 		       NegSum;
-  logic 		       As;
-  logic 		       Ps;
-  logic                        DivSticky;
-  logic                        DivDone;
-  logic                        DivNegSticky;
-  logic [`NE+1:0]              DivCalcExp;
-  logic                        divsqrtop;
+   logic [1:0] 			FmtVal;                     // value of the current Fmt
+   logic [2:0] 			UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
+   logic                        WriteIntVal;                // value of the current WriteInt
+   logic [P.FLEN-1:0] 		X, Y, Z;                    // inputs read from TestFloat
+   logic [P.FLEN-1:0] 		XPostBox;                   // inputs read from TestFloat
+   logic [P.XLEN-1:0] 		SrcA;                       // integer input
+   logic [P.FLEN-1:0] 		Ans;                        // correct answer from TestFloat
+   logic [P.FLEN-1:0] 		Res;                        // result from other units
+   logic [4:0] 			AnsFlg;                     // correct flags read from testfloat
+   logic [4:0] 			ResFlg, Flg;                // Result flags
+   logic [P.FMTBITS-1:0] 	ModFmt;                     // format - 10 = half, 00 = single, 01 = double, 11 = quad
+   logic [P.FLEN-1:0] 		FpRes, FpCmpRes;            // Results from each unit
+   logic [P.XLEN-1:0] 		IntRes, CmpRes;             // Results from each unit
+   logic [4:0] 			FmaFlg, CvtFlg, DivFlg;     // Outputed flags
+   logic [4:0] 			CmpFlg;                     // Outputed flags
+   logic                        AnsNaN, ResNaN, NaNGood;
+   logic                        Xs, Ys, Zs;                 // sign of the inputs
+   logic [P.NE-1:0] 		Xe, Ye, Ze;                 // exponent of the inputs
+   logic [P.NF:0] 		Xm, Ym, Zm;                 // mantissas of the inputs
+   logic                        XNaN, YNaN, ZNaN;           // is the input NaN
+   logic                        XSNaN, YSNaN, ZSNaN;        // is the input a signaling NaN
+   logic                        XSubnorm, ZSubnorm;         // is the input denormalized
+   logic                        XInf, YInf, ZInf;           // is the input infinity
+   logic                        XZero, YZero, ZZero;        // is the input zero
+   logic                        XExpMax, YExpMax, ZExpMax;  // is the input's exponent all ones  
+   logic [P.CVTLEN-1:0] 	CvtLzcInE;                  // input to the Leading Zero Counter (priority encoder)
+   logic                        IntZero;
+   logic                        CvtResSgnE;
+   logic [P.NE:0] 		CvtCalcExpE;                // the calculated exponent
+   logic [P.LOGCVTLEN-1:0] 	CvtShiftAmtE;               // how much to shift by
+   logic [P.DIVb:0] 		Quot;
+   logic                        CvtResSubnormUfE;
+   logic                        DivStart;
+   logic 			FDivBusyE;
+   logic 			OldFDivBusyE;
+   logic                        reset = 1'b0;
+   logic [$clog2(P.NF+2)-1:0] 	XZeroCnt, YZeroCnt;
+   logic [P.DURLEN-1:0] 	Dur;
+
+   // in-between FMA signals
+   logic                        Mult;
+   logic                        Ss;
+   logic [P.NE+1:0] 		Pe;
+   logic [P.NE+1:0] 		Se;
+   logic 			ASticky;
+   logic 			KillProd; 
+   logic [$clog2(3*P.NF+5)-1:0] SCnt;
+   logic [3*P.NF+3:0] 		Sm;       
+   logic 			InvA;
+   logic 			NegSum;
+   logic 			As;
+   logic 			Ps;
+   logic                        DivSticky;
+   logic                        DivDone;
+   logic                        DivNegSticky;
+   logic [P.NE+1:0] 		DivCalcExp;
+   logic                        divsqrtop;
 
    // Missing logic vectors fdivsqrt
-   logic [2:0]                 Funct3E;
-   logic [2:0]                 Funct3M;
-   logic                       FlushE;
-   logic                       IFDivStartE, FDivDoneE;
-   logic [`NE+1:0]             QeM;
-   logic [`DIVb:0]             QmM;
-   logic [`XLEN-1:0]           FIntDivResultM;   
+   logic [2:0] 			Funct3E;
+   logic [2:0] 			Funct3M;
+   logic 			FlushE;
+   logic 			IFDivStartE;
+   logic 			FDivDoneE;
+   logic [P.NE+1:0] 		QeM;
+   logic [P.DIVb:0] 		QmM;
+   logic [P.XLEN-1:0] 		FIntDivResultM;
+   logic 			ResMatch;                   // Check if result match
+   logic 			FlagMatch;                  // Check if IEEE flags match
+   logic 			CheckNow;                   // Final check
+   logic 			FMAop;                      // Is this a FMA operation?   
+   
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
+   //     ||||||||| |||||||| ||||||| |||||||||   ||||||| |||||||| |||
+   //        |||    |||      |||        |||      |||     |||      |||
+   //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||
+   //        |||    |||          |||    |||          ||| |||      |||
+   //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||||||||
 
-  ///////////////////////////////////////////////////////////////////////////////////////////////
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  //     ||||||||| |||||||| ||||||| |||||||||   ||||||| |||||||| |||
-  //        |||    |||      |||        |||      |||     |||      |||
-  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||
-  //        |||    |||          |||    |||          ||| |||      |||
-  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||||||||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // select tests relevent to the specified configuration
-  //    cvtint - test integer conversion unit (fcvtint)
-  //    cvtfp  - test floating-point conversion unit (fcvtfp)
-  //    cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
-  //    add    - test addition
-  //    sub    - test subtraction
-  //    div    - test division
-  //    sqrt   - test square root
-  //    all    - test all of the above
-  initial begin
-    $display("TEST is %s", TEST);
-    if (`Q_SUPPORTED) begin // if Quad percision is supported
-      if (TEST === "cvtint"| TEST === "all") begin  // if testing integer conversion
-         // add the 128-bit cvtint tests to the to-be-tested list
-         Tests = {Tests, f128rv32cvtint};
-         // add the op-codes for these tests to the op-code list
-         OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-         WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-         // add what unit is used and the fmt to their lists (one for each test)
-         for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b11};
-         end
-         if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
-            Tests = {Tests, f128rv64cvtint};
+   // select tests relevent to the specified configuration
+   //    cvtint - test integer conversion unit (fcvtint)
+   //    cvtfp  - test floating-point conversion unit (fcvtfp)
+   //    cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+   //    add    - test addition
+   //    sub    - test subtraction
+   //    div    - test division
+   //    sqrt   - test square root
+   //    all    - test all of the above
+   
+   initial begin
+      // Information displayed for user on what is simulating
+      $display("\nThe start of simulation...");      
+      $display("This simulation for TEST is %s", TEST);
+      $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);      
+      if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
+	 if (TEST === "cvtint" | TEST === "all") begin  // if testing integer conversion
+            // add the 128-bit cvtint tests to the to-be-tested list
+            Tests = {Tests, f128rv32cvtint};
             // add the op-codes for these tests to the op-code list
-            OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+            OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
             WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
             // add what unit is used and the fmt to their lists (one for each test)
             for(int i = 0; i<20; i++) begin
                Unit = {Unit, `CVTINTUNIT};
                Fmt = {Fmt, 2'b11};
             end
-         end
-      end 
-      // if the floating-point conversions are being tested          
-      if (TEST === "cvtfp" | TEST === "all") begin  
-        if(`D_SUPPORTED) begin // if double precision is supported
-          // add the 128 <-> 64 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f64cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b01, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-        end
-        if(`F_SUPPORTED) begin // if single precision is supported
-          // add the 128 <-> 32 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f32cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b00, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-        end
-        if(`ZFH_SUPPORTED) begin // if half precision is supported
-          // add the 128 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
+            if (P.XLEN == 64) begin // if 64-bit integers are supported add their conversions
+               Tests = {Tests, f128rv64cvtint};
+               // add the op-codes for these tests to the op-code list
+               OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+               WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+               // add what unit is used and the fmt to their lists (one for each test)
+               for(int i = 0; i<20; i++) begin
+		  Unit = {Unit, `CVTINTUNIT};
+		  Fmt = {Fmt, 2'b11};
+               end
+            end
+	 end 
+	 // if the floating-point conversions are being tested          
+	 if (TEST === "cvtfp" | TEST === "all") begin  
+            if (P.D_SUPPORTED) begin // if double precision is supported
+               // add the 128 <-> 64 bit conversions to the to-be-tested list
+               Tests = {Tests, f128f64cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b01, 3'b11};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b11};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b01};
+               end
+            end
+            if (P.F_SUPPORTED) begin // if single precision is supported
+               // add the 128 <-> 32 bit conversions to the to-be-tested list
+               Tests = {Tests, f128f32cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b00, 3'b11};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b11};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b00};
+               end
+            end
+            if (P.ZFH_SUPPORTED) begin // if half precision is supported
+               // add the 128 <-> 16 bit conversions to the to-be-tested list
+               Tests = {Tests, f128f16cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b10, 3'b11};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b11};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b10};
+               end
+            end
+	 end
+	 if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested
+            // add the compare tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128cmp};
+            OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+            for(int i = 0; i<15; i++) begin
+               Unit = {Unit, `CMPUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "add" | TEST === "all") begin // if addition is being tested
+            // add the addition tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128add};
+            OpCtrl = {OpCtrl, `ADD_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested
+            // add the subtraction tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128sub};
+            OpCtrl = {OpCtrl, `SUB_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
+            // add the multiply tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128mul};
+            OpCtrl = {OpCtrl, `MUL_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "div" | TEST === "all") begin // if division is being tested
+            // add the divide tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128div};
+            OpCtrl = {OpCtrl, `DIV_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested
+            // add the square-root tests/op-ctrls/unit/fmt
+            Tests = {Tests, f128sqrt};
+            OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
+	 if (TEST === "fma" | TEST === "all") begin  // if fused-mutliply-add is being tested
+            Tests = {Tests, f128fma};
+            OpCtrl = {OpCtrl, `FMA_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b11};
+            end
+	 end
       end
-      if (TEST === "cmp"   | TEST === "all") begin// if comparisons are being tested
-        // add the compare tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-          for(int i = 0; i<15; i++) begin
-            Unit = {Unit, `CMPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
-        // add the addition tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `FMAUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "sub"   | TEST === "all") begin // if subtraction is being tested
-        // add the subtraction tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `FMAUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
-        // add the multiply tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `FMAUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "div"   | TEST === "all") begin // if division is being tested
-        // add the divide tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `DIVUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tested
-        // add the square-root tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `DIVUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-      end
-      if (TEST === "fma"   | TEST === "all") begin  // if fused-mutliply-add is being tested
-        Tests = {Tests, f128fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-    end
-    if (`D_SUPPORTED) begin // if double precision is supported
-      if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
-         Tests = {Tests, f64rv32cvtint};
-         // add the op-codes for these tests to the op-code list
-         OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-         WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-         // add what unit is used and the fmt to their lists (one for each test)
-         for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b01};
-         end
-         if (`XLEN == 64) begin // if 64-bit integers are being supported
-            Tests = {Tests, f64rv64cvtint};
+      if (P.D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported
+	 if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested
+            Tests = {Tests, f64rv32cvtint};
             // add the op-codes for these tests to the op-code list
-            OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+            OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
             WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
             // add what unit is used and the fmt to their lists (one for each test)
             for(int i = 0; i<20; i++) begin
                Unit = {Unit, `CVTINTUNIT};
                Fmt = {Fmt, 2'b01};
             end
-         end
+            if (P.XLEN == 64) begin // if 64-bit integers are being supported
+               Tests = {Tests, f64rv64cvtint};
+               // add the op-codes for these tests to the op-code list
+               OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+               WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+               // add what unit is used and the fmt to their lists (one for each test)
+               for(int i = 0; i<20; i++) begin
+		  Unit = {Unit, `CVTINTUNIT};
+		  Fmt = {Fmt, 2'b01};
+               end
+            end
+	 end
+	 if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
+            if (P.F_SUPPORTED) begin // if single precision is supported
+               // add the 64 <-> 32 bit conversions to the to-be-tested list
+               Tests = {Tests, f64f32cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b00, 3'b01};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b01};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b00};
+               end
+            end
+            if (P.ZFH_SUPPORTED) begin // if half precision is supported
+               // add the 64 <-> 16 bit conversions to the to-be-tested list
+               Tests = {Tests, f64f16cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b10, 3'b01};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b01};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b10};
+               end
+            end
+	 end
+	 if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64cmp};
+            OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+            for(int i = 0; i<15; i++) begin
+               Unit = {Unit, `CMPUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "add" | TEST === "all") begin // if addition is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64add};
+            OpCtrl = {OpCtrl, `ADD_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "sub" | TEST === "all") begin // if subtration is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64sub};
+            OpCtrl = {OpCtrl, `SUB_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64mul};
+            OpCtrl = {OpCtrl, `MUL_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "div" | TEST === "all") begin // if division is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64div};
+            OpCtrl = {OpCtrl, `DIV_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f64sqrt};
+            OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
+	 if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested
+            Tests = {Tests, f64fma};
+            OpCtrl = {OpCtrl, `FMA_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b01};
+            end
+	 end
       end
-      if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
-        if(`F_SUPPORTED) begin // if single precision is supported
-          // add the 64 <-> 32 bit conversions to the to-be-tested list
-          Tests = {Tests, f64f32cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b00, 3'b01};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-        end
-        if(`ZFH_SUPPORTED) begin // if half precision is supported
-          // add the 64 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f64f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b01};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp"   | TEST === "all") begin // if comparisions are being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "sub"   | TEST === "all") begin // if subtration is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "div"   | TEST === "all") begin // if division is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tessted
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "fma"   | TEST === "all") begin // if the fused multiply add is being tested
-        Tests = {Tests, f64fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-    end
-    if (`F_SUPPORTED) begin // if single precision being supported
-      if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
-         Tests = {Tests, f32rv32cvtint};
-         // add the op-codes for these tests to the op-code list
-         OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-         WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-         // add what unit is used and the fmt to their lists (one for each test)
-         for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b00};
-         end
-         if (`XLEN == 64) begin // if 64-bit integers are supported
-            Tests = {Tests, f32rv64cvtint};
+      if (P.F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported
+	 if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
+            Tests = {Tests, f32rv32cvtint};
             // add the op-codes for these tests to the op-code list
-            OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+            OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
             WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
             // add what unit is used and the fmt to their lists (one for each test)
             for(int i = 0; i<20; i++) begin
                Unit = {Unit, `CVTINTUNIT};
                Fmt = {Fmt, 2'b00};
             end
-         end
+            if (P.XLEN == 64) begin // if 64-bit integers are supported
+               Tests = {Tests, f32rv64cvtint};
+               // add the op-codes for these tests to the op-code list
+               OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+               WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+               // add what unit is used and the fmt to their lists (one for each test)
+               for(int i = 0; i<20; i++) begin
+		  Unit = {Unit, `CVTINTUNIT};
+		  Fmt = {Fmt, 2'b00};
+               end
+            end
+	 end
+	 if (TEST === "cvtfp" | TEST === "all") begin  // if floating point conversion is being tested
+            if (P.ZFH_SUPPORTED) begin 
+               // add the 32 <-> 16 bit conversions to the to-be-tested list
+               Tests = {Tests, f32f16cvt};
+               // add the op-ctrls (i.e. the format of the result)
+               OpCtrl = {OpCtrl, 3'b10, 3'b00};
+               WriteInt = {WriteInt, 1'b0, 1'b0};
+               // add the unit being tested and fmt (input format)
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b00};
+               end
+               for(int i = 0; i<5; i++) begin
+		  Unit = {Unit, `CVTFPUNIT};
+		  Fmt = {Fmt, 2'b10};
+               end
+            end
+	 end
+	 if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32cmp};
+            OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+            for(int i = 0; i<15; i++) begin
+               Unit = {Unit, `CMPUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "add" | TEST === "all") begin // if addition is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32add};
+            OpCtrl = {OpCtrl, `ADD_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "sub" | TEST === "all") begin // if subtration is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32sub};
+            OpCtrl = {OpCtrl, `SUB_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "mul" | TEST === "all") begin // if multiply is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32mul};
+            OpCtrl = {OpCtrl, `MUL_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "div" | TEST === "all") begin // if division is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32div};
+            OpCtrl = {OpCtrl, `DIV_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f32sqrt};
+            OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
+	 if (TEST === "fma" | TEST === "all")  begin // if fma is being tested
+            Tests = {Tests, f32fma};
+            OpCtrl = {OpCtrl, `FMA_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b00};
+            end
+	 end
       end
-      if (TEST === "cvtfp" | TEST === "all") begin  // if floating point conversion is being tested
-        if(`ZFH_SUPPORTED) begin 
-          // add the 32 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f32f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b00};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp"   | TEST === "all") begin // if comparision is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "sub"   | TEST === "all") begin // if subtration is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "mul"   | TEST === "all") begin // if multiply is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "div"   | TEST === "all") begin // if division is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "fma"   | TEST === "all")  begin // if fma is being tested
-        Tests = {Tests, f32fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-    end
-    if (`ZFH_SUPPORTED) begin // if half precision supported
-      if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
-         Tests = {Tests, f16rv32cvtint};
-         // add the op-codes for these tests to the op-code list
-         OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-         WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-         // add what unit is used and the fmt to their lists (one for each test)
-         for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b10};
-         end
-         if (`XLEN == 64) begin // if 64-bit integers are supported
-            Tests = {Tests, f16rv64cvtint};
+      if (P.ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported
+	 if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested
+            Tests = {Tests, f16rv32cvtint};
             // add the op-codes for these tests to the op-code list
-            OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+            OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
             WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
             // add what unit is used and the fmt to their lists (one for each test)
             for(int i = 0; i<20; i++) begin
                Unit = {Unit, `CVTINTUNIT};
                Fmt = {Fmt, 2'b10};
             end
-         end
+            if (P.XLEN == 64) begin // if 64-bit integers are supported
+               Tests = {Tests, f16rv64cvtint};
+               // add the op-codes for these tests to the op-code list
+               OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+               WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+               // add what unit is used and the fmt to their lists (one for each test)
+               for(int i = 0; i<20; i++) begin
+		  Unit = {Unit, `CVTINTUNIT};
+		  Fmt = {Fmt, 2'b10};
+               end
+            end
+	 end
+	 if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16cmp};
+            OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+            for(int i = 0; i<15; i++) begin
+               Unit = {Unit, `CMPUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
+	 if (TEST === "add" | TEST === "all") begin //  if addition is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16add};
+            OpCtrl = {OpCtrl, `ADD_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
+	 if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16sub};
+            OpCtrl = {OpCtrl, `SUB_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
+	 if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16mul};
+            OpCtrl = {OpCtrl, `MUL_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
+	 if (TEST === "div" | TEST === "all") begin // if division is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16div};
+            OpCtrl = {OpCtrl, `DIV_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
+	 if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
+            // add the correct tests/op-ctrls/unit/fmt to their lists
+            Tests = {Tests, f16sqrt};
+            OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `DIVUNIT};
+               Fmt = {Fmt, 2'b10};
+            end 
+	 end
+	 if (TEST === "fma" | TEST === "all") begin // if fma is being tested
+            Tests = {Tests, f16fma};
+            OpCtrl = {OpCtrl, `FMA_OPCTRL};
+            WriteInt = {WriteInt, 1'b0};
+            for(int i = 0; i<5; i++) begin
+               Unit = {Unit, `FMAUNIT};
+               Fmt = {Fmt, 2'b10};
+            end
+	 end
       end
-      if (TEST === "cmp"   | TEST === "all") begin // if comparisions are being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
+      // check if nothing is being tested
+      if (Tests.size() == 0) begin
+	 $display("TEST %s not supported in this configuration", TEST);
+	 $stop;
       end
-      if (TEST === "add"   | TEST === "all") begin //  if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "sub"   | TEST === "all") begin // if subtraction is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "div"   | TEST === "all") begin // if division is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b10};
-        end 
-      end
-      if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
-        Tests = {Tests, f16fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-    end
+   end
 
-    // check if nothing is being tested
-    if (Tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
-      $stop;
-    end
-  end
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  ///////////////////////////////////////////////////////////////////////////////////////////////
+   //     ||||||||| |||||||| ||||||||| |||||||     ||||||||| |||||||| ||||||| |||||||||   
+   //     |||   ||| |||      |||   ||| ||   ||        |||    |||      |||        |||      
+   //     ||||||||  |||||||| ||||||||| ||   ||        |||    |||||||| |||||||    |||      
+   //     |||  ||   |||      |||   ||| ||   ||        |||    |||          |||    |||      
+   //     |||   ||| |||||||| |||   ||| |||||||        |||    |||||||| |||||||    |||      
 
-  //     ||||||||| |||||||| ||||||||| |||||||     ||||||||| |||||||| ||||||| |||||||||   
-  //     |||   ||| |||      |||   ||| ||   ||        |||    |||      |||        |||      
-  //     ||||||||  |||||||| ||||||||| ||   ||        |||    |||||||| |||||||    |||      
-  //     |||  ||   |||      |||   ||| ||   ||        |||    |||          |||    |||      
-  //     |||   ||| |||||||| |||   ||| |||||||        |||    |||||||| |||||||    |||      
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Read the first test
+   initial begin
+      //string testname = {`PATH, Tests[TestNum]}; 
+      string p = `PATH;
+      string testname;
+      string tt0;
+      tt0 = $psprintf("%s", Tests[TestNum]);
+      testname = {p, tt0};
+      $display("Here you are %s", testname);     
+      $display("\n\nRunning %s vectors ", Tests[TestNum]);
+      $readmemh(testname, TestVectors);
+      // set the test index to 0
+      TestNum = 0;
+   end
 
-  // Read the first test
-  initial begin
-    $display("\n\nRunning %s vectors", Tests[TestNum]);
-    $readmemh({`PATH, Tests[TestNum]}, TestVectors);
-    // set the test index to 0
-    TestNum = 0;
-  end
+   // set a the signals for all tests
+   always_comb UnitVal = Unit[TestNum];
+   always_comb FmtVal = Fmt[TestNum];
+   always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
+   always_comb WriteIntVal = WriteInt[OpCtrlNum];
+   always_comb FrmVal = Frm[FrmNum];
 
-  // set a the signals for all tests
-  always_comb UnitVal = Unit[TestNum];
-  always_comb FmtVal = Fmt[TestNum];
-  always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
-  always_comb WriteIntVal = WriteInt[OpCtrlNum];
-  always_comb FrmVal = Frm[FrmNum];
+   // modify the format signal if only 2 percisions supported
+   //    - 1 for the larger precision
+   //    - 0 for the smaller precision
+   always_comb begin
+      if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT;
+      else ModFmt = FmtVal;
+   end
 
-  // modify the format signal if only 2 percisions supported
-  //    - 1 for the larger precision
-  //    - 0 for the smaller precision
-  always_comb begin
-    if(`FMTBITS == 1) ModFmt = FmtVal == `FMT;
-    else ModFmt = FmtVal;
-  end
+   // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
+   readvectors #(P) readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), 
+                                 .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, 
+                                 .Xs, .Ys, .Zs, .Unit(UnitVal),
+                                 .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
+                                 .Xm, .Ym, .Zm, .DivStart,
+                                 .XNaN, .YNaN, .ZNaN,
+                                 .XSNaN, .YSNaN, .ZSNaN, 
+                                 .XSubnorm, .ZSubnorm, 
+                                 .XZero, .YZero, .ZZero,
+                                 .XInf, .YInf, .ZInf, .XExpMax,
+                                 .X, .Y, .Z, .XPostBox);
 
-  // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
-  readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), 
-                           .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, 
-                           .Xs, .Ys, .Zs, .Unit(UnitVal),
-                           .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
-                           .Xm, .Ym, .Zm, .DivStart,
-                           .XNaN, .YNaN, .ZNaN,
-                           .XSNaN, .YSNaN, .ZSNaN, 
-                           .XSubnorm, .ZSubnorm, 
-                           .XZero, .YZero, .ZZero,
-                           .XInf, .YInf, .ZInf, .XExpMax,
-                           .X, .Y, .Z, .XPostBox);
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
+   //     |||||||   |||   ||| ||||||||| 
+   //     |||   ||| |||   |||    |||    
+   //     |||   ||| |||   |||    |||    
+   //     |||   ||| |||   |||    |||         
+   //     |||||||   |||||||||    |||    
 
-  ///////////////////////////////////////////////////////////////////////////////////////////////
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  //     |||||||   |||   ||| ||||||||| 
-  //     |||   ||| |||   |||    |||    
-  //     |||   ||| |||   |||    |||    
-  //     |||   ||| |||   |||    |||         
-  //     |||||||   |||||||||    |||    
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // instantiate devices under test
-  if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
-    fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), 
-            .Xe(Xe), .Ye(Ye), .Ze(Ze), 
-            .Xm(Xm), .Ym(Ym), .Zm(Zm),
-            .XZero, .YZero, .ZZero, .Ss, .Se,
-            .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
-            .ASticky); 
-  end
-              
-  postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
-              .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
-              .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
-              .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
-              .XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
-              .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
-              .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
-              .FmaASticky(ASticky), .FmaSe(Se),
-              .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), 
-              .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
-  
-  if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
-    fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
-              .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
-              .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
-  end
-
-  if (TEST === "cmp" | TEST === "all") begin: fcmp
-    fcmp fcmp   (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
-                .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
-                .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
-  end
-  if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
-     fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
-		       .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
-                       .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
-		       .XNaNE(XNaN), .YNaNE(YNaN), 
-                       .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
-                       .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
-                       .QmM(Quot),
-                       .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
-                       .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
-                       .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
-  end
-
-  assign CmpFlg[3:0] = 0;
-
-  // produce clock
-  always begin
-    clk = 1; #5; clk = 0; #5;
-  end
-
-  // Provide reset for divsqrt to reset state to IDLE
-  // Previous version did not initiate a divide due to missing state
-  // information.  This starts the FSM by putting the fdivsqrt into
-  // the IDLE state.
-  initial
-  begin
-    #0 reset = 1'b1;
-    #25 reset = 1'b0;     
-  end  
-  
-///////////////////////////////////////////////////////////////////////////////////////////////
-
-//          |||||      |||  ||||||||||  |||||      |||
-//          |||||||    |||  |||    |||  |||||||    |||
-//          |||| |||   |||  ||||||||||  |||| |||   |||
-//          ||||  |||  |||  |||    |||  ||||  |||  |||
-//          ||||   ||| |||  |||    |||  ||||   ||| |||
-//          ||||    ||||||  |||    |||  ||||    ||||||
-
-///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // Check if the correct answer and result is a NaN
-  always_comb begin
-    if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
-      // an integer output can't be a NaN
-      AnsNaN = 1'b0;
-      ResNaN = 1'b0;
-    end
-    else if (UnitVal === `CVTFPUNIT) begin
-      case (OpCtrlVal[1:0])
-          4'b11: begin // quad             
-            AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]);
-            ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]);
-          end
-          4'b01: begin // double                 
-            AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]);
-            ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]);
-          end
-          4'b00: begin // single
-            AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]);
-            ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]);
-          end
-          4'b10: begin // half
-            AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]);
-            ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]);
-          end
-      endcase
-    end
-    else begin
-      case (FmtVal)
-          4'b11: begin // quad             
-            AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]);
-            ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]);
-          end
-          4'b01: begin // double                 
-            AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]);
-            ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]);
-          end
-          4'b00: begin // single
-            AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]);
-            ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]);
-          end
-          4'b10: begin // half
-            AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]);
-            ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]);
-          end
-      endcase
-    end
-  end
-always_comb begin
-    // select the result to check
-    case (UnitVal)
-      `FMAUNIT: Res = FpRes;
-      `DIVUNIT: Res = FpRes;
-      `CMPUNIT: Res = CmpRes;
-      `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes;
-      `CVTFPUNIT: Res = FpRes;
-    endcase
-
-    // select the flag to check
-    case (UnitVal)
-      `FMAUNIT: ResFlg = Flg;
-      `DIVUNIT: ResFlg = Flg;
-      `CMPUNIT: ResFlg = CmpFlg;
-      `CVTINTUNIT: ResFlg = Flg;
-      `CVTFPUNIT: ResFlg = Flg;
-    endcase
-end
-
-  logic ResMatch, FlagMatch, CheckNow;
-
-always @(posedge clk) 
-  OldFDivBusyE = FDivDoneE;
-
-// check results on falling edge of clk
-always @(negedge clk) begin
-
-
-    // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
-    //    - the sign of the NaN does not matter for the opperations being tested
-    //    - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
-    if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
-      case (FmtVal)
-        4'b11: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
-                          (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | 
-                          (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) |
-                          (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]})));
-        4'b01: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
-                          (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | 
-                          (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) |
-                          (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})));
-        4'b00: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
-                          (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | 
-                          (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) |
-                          (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})));
-        4'b10: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
-                          (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | 
-                          (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) |
-                          (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})));
-      endcase
-    else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
-      case (OpCtrlVal[1:0]) 
-        2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | 
-                          (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | 
-                          (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})));
-        2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | 
-                          (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | 
-                          (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})));
-        2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | 
-                          (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | 
-                          (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})));
-        2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | 
-                          (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | 
-                          (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})));
-      endcase
-    else NaNGood = 1'b0; // integers can't be NaNs
-
-    
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  //     ||||||| |||    ||| ||||||| ||||||| |||   |||
-  //     |||     |||    ||| |||     |||     |||  |||
-  //     |||     |||||||||| ||||||| |||     ||||||
-  //     |||     |||    ||| |||     |||     |||  |||
-  //     ||||||| |||    ||| ||||||| ||||||| |||    |||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-    // check if result is correct
-    //  - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
-   // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
-    ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
-    FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
-    divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
-    assign DivDone = OldFDivBusyE & ~FDivBusyE;
-
-    //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
-    CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
-    if(~(ResMatch & FlagMatch) & CheckNow) begin
-//    if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
-      errors += 1;
-      $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
-      $display("Error in %s", Tests[TestNum]);
-      $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
-      $stop;
-    end
-    
-    // TestFloat sets the result to all 1's when there is an invalid result, however in 
-    // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
-    // for an unsigned integer result 0 is also okay
-
-    // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but 
-    // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
-    else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | 
-            (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | 
-            (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
-            (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
-      errors += 1;
-      $display("There is an error in %s", Tests[TestNum]);
-      $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
-      $stop;
-    end
-
-    // Add extra clock cycles in beginning for fdivsqrt to adequate reset state
-    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
-       repeat (12)
-	 @(posedge clk);
-       if (reset != 1'b1)
-	 VectorNum += 1; // increment the vector
-    end
+   // instantiate devices under test
+   if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
+      fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), 
+		   .Xe(Xe), .Ye(Ye), .Ze(Ze), 
+		   .Xm(Xm), .Ym(Ym), .Zm(Zm),
+		   .XZero, .YZero, .ZZero, .Ss, .Se,
+		   .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
+		   .ASticky); 
+   end
    
-    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
+   postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
+				.OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
+				.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
+				.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
+				.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
+				.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
+				.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
+				.FmaASticky(ASticky), .FmaSe(Se),
+				.FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), 
+				.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
+   
+   if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
+      fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
+		      .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
+		      .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), 
+		      .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
+   end
 
-      // increment the test
-      TestNum += 1;
+   if (TEST === "cmp" | TEST === "all") begin: fcmp
+      fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
+                   .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
+                   .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
+   end
+   
+   if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
+      fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
+			     .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
+			     .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
+			     .XNaNE(XNaN), .YNaNE(YNaN), 
+			     .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
+			     .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+			     .QmM(Quot),
+			     .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
+			     .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
+			     .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
+   end
 
-      // clear the vectors
-      for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
-      // read next files
-      $readmemh({`PATH, Tests[TestNum]}, TestVectors);
+   assign CmpFlg[3:0] = 0;
 
-      // set the vector index back to 0
-      VectorNum = 0;
-      // incemet the operation if all the rounding modes have been tested
-      if(FrmNum === 4) OpCtrlNum += 1;
-      // increment the rounding mode or loop back to rne 
-      if(FrmNum < 4) FrmNum += 1;
-      else FrmNum = 0; 
+   // produce clock
+   always begin
+      clk = 1; #5; clk = 0; #5;
+   end
 
-      // if no more Tests - finish
-      if(Tests[TestNum] === "") begin
-        $display("\nAll Tests completed with %d errors\n", errors);
-        $stop;
-      end 
+   // Provide reset for divsqrt to reset state to IDLE
+   // Previous version did not initiate a divide due to missing state
+   // information.  This starts the FSM by putting the fdivsqrt into
+   // the IDLE state.
+   initial
+     begin
+	#0 reset = 1'b1;
+	#25 reset = 1'b0;     
+     end  
+   
+   ///////////////////////////////////////////////////////////////////////////////////////////////
 
-      $display("Running %s vectors", Tests[TestNum]);
-    end
-  end
+   //          |||||      |||  ||||||||||  |||||      |||
+   //          |||||||    |||  |||    |||  |||||||    |||
+   //          |||| |||   |||  ||||||||||  |||| |||   |||
+   //          ||||  |||  |||  |||    |||  ||||  |||  |||
+   //          ||||   ||| |||  |||    |||  ||||   ||| |||
+   //          ||||    ||||||  |||    |||  ||||    ||||||
+
+   ///////////////////////////////////////////////////////////////////////////////////////////////
+
+   // Check if the correct answer and result is a NaN
+   always_comb begin
+      if (UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
+	 // an integer output can't be a NaN
+	 AnsNaN = 1'b0;
+	 ResNaN = 1'b0;
+      end
+      else if (UnitVal === `CVTFPUNIT) begin
+	 case (OpCtrlVal[1:0])
+           4'b11: begin // quad             
+              AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]);
+              ResNaN = &Res[P.Q_LEN-2:P.NF]&(|Res[P.Q_NF-1:0]);
+           end
+           4'b01: begin // double                 
+              AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
+              ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
+           end
+           4'b00: begin // single
+              AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
+              ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
+           end
+           4'b10: begin // half
+              AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
+              ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
+           end
+	 endcase
+      end
+      else begin
+	 case (FmtVal)
+           4'b11: begin // quad             
+              AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]);
+              ResNaN = &Res[P.Q_LEN-2:P.Q_NF]&(|Res[P.Q_NF-1:0]);
+           end
+           4'b01: begin // double                 
+              AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
+              ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
+           end
+           4'b00: begin // single
+              AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
+              ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
+           end
+           4'b10: begin // half
+              AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
+              ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
+           end
+	 endcase
+      end
+   end 
+   
+   always_comb begin
+      // select the result to check
+      case (UnitVal)
+	`FMAUNIT: Res = FpRes;
+	`DIVUNIT: Res = FpRes;
+	`CMPUNIT: Res = CmpRes;
+	`CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes;
+	`CVTFPUNIT: Res = FpRes;
+      endcase
+
+      // select the flag to check
+      case (UnitVal)
+	`FMAUNIT: ResFlg = Flg;
+	`DIVUNIT: ResFlg = Flg;
+	`CMPUNIT: ResFlg = CmpFlg;
+	`CVTINTUNIT: ResFlg = Flg;
+	`CVTFPUNIT: ResFlg = Flg;
+      endcase
+   end
+
+   always @(posedge clk) 
+     OldFDivBusyE = FDivDoneE;
+
+   // For FP division this adds extra clock cycles to make sure the
+   // computation completes.  
+   always @(posedge clk) begin
+      // Add extra clock cycles in beginning for fdivsqrt to adequate reset state
+      if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
+	 // This allows specific number of clocks to allow each vector
+	 // to complete for division or square root.  It is an
+	 // arbitrary value and can be changed, if needed.
+	 case (FmtVal)
+	   // QP
+	   4'b11: begin
+	      repeat (20)
+		@(posedge clk);
+	   end
+	   // HP
+	   4'b10: begin
+	      repeat (14)
+		@(posedge clk);
+	   end
+	   // DP
+	   4'b01: begin
+	      repeat (18)
+		@(posedge clk);
+	   end
+	   // SP
+	   4'b00: begin
+	      repeat (16)
+		@(posedge clk);
+	   end
+	 endcase // case (FmtVal)	 
+	 if (reset != 1'b1)
+	   VectorNum += 1; // increment the vector
+      end
+   end
+
+   // check results on falling edge of clk
+   always @(negedge clk) begin
+      // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
+      //    - the sign of the NaN does not matter for the opperations being tested
+      //    - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
+      if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
+	case (FmtVal)
+          4'b11: NaNGood =  (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
+                             (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
+                             (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | 
+                             (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
+                             (ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
+          4'b01: NaNGood =  (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
+                             (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
+                             (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | 
+                             (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
+                             (ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
+          4'b00: NaNGood =  (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
+                             (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
+                             (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | 
+                             (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
+                             (ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
+          4'b10: NaNGood =  (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
+                             (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
+                             (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | 
+                             (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
+                             (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
+	endcase
+      else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
+	case (OpCtrlVal[1:0]) 
+          2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
+                            (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
+                            (AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) | 
+                            (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | 
+                            (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})));
+          2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
+                            (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
+                            (AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) | 
+                            (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | 
+                            (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})));
+          2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
+                            (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
+                            (AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) | 
+                            (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | 
+                            (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})));
+          2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
+                            (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
+                            (AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) | 
+                            (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | 
+                            (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
+	endcase
+      else NaNGood = 1'b0; // integers can't be NaNs
+
+      
+      ///////////////////////////////////////////////////////////////////////////////////////////////
+
+      //     ||||||| |||    ||| ||||||| ||||||| |||   |||
+      //     |||     |||    ||| |||     |||     |||  |||
+      //     |||     |||||||||| ||||||| |||     ||||||
+      //     |||     |||    ||| |||     |||     |||  |||
+      //     ||||||| |||    ||| ||||||| ||||||| |||    |||
+
+      ///////////////////////////////////////////////////////////////////////////////////////////////
+
+      // check if result is correct
+      //  wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
+      assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
+      assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
+      assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
+      assign FMAop = (OpCtrlVal == `FMAUNIT);  
+      assign DivDone = OldFDivBusyE & ~FDivBusyE;
+
+      // Maybe change OpCtrl but for now just look at TEST for fma test
+      assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
+      if (~(ResMatch & FlagMatch) & CheckNow) begin
+	 errors += 1;
+	 $display("\nError in %s", Tests[TestNum]);
+	 $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);	 
+	 $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+	 $stop;
+      end
+      
+      // TestFloat sets the result to all 1's when there is an invalid result, however in 
+      // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
+      // for an unsigned integer result 0 is also okay
+
+      // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but 
+      // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
+      else if ((UnitVal === `CVTINTUNIT) & 
+	       ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | 
+		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | 
+		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
+		  (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
+	 errors += 1;
+	 $display("There is an error in %s", Tests[TestNum]);
+	 $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+	 $stop;
+      end
+
+      if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
+	 // increment the test
+	 TestNum += 1;
+	 // clear the vectors
+	 for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
+	 // read next files
+	 $readmemh({`PATH, Tests[TestNum]}, TestVectors);
+	 // set the vector index back to 0
+	 VectorNum = 0;
+	 // incemet the operation if all the rounding modes have been tested
+	 if (FrmNum === 4) OpCtrlNum += 1;
+	 // increment the rounding mode or loop back to rne 
+	 if (FrmNum < 4) FrmNum += 1;
+	 else FrmNum = 0; 
+	 // if no more Tests - finish
+	 if (Tests[TestNum] === "") begin
+            $display("\nAll Tests completed with %d errors\n", errors);
+            $stop;
+	 end 
+	 $display("Running %s vectors", Tests[TestNum]);
+      end
+   end
 endmodule
 
 
 module readvectors (
-  input logic                clk,
-  input logic [`FLEN*4+7:0]  TestVector,
-  input logic [`FMTBITS-1:0] ModFmt,
-  input logic [1:0]          Fmt,
-  input logic [2:0]          Unit,
-  input logic [31:0]         VectorNum,
-  input logic [31:0]         TestNum,
-  input logic [2:0]          OpCtrl,
-  output logic [`FLEN-1:0]   Ans,
-  output logic [`XLEN-1:0]   SrcA,
-  output logic [4:0]         AnsFlg,
-  output logic               Xs, Ys, Zs, // sign bits of XYZ
-  output logic [`NE-1:0]     Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]       Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
-  output logic               XNaN, YNaN, ZNaN, // is XYZ a NaN
-  output logic               XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
-  output logic               XSubnorm, ZSubnorm,  // is XYZ denormalized
-  output logic               XZero, YZero, ZZero, // is XYZ zero
-  output logic               XInf, YInf, ZInf,    // is XYZ infinity
-  output logic               XExpMax,
-  output logic               DivStart,
-  output logic [`FLEN-1:0]   X, Y, Z, XPostBox
-);
-  logic XEn, YEn, ZEn;
+		    input logic 	        clk,
+		    input logic [P.FLEN*4+7:0]  TestVector,
+		    input logic [P.FMTBITS-1:0] ModFmt,
+		    input logic [1:0] 	        Fmt,
+		    input logic [2:0] 	        Unit,
+		    input logic [31:0] 	        VectorNum,
+		    input logic [31:0] 	        TestNum,
+		    input logic [2:0] 	        OpCtrl,
+		    output logic [P.FLEN-1:0]   Ans,
+		    output logic [P.XLEN-1:0]   SrcA,
+		    output logic [4:0] 	        AnsFlg,
+		    output logic 	        Xs, Ys, Zs, // sign bits of XYZ
+		    output logic [P.NE-1:0]     Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
+		    output logic [P.NF:0]       Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
+		    output logic 	        XNaN, YNaN, ZNaN, // is XYZ a NaN
+		    output logic 	        XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
+		    output logic 	        XSubnorm, ZSubnorm, // is XYZ denormalized
+		    output logic 	        XZero, YZero, ZZero, // is XYZ zero
+		    output logic 	        XInf, YInf, ZInf, // is XYZ infinity
+		    output logic 	        XExpMax,
+		    output logic 	        DivStart,
+		    output logic [P.FLEN-1:0]   X, Y, Z, XPostBox
+		    );
 
-  // apply test vectors on rising edge of clk
-  // Format of vectors Inputs(1/2/3)_AnsFlg
-  always @(VectorNum) begin
-    #1; 
-    AnsFlg = TestVector[4:0];
-    DivStart = 1'b0;
-    case (Unit)
-      `FMAUNIT:
-        case (Fmt)
-          2'b11: begin       // quad
-            if(OpCtrl === `FMA_OPCTRL) begin
-              X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)];
-              Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
-              Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN];
-            end
-            else begin
-              X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
-              if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)};
-              if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
-            end
-            Ans = TestVector[8+(`Q_LEN-1):8];
-          end
-          2'b01:	if (`D_SUPPORTED)begin	  // double
-            if(OpCtrl === `FMA_OPCTRL) begin
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]};
-              Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
-              Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]};
-            end
-            else begin
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
-              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; 
-              else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)};
-              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; 
-              else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
-            end
-            Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-          end
-          2'b00:	if (`S_SUPPORTED)begin	  // single
-            if(OpCtrl === `FMA_OPCTRL) begin
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]};
-              Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
-              Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]};
-            end
-            else begin
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
-              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; 
-              else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)};
-              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; 
-              else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]};
-            end
-            Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-          end
-          2'b10:	begin	  // half
-            if(OpCtrl === `FMA_OPCTRL) begin
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]};
-              Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
-              Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]};
-            end
-            else begin
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
-              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; 
-              else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)};
-              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; 
-              else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
-            end
-            Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-          end
-        endcase
-      `DIVUNIT:
-        if(OpCtrl[0])
+   localparam Q_LEN = 32'd128;
+  `include "parameter-defs.vh"   
+   
+   logic 					XEn;
+   logic 					YEn;
+   logic 					ZEn;
+   logic 					FPUActive;   
+
+   // apply test vectors on rising edge of clk
+   // Format of vectors Inputs(1/2/3)_AnsFlg
+   always @(VectorNum) begin
+      DivStart = 1'b0;      
+      #1;
+      AnsFlg = TestVector[4:0];
+      case (Unit)
+	`FMAUNIT:
           case (Fmt)
-            2'b11: begin       // quad
-              X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
-              Ans = TestVector[8+(`Q_LEN-1):8];
-              if (~clk) #5;
-              DivStart = 1'b1; #10 // one clk cycle
-              DivStart = 1'b0;
+            2'b11: begin // quad
+               if (OpCtrl === `FMA_OPCTRL) begin
+		  X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
+		  Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
+		  Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN];
+               end
+               else begin
+		  X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
+		  if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
+		  if (OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
+               end
+               Ans = TestVector[8+(P.Q_LEN-1):8];
             end
-            2'b01:	if (`D_SUPPORTED)begin	  // double
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b01: if (P.D_SUPPORTED) begin // double
+               if (OpCtrl === `FMA_OPCTRL) begin
+		  X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
+		  Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
+		  Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
+               end
+               else begin
+		  X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
+		  if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; 
+		  else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
+		  if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}; 
+		  else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
+               end
+               Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
             end
-            2'b00:	if (`S_SUPPORTED)begin	  // single
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b00: if (P.S_SUPPORTED) begin // single
+               if (OpCtrl === `FMA_OPCTRL) begin
+		  X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
+		  Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
+		  Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
+               end
+               else begin
+		  X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
+		  if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; 
+		  else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
+		  if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}; 
+		  else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
+               end
+               Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
             end
-            2'b10:	begin	  // half
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b10: begin // half
+               if (OpCtrl === `FMA_OPCTRL) begin
+		  X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
+		  Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
+		  Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
+               end
+               else begin
+		  X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
+		  if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; 
+		  else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
+		  if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}; 
+		  else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
+               end
+               Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
             end
           endcase
-        else
+	`DIVUNIT:
+          if (OpCtrl[0])
+            case (Fmt)
+              2'b11: begin // quad
+		 #20;		 
+		 X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
+		 Ans = TestVector[8+(P.Q_LEN-1):8];
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10 // one clk cycle
+		   DivStart = 1'b0;
+              end
+              2'b01: if (P.D_SUPPORTED) begin // double
+		 #20;		 
+		 X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
+		 Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+              2'b00: if (P.S_SUPPORTED) begin // single
+		 #20;		 
+		 X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
+		 Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+              2'b10: begin // half
+		 #20;		 
+		 X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
+		 Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+            endcase
+          else
+            case (Fmt)
+              2'b11: begin // quad
+		 #20;		 
+		 X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
+		 Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
+		 Ans = TestVector[8+(P.Q_LEN-1):8];
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10 // one clk cycle
+		   DivStart = 1'b0;
+              end
+              2'b01: if (P.D_SUPPORTED) begin // double
+		 #20;		 
+		 X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
+		 Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
+		 Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+              2'b00: if (P.S_SUPPORTED) begin // single
+		 #20;		 
+		 X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
+		 Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
+		 Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+              2'b10: begin // half
+		 #20;		 
+		 X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
+		 Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
+		 Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 if (~clk) #5;
+		 DivStart = 1'b1; #10
+		   DivStart = 1'b0;
+              end
+            endcase
+	`CMPUNIT:
+          case (Fmt)        
+            2'b11: begin // quad
+               X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
+               Y = TestVector[12+(P.Q_LEN)-1:12];
+               Ans = TestVector[8];
+            end
+            2'b01: if (P.D_SUPPORTED) begin // double
+               X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
+               Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
+               Ans = TestVector[8];
+            end
+            2'b00: if (P.S_SUPPORTED) begin // single
+               X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
+               Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
+               Ans = TestVector[8];
+            end
+            2'b10: begin // half
+               X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
+               Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
+               Ans = TestVector[8];
+            end
+          endcase
+	`CVTFPUNIT:
           case (Fmt)
-            2'b11: begin       // quad
-              X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
-              Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
-              Ans = TestVector[8+(`Q_LEN-1):8];
-              if (~clk) #5;
-              DivStart = 1'b1; #10 // one clk cycle
-              DivStart = 1'b0;
+            2'b11: begin // quad
+               case (OpCtrl[1:0])
+		 2'b11: begin // quad
+		    X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
+		    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b01:	if (P.D_SUPPORTED) begin // double
+		    X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
+		    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b00:	begin // single
+		    X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
+		    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b10:	begin // half
+		    X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
+		    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+               endcase
             end
-            2'b01:	if (`D_SUPPORTED)begin	  // double
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
-              Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b01: if (P.D_SUPPORTED) begin // double
+               case (OpCtrl[1:0])
+		 2'b11: begin // quad
+		    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
+		    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b01:	begin // double
+		    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
+		    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b00:	begin // single
+		    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
+		    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b10:	begin // half
+		    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
+		    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+               endcase
             end
-            2'b00:	if (`S_SUPPORTED)begin	  // single
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
-              Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b00: if (P.S_SUPPORTED) begin // single
+               case (OpCtrl[1:0])
+		 2'b11: begin // quad
+		    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
+		    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b01:	if (P.D_SUPPORTED) begin // double
+		    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
+		    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b00:	begin // single
+		    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
+		    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b10:	begin // half
+		    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
+		    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+               endcase
             end
-            2'b10:	begin	  // half
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
-              Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-              if (~clk) #5;
-              DivStart = 1'b1; #10
-              DivStart = 1'b0;
+            2'b10: begin // half
+               case (OpCtrl[1:0])
+		 2'b11: begin // quad
+		    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
+		    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b01:	if (P.D_SUPPORTED) begin // double
+		    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
+		    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b00:	if (P.S_SUPPORTED) begin // single
+		    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
+		    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b10:	begin // half
+		    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
+		    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+               endcase
+            end
+          endcase        
+	`CVTINTUNIT:
+          case (Fmt)
+            2'b11: begin // quad
+               // {is the integer a long, is the opperation to an integer}
+               casex ({OpCtrl[2:1]})
+		 2'b11: begin // long -> quad
+                    X = {P.FLEN{1'bx}};
+                    SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
+                    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b10:	begin // int -> quad
+                    // correctly sign extend the integer depending on if it's a signed/unsigned test
+                    X = {P.FLEN{1'bx}};
+                    SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
+                    Ans = TestVector[8+(P.Q_LEN-1):8];
+		 end
+		 2'b01:	begin // quad -> long
+                    X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {TestVector[8+(P.XLEN-1):8]};
+		 end
+		 2'b00:	begin // quad -> int
+                    X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+		 end
+               endcase
+            end
+            2'b01: if (P.D_SUPPORTED) begin // double
+               // {Int->Fp?, is the integer a long}
+               casex ({OpCtrl[2:1]})
+		 2'b11: begin // long -> double
+                    X = {P.FLEN{1'bx}};
+                    SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
+                    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b10:	begin // int -> double
+                    // correctly sign extend the integer depending on if it's a signed/unsigned test
+                    X = {P.FLEN{1'bx}};
+                    SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
+                    Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
+		 end
+		 2'b01:	begin // double -> long
+                    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {TestVector[8+(P.XLEN-1):8]};
+		 end
+		 2'b00:	begin // double -> int
+                    X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+		 end
+               endcase
+            end
+            2'b00: if (P.S_SUPPORTED) begin // single
+               // {is the integer a long, is the opperation to an integer}
+               casex ({OpCtrl[2:1]})
+		 2'b11: begin // long -> single
+                    X = {P.FLEN{1'bx}};
+                    SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
+                    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b10:	begin // int -> single
+                    // correctly sign extend the integer depending on if it's a signed/unsigned test
+                    X = {P.FLEN{1'bx}};
+                    SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
+                    Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
+		 end
+		 2'b01:	begin // single -> long
+                    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {TestVector[8+(P.XLEN-1):8]};
+		 end
+		 2'b00:	begin // single -> int
+                    X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+		 end
+               endcase
+            end
+            2'b10: begin // half
+               // {is the integer a long, is the opperation to an integer}
+               casex ({OpCtrl[2:1]})
+		 2'b11: begin // long -> half
+                    X = {P.FLEN{1'bx}};
+                    SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
+                    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+		 2'b10:	begin // int -> half
+                    // correctly sign extend the integer depending on if it's a signed/unsigned test
+                    X = {P.FLEN{1'bx}};
+                    SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
+                    Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
+		 end
+		 2'b01:	begin // half -> long
+                    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {TestVector[8+(P.XLEN-1):8]};
+		 end
+		 2'b00:	begin // half -> int
+                    X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
+                    SrcA = {P.XLEN{1'bx}};
+                    Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
+		 end
+               endcase
             end
           endcase
-      `CMPUNIT:
-        case (Fmt)        
-          2'b11: begin       // quad
-            X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)];
-            Y = TestVector[12+(`Q_LEN)-1:12];
-            Ans = TestVector[8];
-          end
-          2'b01:	if (`D_SUPPORTED)begin	  // double
-            X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]};
-            Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]};
-            Ans = TestVector[8];
-          end
-          2'b00:	if (`S_SUPPORTED)begin	  // single
-            X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]};
-            Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]};
-            Ans = TestVector[8];
-          end
-          2'b10:	begin	  // half
-            X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]};
-            Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]};
-            Ans = TestVector[8];
-          end
-        endcase
-      `CVTFPUNIT:
-        case (Fmt)
-          2'b11: begin       // quad
-          case (OpCtrl[1:0])
-            2'b11: begin       // quad
-              X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]};
-              Ans = TestVector[8+(`Q_LEN-1):8];
-            end
-            2'b01:	if (`D_SUPPORTED)begin	  // double
-              X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-            end
-            2'b00:	begin	  // single
-              X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-            end
-            2'b10:	begin	  // half
-              X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-            end
-          endcase
-          end
-          2'b01:	if (`D_SUPPORTED)begin	  // double
-          case (OpCtrl[1:0])
-            2'b11: begin       // quad
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]};
-              Ans = TestVector[8+(`Q_LEN-1):8];
-            end
-            2'b01:	begin	  // double
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-            end
-            2'b00:	begin	  // single
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-            end
-            2'b10:	begin	  // half
-              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-            end
-          endcase
-          end
-          2'b00:	if (`S_SUPPORTED)begin	  // single
-          case (OpCtrl[1:0])
-            2'b11: begin       // quad
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]};
-              Ans = TestVector[8+(`Q_LEN-1):8];
-            end
-            2'b01:	if (`D_SUPPORTED)begin	  // double
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-            end
-            2'b00:	begin	  // single
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-            end
-            2'b10:	begin	  // half
-              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-            end
-          endcase
-          end
-          2'b10:	begin	  // half
-          case (OpCtrl[1:0])
-            2'b11: begin       // quad
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]};
-              Ans = TestVector[8+(`Q_LEN-1):8];
-            end
-            2'b01:	if (`D_SUPPORTED)begin	  // double
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]};
-              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-            end
-            2'b00:	if (`S_SUPPORTED)begin	  // single
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]};
-              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-            end
-            2'b10:	begin	  // half
-              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]};
-              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-            end
-          endcase
-          end
-        endcase
-        
-      `CVTINTUNIT:
-        case (Fmt)
-          2'b11: begin       // quad
-            //     {is the integer a long,     is the opperation to an integer}
-            casex ({OpCtrl[2:1]})
-              2'b11: begin       // long -> quad
-                X = {`FLEN{1'bx}};
-                SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)];
-                Ans = TestVector[8+(`Q_LEN-1):8];
-              end
-              2'b10:	begin	  // int -> quad
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {`FLEN{1'bx}};
-                SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]};
-                Ans = TestVector[8+(`Q_LEN-1):8];
-              end
-              2'b01:	begin	  // quad -> long
-                X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {TestVector[8+(`XLEN-1):8]};
-              end
-              2'b00:	begin	  // quad -> int
-                X = {TestVector[8+32+`Q_LEN-1:8+(32)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b01:	if (`D_SUPPORTED)begin	  // double
-            //     {Int->Fp?, is the integer a long}
-            casex ({OpCtrl[2:1]})
-              2'b11: begin       // long -> double
-                X = {`FLEN{1'bx}};
-                SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)];
-                Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-              end
-              2'b10:	begin	  // int -> double
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {`FLEN{1'bx}};
-                SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]};
-                Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-              end
-              2'b01:	begin	  // double -> long
-                X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {TestVector[8+(`XLEN-1):8]};
-              end
-              2'b00:	begin	  // double -> int
-                X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b00:	if (`S_SUPPORTED)begin	  // single
-            //     {is the integer a long,     is the opperation to an integer}
-            casex ({OpCtrl[2:1]})
-              2'b11: begin       // long -> single
-                X = {`FLEN{1'bx}};
-                SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)];
-                Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-              end
-              2'b10:	begin	  // int -> single
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {`FLEN{1'bx}};
-                SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]};
-                Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-              end
-              2'b01:	begin	  // single -> long
-                X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {TestVector[8+(`XLEN-1):8]};
-              end
-              2'b00:	begin	  // single -> int
-                X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b10:	begin	  // half
-            //     {is the integer a long,     is the opperation to an integer}
-            casex ({OpCtrl[2:1]})
-              2'b11: begin       // long -> half
-                X = {`FLEN{1'bx}};
-                SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)];
-                Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-              end
-              2'b10:	begin	  // int -> half
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {`FLEN{1'bx}};
-                SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]};
-                Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-              end
-              2'b01:	begin	  // half -> long
-                X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {TestVector[8+(`XLEN-1):8]};
-              end
-              2'b00:	begin	  // half -> int
-                X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]};
-                SrcA = {`XLEN{1'bx}};
-                Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-        endcase
-    endcase  
-  end
-  
-  assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
-  assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
-  assign ZEn = (Unit == `FMAUNIT);
-  
-  unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
-                .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
-                .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
-                .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
+      endcase  
+   end
+
+   assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
+   assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
+   assign ZEn = (Unit == `FMAUNIT);
+   // Will fix with better activation - for now, this works (jes)
+   assign FPUActive = 1'b1;
+   
+   unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
+                      .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
+                      .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
+                      .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
 endmodule
diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv
index d3d71626f..79b354cb0 100644
--- a/testbench/testbench-linux-imperas.sv
+++ b/testbench/testbench-linux-imperas.sv
@@ -30,7 +30,7 @@
 // `define USE_IMPERAS_DV
 
 `ifdef USE_IMPERAS_DV
-  `include "rvvi/imperasDV.svh"
+    `include "idv/idv.svh"
 `endif
 
 `define DEBUG_TRACE 0
@@ -55,7 +55,7 @@ module testbench;
 
 
   `ifdef USE_IMPERAS_DV
-    import rvviPkg::*;
+    import idvPkg::*;
     import rvviApiPkg::*;
     import idvApiPkg::*;
   `endif
@@ -302,7 +302,7 @@ module testbench;
       initial begin
         int iter;
         #1;
-        MAX_ERRS = 3;
+        IDV_MAX_ERRS = 3;
 
         // Initialize REF (do this before initializing the DUT)
         if (!rvviVersionCheck(RVVI_API_VERSION)) begin
@@ -866,10 +866,12 @@ module testbench;
             "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
             "mepc":    `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
             "mtval":   `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
+            "menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW)
             "sepc":    `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
             "scause":  `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
             "stvec":   `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
             "stval":   `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
+            "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
             "mip": begin
                        `checkCSR(`CSR_BASE.csrm.MIP_REGW)
                        if(!NO_SPOOFING) begin
diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
index 908660ffe..5c83aca29 100644
--- a/testbench/testbench-linux.sv
+++ b/testbench/testbench-linux.sv
@@ -24,7 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
+import cvw::*;
 
 `define DEBUG_TRACE 0
 // Debug Levels
@@ -47,12 +48,7 @@ module testbench;
   parameter NO_SPOOFING = 0;
 
 
-
-
-
-
-
-
+`include "parameter-defs.vh"
 
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -85,40 +81,40 @@ module testbench;
       integer TokenIndex``STAGE; \
       integer MarkerIndex``STAGE; \
       integer NumCSR``STAGE; \
-      logic [`XLEN-1:0] ExpectedPC``STAGE; \
+      logic [P.XLEN-1:0] ExpectedPC``STAGE; \
       logic [31:0]      ExpectedInstr``STAGE; \
       string            text``STAGE; \
       string            MemOp``STAGE; \
       string            RegWrite``STAGE; \
       integer           ExpectedRegAdr``STAGE; \
-      logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
-      logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
+      logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \
+      logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
       string            ExpectedCSRArray``STAGE[10:0]; \
-      logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
+      logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
   `DECLARE_TRACE_SCANNER_SIGNALS(E)
   `DECLARE_TRACE_SCANNER_SIGNALS(M)
   //  M-stage expected values
   logic             checkInstrM;
   integer           MIPexpected, SIPexpected;
   string            name;
-  logic [`AHBW-1:0] readDataExpected;
+  logic [P.AHBW-1:0] readDataExpected;
   // W-stage expected values
   logic             checkInstrW;
-  logic [`XLEN-1:0] ExpectedPCW;
+  logic [P.XLEN-1:0] ExpectedPCW;
   logic [31:0]      ExpectedInstrW;
   string            textW;
   string            RegWriteW;
   integer           ExpectedRegAdrW;
-  logic [`XLEN-1:0] ExpectedRegValueW;
+  logic [P.XLEN-1:0] ExpectedRegValueW;
   string            MemOpW;
-  logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
+  logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
   integer           NumCSRW;
   string            ExpectedCSRArrayW[10:0];
-  logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
-  logic [`XLEN-1:0] ExpectedIntType;
+  logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0];
+  logic [P.XLEN-1:0] ExpectedIntType;
   integer           NumCSRWIndex;
   integer           NumCSRPostWIndex;
-  logic [`XLEN-1:0] InstrCountW;
+  logic [P.XLEN-1:0] InstrCountW;
   // ========== Interrupt parsing & spoofing ==========
   string  interrupt;
   string  interruptLine;
@@ -132,7 +128,7 @@ module testbench;
   string  interruptDesc;
   integer           NextMIPexpected, NextSIPexpected;
   integer           NextMepcExpected;
-  logic [`XLEN-1:0] AttemptedInstructionCount;
+  logic [P.XLEN-1:0] AttemptedInstructionCount;
   // ========== Misc Aliases ==========
   `define RF dut.core.ieu.dp.regf.rf
   `define PC dut.core.ifu.pcreg.q
@@ -238,14 +234,14 @@ module testbench;
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
   // Wally Interface
-  logic [`AHBW-1:0] HRDATAEXT;
+  logic [P.AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
   logic             HCLK, HRESETn;
   logic             HREADY;
   logic 	    HSELEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0] HWDATA;
-  logic [`XLEN/8-1:0] HWSTRB;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0] HWDATA;
+  logic [P.XLEN/8-1:0] HWSTRB;
   logic             HWRITE;
   logic [2:0]       HSIZE;
   logic [2:0]       HBURST;
@@ -268,7 +264,7 @@ module testbench;
   assign UARTSin = 1;
 
   // Wally
-  wallypipelinedsoc dut(.clk, .reset, .reset_ext,
+  wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
                         .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
 			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
 			.HTRANS, .HMASTLOCK, 
@@ -278,18 +274,18 @@ module testbench;
 
   // W-stage hardware not needed by Wally itself 
   parameter nop = 'h13;
-  logic [`XLEN-1:0] PCW;
+  logic [P.XLEN-1:0] PCW;
   logic [31:0]      InstrW;
   logic             InstrValidW;
-  logic [`XLEN-1:0] IEUAdrW, WriteDataW;
+  logic [P.XLEN-1:0] IEUAdrW, WriteDataW;
   logic             TrapW;
   `define FLUSHW dut.core.FlushW
   `define STALLW dut.core.StallW
-  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
+  flopenrc #(P.XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
-  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
+  flopenrc #(P.XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
+  flopenrc #(P.XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
 
 
@@ -365,29 +361,29 @@ module testbench;
     end
 
   genvar i;
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [`XLEN-1:0],31,1);
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
-  `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [P.XLEN-1:0],31,1);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0);
+  `INIT_CHECKPOINT_VAL(PC,         [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEDELEG,    [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MIDELEG,    [P.XLEN-1:0]);
   if(!NO_SPOOFING) begin
     `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
     `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
     end
-  `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEPC,       [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SEPC,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEPC,       [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SEPC,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
   `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
-  `INIT_CHECKPOINT_VAL(MSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MTVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(STVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MTVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(STVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SATP,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
-  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0);
+  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0);
   `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
   // UART checkpointing does not cover entire UART state
   //     Many UART registers are difficult to initialize because under the hood
@@ -402,8 +398,8 @@ module testbench;
   `INIT_CHECKPOINT_VAL(UART_SCR,   [7:0]);
   // xSTATUS need to be handled manually because the most upstream signals
   // are made of individual bits, not registers
-  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);  
+  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0);  
 
   // ========== INITIALIZATION ==========
   initial begin
@@ -458,7 +454,7 @@ module testbench;
       force {`STATUS_SPIE} = initMSTATUS[0][5];
       force {`STATUS_MIE} = initMSTATUS[0][3];
       force {`STATUS_SIE} = initMSTATUS[0][1];
-      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
+      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
       force `INSTRET = CHECKPOINT;
       while (reset!==1) #1;
       while (reset!==0) #1;
@@ -789,7 +785,7 @@ module testbench;
   //////////////////////////////// Extra Features ///////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
   // Function Tracking
-  FunctionName FunctionName(.reset(reset),
+  FunctionName #(P) FunctionName(.reset(reset),
                             .clk(clk),
                             .ProgramAddrMapFile(ProgramAddrMapFile),
                             .ProgramLabelMapFile(ProgramLabelMapFile));
@@ -814,12 +810,12 @@ module testbench;
    * explanation of the below algorithm.
    */
   logic             SvMode, PTE_R, PTE_X;
-  logic [`XLEN-1:0] SATP, PTE;
+  logic [P.XLEN-1:0] SATP, PTE;
   logic [55:0]      BaseAdr, PAdr;
   logic [8:0]       VPN [2:0];
   logic [11:0]      Offset;
-  function logic [`XLEN-1:0] adrTranslator( 
-    input logic [`XLEN-1:0] adrIn);
+  function logic [P.XLEN-1:0] adrTranslator( 
+    input logic [P.XLEN-1:0] adrIn);
     begin
       int i;
       // Grab the SATP register from privileged unit
diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv
new file mode 100644
index 000000000..368cc3f07
--- /dev/null
+++ b/testbench/testbench-xcelium.sv
@@ -0,0 +1,606 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+`include "tests.vh"
+
+import cvw::*;
+
+module testbench;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
+  parameter DEBUG=0;
+  parameter TEST="none";
+  parameter PrintHPMCounters=1;
+  parameter BPRED_LOGGER=0;
+  parameter I_CACHE_ADDR_LOGGER=0;
+  parameter D_CACHE_ADDR_LOGGER=0;
+ 
+`include "parameter-defs.vh"
+
+  logic        clk;
+  logic        reset_ext, reset;
+  logic        ResetMem;
+
+  // DUT signals
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                 HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                 HWRITE;
+  logic [2:0]           HSIZE;
+  logic [2:0]           HBURST;
+  logic [3:0]           HPROT;
+  logic [1:0]           HTRANS;
+  logic                 HMASTLOCK;
+  logic                 HCLK, HRESETn;
+
+  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1  [3:0]  SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+
+  
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
+  integer ProgramAddrLabelArray [string];
+
+  int test, i, errors, totalerrors;
+
+  string outputfile;
+  integer outputFilePointer;
+
+  string tests[];
+  logic DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
+  logic Validate;
+  logic SelectTest;
+
+  
+
+  // pick tests based on modes supported
+  initial begin
+    $display("TEST is %s", TEST);
+    //tests = '{};
+    if (P.XLEN == 64) begin // RV64
+      case (TEST)
+        "arch64i":                               tests = arch64i;
+        "arch64priv":                            tests = arch64priv;
+        "arch64c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
+                          else                   tests = {arch64c};
+        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
+        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
+        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
+        "arch64f_fma":      if (P.F_SUPPORTED)        tests = arch64f_fma;
+        "arch64d_fma":      if (P.D_SUPPORTED)        tests = arch64d_fma;  
+        "arch64zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "imperas64i":                            tests = imperas64i;
+        "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
+        "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
+        "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
+        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
+                        else                     tests = imperas64iNOc;
+        "custom":                                tests = custom;
+        "wally64i":                              tests = wally64i; 
+        "wally64priv":                           tests = wally64priv;
+        "wally64periph":                         tests = wally64periph;
+        "coremark":                              tests = coremark;
+        "fpga":                                  tests = fpga;
+        "ahb" :                                  tests = ahb;
+        "coverage64gc" :                         tests = coverage64gc;
+        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
+        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
+        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
+        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
+      endcase 
+    end else begin // RV32
+      case (TEST)
+        "arch32i":                               tests = arch32i;
+        "arch32priv":                            tests = arch32priv;
+        "arch32c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
+                          else                   tests = {arch32c};
+        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
+        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
+        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
+        "arch32f_fma":      if (P.F_SUPPORTED)        tests = arch32f_fma;
+        "arch32d_fma":      if (P.D_SUPPORTED)        tests = arch32d_fma;
+        "arch32zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "imperas32i":                            tests = imperas32i;
+        "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
+        "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
+        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
+                        else                     tests = imperas32iNOc;
+        "wally32i":                              tests = wally32i; 
+        "wally32e":                              tests = wally32e; 
+        "wally32priv":                           tests = wally32priv;
+        "wally32periph":                         tests = wally32periph;
+        "embench":                               tests = embench;
+        "coremark":                              tests = coremark;
+        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
+        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
+        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
+        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
+      endcase
+    end
+    if (tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end // initial begin
+
+  // Model the testbench as an fsm.
+  // Do this in parts so it easier to verify
+  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
+  // part 2: drive some of the controls
+  // part 3: drive all logic and remove old inital and always @ negedge clk block
+
+  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
+                           STATE_INIT_TEST,
+                           STATE_RESET_MEMORIES,
+                           STATE_RESET_MEMORIES2,
+                           STATE_LOAD_MEMORIES,
+                           STATE_RESET_TEST,
+                           STATE_RUN_TEST,
+                           STATE_CHECK_TEST,
+                           STATE_CHECK_TEST_WAIT,
+                           STATE_VALIDATE,
+                           STATE_INCR_TEST} statetype;
+  statetype CurrState, NextState;
+  logic        TestBenchReset;
+  logic [2:0]  ResetCount, ResetThreshold;
+  logic        LoadMem;
+  logic        ResetCntEn;
+  logic        ResetCntRst;
+  
+
+  string  signame, memfilename, pathname;
+  integer begin_signature_addr;
+
+  assign ResetThreshold = 3'd5;
+
+  initial begin
+    TestBenchReset = 1;
+    # 100;
+    TestBenchReset = 0;
+  end
+
+  always_ff @(posedge clk)
+    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
+    else CurrState <= #1 NextState;  
+
+  // fsm next state logic
+  always_comb begin
+    // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
+    // and tests[0] == "2" refers to WallyRiscvArchTests 
+    riscofTest = tests[0] == "1" | tests[0] == "2"; 
+    pathname = tvpaths[tests[0].atoi()];
+
+    case(CurrState)
+      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
+      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
+      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
+      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
+      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
+      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_RUN_TEST:        if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
+      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
+      default:                                    NextState = STATE_TESTBENCH_RESET;
+    endcase
+  end // always_comb
+  // fsm output control logic 
+  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | 
+                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | 
+                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
+  // this initialization is very expensive, only do it for coremark.  
+  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
+  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
+  assign ResetCntRst = CurrState == STATE_INIT_TEST;
+  assign ResetCntEn = CurrState == STATE_RESET_TEST;
+  assign Validate = CurrState == STATE_VALIDATE;
+  assign SelectTest = CurrState == STATE_INIT_TEST;
+
+  // fsm reset counter
+  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Find the test vector files and populate the PC to function label converter
+  ////////////////////////////////////////////////////////////////////////////////
+  logic [P.XLEN-1:0] testadr;
+  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+  always @(posedge clk) begin
+    if(SelectTest) begin
+      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else            memfilename = {pathname, tests[test], ".elf.memfile"};
+      if (riscofTest) begin
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else begin
+        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+      end
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
+      // the addr of each label and fill the array. To expand, add more elements to this array 
+      // and initialize them to zero (also initilaize them to zero at the start of the next test)
+      if(!P.FPGA) begin
+        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+      end
+    end
+    
+  ////////////////////////////////////////////////////////////////////////////////
+  // Verify the test ran correctly by checking the memory against a known signature.
+  ////////////////////////////////////////////////////////////////////////////////
+    if(TestBenchReset) test = 1;
+    if (TEST == "coremark")
+      if (dut.core.EcallFaultM) begin
+        $display("Benchmark: coremark is done.");
+        $stop;
+      end
+    if(Validate) begin
+      if (TEST == "embench") begin
+        // Writes contents of begin_signature to .sim.output file
+        // this contains instret and cycles for start and end of test run, used by embench 
+        // python speed script to calculate embench speed score. 
+        // also, begin_signature contains the results of the self checking mechanism, 
+        // which will be read by the python script for error checking
+        $display("Embench Benchmark: %s is done.", tests[test]);
+        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+        else outputfile = {pathname, tests[test], ".sim.output"};
+        outputFilePointer = $fopen(outputfile, "w");
+        i = 0;
+        testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+        while ($unsigned(i) < $unsigned(5'd5)) begin
+          $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+          i = i + 1;
+        end
+        $fclose(outputFilePointer);
+        $display("Embench Benchmark: created output file: %s", outputfile);
+      end else if (TEST == "coverage64gc") begin
+        $display("Coverage tests don't get checked");
+      end else begin 
+        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+        // clear signature to prevent contamination from previous tests
+      end
+
+      if (!begin_signature_addr)
+        $display("begin_signature addr not found in %s", ProgramLabelMapFile);
+      else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
+        CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+      end
+      if(errors > 0) totalerrors = totalerrors + 1;
+      test = test + 1; // *** this probably needs to be moved.
+      if (test == tests.size()) begin
+        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+        else $display("FAIL: %d test programs had errors", totalerrors);
+        $stop;
+      end
+    end
+  end
+
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Some memories are not reset, but should be zeros or set to some initial value for simulation
+  ////////////////////////////////////////////////////////////////////////////////
+  integer adrindex;
+
+  if (P.UNCORE_RAM_SUPPORTED) `define TB_UNCORE_RAM_SUPPORTED;
+  if (P.BPRED_SUPPORTED) `define TB_BPRED_SUPPORTED;
+  if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) `define TB_BHT;
+
+  always @(posedge clk) begin
+    if (ResetMem)  // program memory is sometimes reset
+      if (P.UNCORE_RAM_SUPPORTED) begin
+      `ifdef TB_UNCORE_RAM_SUPPORTED
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+      `endif
+      end
+    if(reset) begin  // branch predictor must always be reset
+      if (P.BPRED_SUPPORTED) begin
+      `ifdef TB_BPRED_SUPPORTED
+        // local history only
+        if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin
+        `ifdef TB_BHT
+          for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+        `endif
+        end
+        // these are both always included if there is a bpred
+        for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      `endif
+      end
+    end
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // load memories with program image
+  ////////////////////////////////////////////////////////////////////////////////
+  if (P.FPGA) `define TB_FPGA  // this is a gross hack for xcelium and verilator
+  if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
+  if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
+  if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
+  always @(posedge clk) begin
+    if (LoadMem) begin
+      if (P.FPGA) begin
+      `ifdef TB_FPGA
+        string romfilename, sdcfilename;
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        // shorten sdc timers for simulation
+        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      `endif
+      end
+      else if (P.IROM_SUPPORTED) begin
+      `ifdef TB_IROM_SUPPORTED
+        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      `endif
+      end
+      else if (P.BUS_SUPPORTED) begin
+      `ifdef TB_BUS_SUPPORTED
+        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      `endif
+      end
+      if (P.DTIM_SUPPORTED) begin
+      `ifdef TB_DTIM_SUPPORTED
+        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      `endif
+      end
+      $display("Read memfile %s", memfilename);
+    end
+  end  
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Actual hardware
+  ////////////////////////////////////////////////////////////////////////////////
+
+  // instantiate device to be tested
+  assign GPIOIN = 0;
+  assign UARTSin = 1;
+
+  if(P.EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
+    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
+      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
+  end else begin 
+    assign HREADYEXT = 1;
+    assign {HRESPEXT, HRDATAEXT} = '0;
+  end
+
+  if(P.FPGA) begin : sdcard
+    sdModel sdcard
+      (.sdClk(SDCCLK),
+       .cmd(SDCCmd), 
+       .dat(SDCDat));
+
+    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
+    assign SDCCmdIn = SDCCmd;
+    assign SDCDatIn = SDCDat;
+  end else begin
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+  end
+
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // generate clock to sequence tests
+  always begin
+    clk = 1; # 5; clk = 0; # 5;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Support logic
+  ////////////////////////////////////////////////////////////////////////////////
+
+  // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.InstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // watch for problems such as lockup, reading unitialized memory, bad configs
+  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
+  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, 
+                                      dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName);
+  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
+  loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
+  loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
+
+  // track the current function or global label
+  if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
+    FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
+			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
+
+
+  // Termination condition
+  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
+  // or sw	gp,-56(t0) for new Imperas tests
+  // or sd gp, -56(t0) 
+  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
+  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
+  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  else                  assign ecf = 0;
+  assign DCacheFlushStart = ecf & 
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+           ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
+           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
+
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
+
+  task automatic CheckSignature;
+    // This task must be declared inside this module as it needs access to parameter P.  There is
+    // no way to pass P to the task unless we convert it to a module.
+    
+    input string  pathname;
+    input string  TestName;
+    input logic   riscofTest;
+    input integer begin_signature_addr;
+    output integer errors;
+
+    localparam SIGNATURESIZE = 5000000;
+    integer        i;
+    logic [31:0]   sig32[0:SIGNATURESIZE];
+    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
+    string            signame;
+    logic [P.XLEN-1:0] testadr, testadrNoBase;
+
+    if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED2
+    
+    // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+    // clear signature to prevent contamination from previous tests
+    for(i=0; i<SIGNATURESIZE; i=i+1) begin
+      sig32[i] = 'bx;
+    end
+    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
+    else signame = {pathname, TestName, ".signature.output"};
+    // read signature, reformat in 64 bits if necessary
+    $readmemh(signame, sig32);
+    i = 0;
+    while (i < SIGNATURESIZE) begin
+      if (P.XLEN == 32) begin
+        signature[i] = sig32[i];
+        i = i+1;
+      end else begin
+        signature[i/2] = {sig32[i+1], sig32[i]};
+        i = i + 2;
+      end
+      if (i >= 4 & sig32[i-4] === 'bx) begin
+        if (i == 4) begin
+          i = SIGNATURESIZE+1; // flag empty file
+          $display("  Error: empty test file");
+        end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
+      end
+    end
+
+    // Check errors
+    errors = (i == SIGNATURESIZE+1); // error if file is empty
+    i = 0;
+    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
+    /* verilator lint_off INFINITELOOP */
+    while (signature[i] !== 'bx) begin
+      logic [P.XLEN-1:0] sig;
+      if (P.DTIM_SUPPORTED) begin
+      `ifdef TB_DTIM_SUPPORTED2
+        //sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+      `endif
+      end
+      else if (P.UNCORE_RAM_SUPPORTED) begin
+      `ifdef TB_UNCORE_RAM_SUPPORTED
+        sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+      `endif
+      end
+      if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
+        errors = errors+1;
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $stop; //***debug
+      end
+      i = i + 1;
+    end
+    /* verilator lint_on INFINITELOOP */
+    if (errors == 0) begin
+      $display("%s succeeded.  Brilliant!!!", TestName);
+    end else begin
+      $display("%s failed with %d errors. :(", TestName, errors);
+      //totalerrors = totalerrors+1;
+    end
+
+  endtask //
+  
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+
+endmodule
+
+/* verilator lint_on STMTDLY */
+/* verilator lint_on WIDTH */
+
+task automatic updateProgramAddrLabelArray;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
+  input string ProgramAddrMapFile, ProgramLabelMapFile;
+  inout  integer ProgramAddrLabelArray [string];
+  // Gets the memory location of begin_signature
+  integer ProgramLabelMapFP, ProgramAddrMapFP;
+  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
+  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
+
+
+  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    // *** RT: I'm a bit confused by the required initialization here.
+    ProgramAddrLabelArray["begin_signature"] = 0;
+    ProgramAddrLabelArray["tohost"] = 0;
+    while (!$feof(ProgramLabelMapFP)) begin
+      string label, adrstr;
+      integer returncode;
+      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
+      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
+      if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
+    end
+  end
+  $fclose(ProgramLabelMapFP);
+  $fclose(ProgramAddrMapFP);
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+endtask
+
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 9021b6448..caa60e23c 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -25,132 +25,40 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
-`define I_CACHE_ADDR_LOGGER 0
-`define D_CACHE_ADDR_LOGGER 0
+import cvw::*;
 
 module testbench;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
   parameter DEBUG=0;
   parameter TEST="none";
+  parameter PrintHPMCounters=1;
+  parameter BPRED_LOGGER=0;
+  parameter I_CACHE_ADDR_LOGGER=0;
+  parameter D_CACHE_ADDR_LOGGER=0;
  
+`include "parameter-defs.vh"
+
   logic        clk;
   logic        reset_ext, reset;
+  logic        ResetMem;
 
-  parameter SIGNATURESIZE = 5000000;
-
-  int test, i, errors, totalerrors;
-  logic [31:0] sig32[0:SIGNATURESIZE];
-  logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
-  logic [`XLEN-1:0] testadr, testadrNoBase;
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-
-  string tests[];
-  logic [3:0] dummy;
-
-  logic [`AHBW-1:0]    HRDATAEXT;
-  logic                HREADYEXT, HRESPEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0]    HWDATA;
-  logic [`XLEN/8-1:0]  HWSTRB;
-  logic                HWRITE;
-  logic [2:0]          HSIZE;
-  logic [2:0]          HBURST;
-  logic [3:0]          HPROT;
-  logic [1:0]          HTRANS;
-  logic                HMASTLOCK;
-  logic                HCLK, HRESETn;
-  logic [`XLEN-1:0]    PCW;
-
-  string  ProgramAddrMapFile, ProgramLabelMapFile;
-  integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
-
-  logic DCacheFlushDone, DCacheFlushStart;
-  logic riscofTest; 
-  logic StartSample, EndSample;
-    
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
-  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
-
-  // check assertions for a legal configuration
-  riscvassertions riscvassertions();
-
-  // pick tests based on modes supported
-  initial begin
-    $display("TEST is %s", TEST);
-    //tests = '{};
-    if (`XLEN == 64) begin // RV64
-      case (TEST)
-        "arch64i":                               tests = arch64i;
-        "arch64priv":                            tests = arch64priv;
-        "arch64c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
-                          else                   tests = {arch64c};
-        "arch64m":      if (`M_SUPPORTED)        tests = arch64m;
-        "arch64f":      if (`F_SUPPORTED)        tests = arch64f;
-        "arch64d":      if (`D_SUPPORTED)        tests = arch64d;  
-        "arch64zi":     if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
-        "imperas64i":                            tests = imperas64i;
-        "imperas64f":   if (`F_SUPPORTED)        tests = imperas64f;
-        "imperas64d":   if (`D_SUPPORTED)        tests = imperas64d;
-        "imperas64m":   if (`M_SUPPORTED)        tests = imperas64m;
-        "wally64a":     if (`A_SUPPORTED)        tests = wally64a;
-        "imperas64c":   if (`C_SUPPORTED)        tests = imperas64c;
-                        else                     tests = imperas64iNOc;
-        "custom":                                tests = custom;
-        "wally64i":                              tests = wally64i; 
-        "wally64priv":                           tests = wally64priv;
-        "wally64periph":                         tests = wally64periph;
-        "coremark":                              tests = coremark;
-        "fpga":                                  tests = fpga;
-        "ahb" :                                  tests = ahb;
-        "coverage64gc" :                         tests = coverage64gc;
-        "arch64zba":     if (`ZBA_SUPPORTED)     tests = arch64zba;
-        "arch64zbb":     if (`ZBB_SUPPORTED)     tests = arch64zbb;
-        "arch64zbc":     if (`ZBC_SUPPORTED)     tests = arch64zbc;
-        "arch64zbs":     if (`ZBS_SUPPORTED)     tests = arch64zbs;
-      endcase 
-    end else begin // RV32
-      case (TEST)
-        "arch32i":                               tests = arch32i;
-        "arch32priv":                            tests = arch32priv;
-        "arch32c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
-                          else                   tests = {arch32c};
-        "arch32m":      if (`M_SUPPORTED)        tests = arch32m;
-        "arch32f":      if (`F_SUPPORTED)        tests = arch32f;
-        "arch32d":      if (`D_SUPPORTED)        tests = arch32d;
-        "arch32zi":     if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
-        "imperas32i":                            tests = imperas32i;
-        "imperas32f":   if (`F_SUPPORTED)        tests = imperas32f;
-        "imperas32m":   if (`M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (`A_SUPPORTED)        tests = wally32a;
-        "imperas32c":   if (`C_SUPPORTED)        tests = imperas32c;
-                        else                     tests = imperas32iNOc;
-        "wally32i":                              tests = wally32i; 
-        "wally32e":                              tests = wally32e; 
-        "wally32priv":                           tests = wally32priv;
-        "wally32periph":                         tests = wally32periph;
-        "embench":                               tests = embench;
-        "coremark":                              tests = coremark;
-        "arch32zba":     if (`ZBA_SUPPORTED)     tests = arch32zba;
-        "arch32zbb":     if (`ZBB_SUPPORTED)     tests = arch32zbb;
-        "arch32zbc":     if (`ZBC_SUPPORTED)     tests = arch32zbc;
-        "arch32zbs":     if (`ZBS_SUPPORTED)     tests = arch32zbs;
-      endcase
-    end
-    if (tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
-      $stop;
-    end
-  end
-
-  string  signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
-  integer outputFilePointer;
+  // DUT signals
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                 HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                 HWRITE;
+  logic [2:0]           HSIZE;
+  logic [2:0]           HBURST;
+  logic [3:0]           HPROT;
+  logic [1:0]           HTRANS;
+  logic                 HMASTLOCK;
+  logic                 HCLK, HRESETn;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
@@ -165,28 +73,315 @@ module testbench;
 
   logic        HREADY;
   logic        HSELEXT;
+
   
-  logic        InitializingMemories;
-  integer      ResetCount, ResetThreshold;
-  logic        InReset;
-  logic        BeginSample;
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
+  integer ProgramAddrLabelArray [string];
+
+  int test, i, errors, totalerrors;
+
+  string outputfile;
+  integer outputFilePointer;
+
+  string tests[];
+  logic DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
+  logic Validate;
+  logic SelectTest;
+
+
+  // pick tests based on modes supported
+  initial begin
+    $display("TEST is %s", TEST);
+    //tests = '{};
+    if (P.XLEN == 64) begin // RV64
+      case (TEST)
+        "arch64i":                               tests = arch64i;
+        "arch64priv":                            tests = arch64priv;
+        "arch64c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
+                          else                   tests = {arch64c};
+        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
+        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
+        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
+        "arch64f_fma":      if (P.F_SUPPORTED)        tests = arch64f_fma;
+        "arch64d_fma":      if (P.D_SUPPORTED)        tests = arch64d_fma;  
+        "arch64zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "imperas64i":                            tests = imperas64i;
+        "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
+        "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
+        "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
+        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
+                        else                     tests = imperas64iNOc;
+        "custom":                                tests = custom;
+        "wally64i":                              tests = wally64i; 
+        "wally64priv":                           tests = wally64priv;
+        "wally64periph":                         tests = wally64periph;
+        "coremark":                              tests = coremark;
+        "fpga":                                  tests = fpga;
+        "ahb" :                                  tests = ahb;
+        "coverage64gc" :                         tests = coverage64gc;
+        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
+        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
+        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
+        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
+      endcase 
+    end else begin // RV32
+      case (TEST)
+        "arch32i":                               tests = arch32i;
+        "arch32priv":                            tests = arch32priv;
+        "arch32c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
+                          else                   tests = {arch32c};
+        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
+        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
+        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
+        "arch32f_fma":      if (P.F_SUPPORTED)        tests = arch32f_fma;
+        "arch32d_fma":      if (P.D_SUPPORTED)        tests = arch32d_fma;
+        "arch32zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "imperas32i":                            tests = imperas32i;
+        "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
+        "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
+        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
+                        else                     tests = imperas32iNOc;
+        "wally32i":                              tests = wally32i; 
+        "wally32e":                              tests = wally32e; 
+        "wally32priv":                           tests = wally32priv;
+        "wally32periph":                         tests = wally32periph;
+        "embench":                               tests = embench;
+        "coremark":                              tests = coremark;
+        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
+        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
+        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
+        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
+      endcase
+    end
+    if (tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end // initial begin
+
+  // Model the testbench as an fsm.
+  // Do this in parts so it easier to verify
+  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
+  // part 2: drive some of the controls
+  // part 3: drive all logic and remove old inital and always @ negedge clk block
+
+  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
+                           STATE_INIT_TEST,
+                           STATE_RESET_MEMORIES,
+                           STATE_RESET_MEMORIES2,
+                           STATE_LOAD_MEMORIES,
+                           STATE_RESET_TEST,
+                           STATE_RUN_TEST,
+                           STATE_CHECK_TEST,
+                           STATE_CHECK_TEST_WAIT,
+                           STATE_VALIDATE,
+                           STATE_INCR_TEST} statetype;
+  statetype CurrState, NextState;
+  logic        TestBenchReset;
+  logic [2:0]  ResetCount, ResetThreshold;
+  logic        LoadMem;
+  logic        ResetCntEn;
+  logic        ResetCntRst;
   
+
+  string  signame, memfilename, pathname;
+  integer begin_signature_addr;
+
+  assign ResetThreshold = 3'd5;
+
+  initial begin
+    TestBenchReset = 1;
+    # 100;
+    TestBenchReset = 0;
+  end
+
+  always_ff @(posedge clk)
+    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
+    else CurrState <= #1 NextState;  
+
+  // fsm next state logic
+  always_comb begin
+    // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
+    // and tests[0] == "2" refers to WallyRiscvArchTests 
+    riscofTest = tests[0] == "1" | tests[0] == "2"; 
+    pathname = tvpaths[tests[0].atoi()];
+
+    case(CurrState)
+      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
+      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
+      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
+      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
+      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
+      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_RUN_TEST:        if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
+      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
+      default:                                    NextState = STATE_TESTBENCH_RESET;
+    endcase
+  end // always_comb
+  // fsm output control logic 
+  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | 
+                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | 
+                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
+  // this initialization is very expensive, only do it for coremark.  
+  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
+  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
+  assign ResetCntRst = CurrState == STATE_INIT_TEST;
+  assign ResetCntEn = CurrState == STATE_RESET_TEST;
+  assign Validate = CurrState == STATE_VALIDATE;
+  assign SelectTest = CurrState == STATE_INIT_TEST;
+
+  // fsm reset counter
+  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Find the test vector files and populate the PC to function label converter
+  ////////////////////////////////////////////////////////////////////////////////
+  logic [P.XLEN-1:0] testadr;
+  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+  always @(posedge clk) begin
+    if(SelectTest) begin
+      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else            memfilename = {pathname, tests[test], ".elf.memfile"};
+      if (riscofTest) begin
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else begin
+        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+      end
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
+      // the addr of each label and fill the array. To expand, add more elements to this array 
+      // and initialize them to zero (also initilaize them to zero at the start of the next test)
+      if(!P.FPGA) begin
+        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+      end
+    end
+    
+  ////////////////////////////////////////////////////////////////////////////////
+  // Verify the test ran correctly by checking the memory against a known signature.
+  ////////////////////////////////////////////////////////////////////////////////
+    if(TestBenchReset) test = 1;
+    if (TEST == "coremark")
+      if (dut.core.EcallFaultM) begin
+        $display("Benchmark: coremark is done.");
+        $stop;
+      end
+    if(Validate) begin
+      if (TEST == "embench") begin
+        // Writes contents of begin_signature to .sim.output file
+        // this contains instret and cycles for start and end of test run, used by embench 
+        // python speed script to calculate embench speed score. 
+        // also, begin_signature contains the results of the self checking mechanism, 
+        // which will be read by the python script for error checking
+        $display("Embench Benchmark: %s is done.", tests[test]);
+        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+        else outputfile = {pathname, tests[test], ".sim.output"};
+        outputFilePointer = $fopen(outputfile, "w");
+        i = 0;
+        testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+        while ($unsigned(i) < $unsigned(5'd5)) begin
+          $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+          i = i + 1;
+        end
+        $fclose(outputFilePointer);
+        $display("Embench Benchmark: created output file: %s", outputfile);
+      end else if (TEST == "coverage64gc") begin
+        $display("Coverage tests don't get checked");
+      end else begin 
+        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+        // clear signature to prevent contamination from previous tests
+      end
+
+      if (!begin_signature_addr)
+        $display("begin_signature addr not found in %s", ProgramLabelMapFile);
+      else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
+        CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+      end
+      if(errors > 0) totalerrors = totalerrors + 1;
+      test = test + 1; // *** this probably needs to be moved.
+      if (test == tests.size()) begin
+        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+        else $display("FAIL: %d test programs had errors", totalerrors);
+        $stop;
+      end
+    end
+  end
+
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Some memories are not reset, but should be zeros or set to some initial value for simulation
+  ////////////////////////////////////////////////////////////////////////////////
+  integer adrindex;
+  always @(posedge clk) begin
+    if (ResetMem)  // program memory is sometimes reset
+      if (P.UNCORE_RAM_SUPPORTED)
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+    if(reset) begin  // branch predictor must always be reset
+      if (P.BPRED_SUPPORTED) begin
+        // local history only
+        if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR)
+          for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      end
+    end
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // load memories with program image
+  ////////////////////////////////////////////////////////////////////////////////
+  always @(posedge clk) begin
+    if (LoadMem) begin
+      if (P.FPGA) begin
+        string romfilename, sdcfilename;
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        // shorten sdc timers for simulation
+        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      end 
+      else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      if (P.DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      $display("Read memfile %s", memfilename);
+    end
+  end  
+ 
+  ////////////////////////////////////////////////////////////////////////////////
+  // Actual hardware
+  ////////////////////////////////////////////////////////////////////////////////
+
   // instantiate device to be tested
   assign GPIOIN = 0;
   assign UARTSin = 1;
 
-  if(`EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+  if(P.EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
-         .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
-         .HWSTRB);
+      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
   end else begin 
     assign HREADYEXT = 1;
-    assign HRESPEXT = 0;
-    assign HRDATAEXT = 0;
+    assign {HRESPEXT, HRDATAEXT} = '0;
   end
 
-  if(`FPGA) begin : sdcard
+  if(P.FPGA) begin : sdcard
     sdModel sdcard
       (.sdClk(SDCCLK),
        .cmd(SDCCmd), 
@@ -200,323 +395,52 @@ module testbench;
     assign SDCDat = '0;
   end
 
-  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // generate clock to sequence tests
+  always begin
+    clk = 1; # 5; clk = 0; # 5;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Support logic
+  ////////////////////////////////////////////////////////////////////////////////
 
   // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
   instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
                 dut.core.ifu.InstrRawF[31:0],
                 dut.core.ifu.InstrD, dut.core.ifu.InstrE,
                 dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
-  // initialize tests
-  localparam 	   MemStartAddr = 0;
-  localparam 	   MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
-
-  initial
-    begin
-      ResetCount = 0;
-      ResetThreshold = 2;
-      InReset = 1;
-      test = 1;
-      totalerrors = 0;
-      testadr = 0;
-      testadrNoBase = 0;
-      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
-      // and tests[0] == "2" refers to WallyRiscvArchTests 
-      riscofTest = tests[0] == "1" | tests[0] == "2"; 
-      // fill memory with defined values to reduce Xs in simulation
-      // Quick note the memory will need to be initialized.  The C library does not
-      // guarantee the  initialized reads.  For example a strcmp can read 6 byte
-      // strings, but uses a load double to read them in.  If the last 2 bytes are
-      // not initialized the compare results in an 'x' which propagates through 
-      // the design.
-      if (TEST == "coremark") 
-        for (i=MemStartAddr; i<MemEndAddr; i = i+1) 
-          dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0; 
-
-      // read test vectors into memory
-      pathname = tvpaths[tests[0].atoi()];
-      /* if (tests[0] == `IMPERASTEST)
-       pathname = tvpaths[0];
-       else pathname = tvpaths[1]; */
-      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-      else            memfilename = {pathname, tests[test], ".elf.memfile"};
-      if (`FPGA) begin
-        string romfilename, sdcfilename;
-        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
-        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
-        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
-        // force sdc timers
-        force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
-      end else begin
-        if (`IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-        else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-        if (`DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-      end
-
-      if (riscofTest) begin
-        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-      end else begin
-        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-      end
-      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
-      // the addr of each label and fill the array. To expand, add more elements to this array 
-      // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      if(!`FPGA) begin
-        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-        $display("Read memfile %s", memfilename);
-      end
-    end
-
-  // generate clock to sequence tests
-  always
-    begin
-      clk = 1; # 5; clk = 0; # 5;
-      // if ($time % 100000 == 0) $display("Time is %0t", $time);
-    end
-   
-  // check results
-  assign reset_ext = InReset;
-  
-  always @(negedge clk)
-    begin    
-      InitializingMemories = 0;
-      if(InReset == 1) begin
-        // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
-        if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
-        else begin // hit reset threshold so we remove reset.
-          InReset = 0; 
-          ResetCount = 0;
-        end
-      end else begin
-        if (TEST == "coremark")
-          if (dut.core.priv.priv.EcallFaultM) begin
-            $display("Benchmark: coremark is done.");
-            $stop;
-          end
-        // Termination condition (i.e. we finished running current test) 
-        if (DCacheFlushDone) begin
-          integer begin_signature_addr;
-          InReset = 1;
-          begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
-          if (!begin_signature_addr)
-            $display("begin_signature addr not found in %s", ProgramLabelMapFile);
-          testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
-          testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
-          #600; // give time for instructions in pipeline to finish
-          if (TEST == "embench") begin
-            // Writes contents of begin_signature to .sim.output file
-            // this contains instret and cycles for start and end of test run, used by embench 
-            // python speed script to calculate embench speed score. 
-            // also, begin_signature contains the results of the self checking mechanism, 
-            // which will be read by the python script for error checking
-            $display("Embench Benchmark: %s is done.", tests[test]);
-            if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
-            else outputfile = {pathname, tests[test], ".sim.output"};
-            outputFilePointer = $fopen(outputfile);
-            i = 0;
-            while ($unsigned(i) < $unsigned(5'd5)) begin
-              $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
-              i = i + 1;
-            end
-            $fclose(outputFilePointer);
-            $display("Embench Benchmark: created output file: %s", outputfile);
-          end else if (TEST == "coverage64gc") begin
-            $display("Coverage tests don't get checked");
-          end else begin 
-            // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
-            // clear signature to prevent contamination from previous tests
-            for(i=0; i<SIGNATURESIZE; i=i+1) begin
-              sig32[i] = 'bx;
-            end
-            if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
-            else signame = {pathname, tests[test], ".signature.output"};
-            // read signature, reformat in 64 bits if necessary
-            $readmemh(signame, sig32);
-            i = 0;
-            while (i < SIGNATURESIZE) begin
-              if (`XLEN == 32) begin
-                signature[i] = sig32[i];
-                i = i+1;
-              end else begin
-                signature[i/2] = {sig32[i+1], sig32[i]};
-                i = i + 2;
-              end
-              if (i >= 4 & sig32[i-4] === 'bx) begin
-                if (i == 4) begin
-                  i = SIGNATURESIZE+1; // flag empty file
-                  $display("  Error: empty test file");
-                end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
-              end
-            end
-
-            // Check errors
-            errors = (i == SIGNATURESIZE+1); // error if file is empty
-            i = 0;
-            /* verilator lint_off INFINITELOOP */
-            while (signature[i] !== 'bx) begin
-              logic [`XLEN-1:0] sig;
-              if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
-              else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-              //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
-              if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
-                errors = errors+1;
-                $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-						    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
-                $stop; //***debug
-              end
-              i = i + 1;
-            end
-            /* verilator lint_on INFINITELOOP */
-            if (errors == 0) begin
-              $display("%s succeeded.  Brilliant!!!", tests[test]);
-            end else begin
-              $display("%s failed with %d errors. :(", tests[test], errors);
-              totalerrors = totalerrors+1;
-            end
-          end
-          // move onto the next test, check to see if we're done
-          test = test + 1;
-          if (test == tests.size()) begin
-          if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
-          else $display("FAIL: %d test programs had errors", totalerrors);
-          $stop;
-          end else begin
-            InitializingMemories = 1;
-            // If there are still additional tests to run, read in information for the next test
-            //pathname = tvpaths[tests[0]];
-            if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-            else memfilename = {pathname, tests[test], ".elf.memfile"};
-            //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-            if (`IROM_SUPPORTED)               $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-            else if (`UNCORE_RAM_SUPPORTED)    $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-            if (`DTIM_SUPPORTED)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-
-            if (riscofTest) begin
-              ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-              ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-            end else begin
-              ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-              ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-            end
-            ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
-            if(!`FPGA) begin
-              updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-              $display("Read memfile %s", memfilename);
-            end
-          end
-        end // if (DCacheFlushDone)
-      end
-    end // always @ (negedge clk)
-
-
-  if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
-    integer           HPMCindex;
-    logic             StartSampleFirst;
-    logic             StartSampleDelayed, BeginDelayed;
-    logic             EndSampleFirst, EndSampleDelayed;
-    logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
-
-    string  HPMCnames[] = '{"Mcycle",
-                            "------",
-                            "InstRet",
-                            "Br Count",
-                            "Jump Not Return",
-                            "Return",
-                            "BP Wrong",
-                            "BP Dir Wrong",
-                            "BP Target Wrong",
-                            "RAS Wrong",
-                            "Instr Class Wrong",
-                            "Load Stall",
-                            "Store Stall",
-                            "D Cache Access",
-                            "D Cache Miss",
-                            "D Cache Cycles",
-                            "I Cache Access",
-                            "I Cache Miss",
-                            "I Cache Cycles",
-                            "CSR Write",
-                            "FenceI",
-                            "SFenceVMA",
-                            "Interrupt",
-                            "Exception",
-                            "Divide Cycles"
-                          };
-
-    if(TEST == "embench") begin
-      // embench runs warmup then runs start_trigger
-      // embench end with stop_trigger.
-      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else if(TEST == "coremark") begin
-      // embench runs warmup then runs start_trigger
-	    // embench end with stop_trigger.
-      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else begin
-      // default start condiction is reset
-      // default end condiction is end of test (DCacheFlushDone)
-      assign StartSampleFirst = InReset;
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
-
-      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
-      assign BeginSample = StartSampleFirst & ~BeginDelayed;
-
-    end
-    always @(negedge clk) begin
-      if(StartSample) begin
-        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
-          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
-        end
-      end
-      if(EndSample) begin
-        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
-          // unlikely to have more than 10M in any counter.
-          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
-        end
-      end
-    end
-  end
-  
-
+  // watch for problems such as lockup, reading unitialized memory, bad configs
+  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
+  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, 
+                                      dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName);
+  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
+  loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
+  loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
 
   // track the current function or global label
-  if (DEBUG == 1 | (`PrintHPMCounters & `ZICOUNTERS_SUPPORTED)) begin : FunctionName
-    FunctionName FunctionName(.reset(reset),
-			      .clk(clk),
-			      .ProgramAddrMapFile(ProgramAddrMapFile),
-			      .ProgramLabelMapFile(ProgramLabelMapFile));
+  if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
+    FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
+			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
   end
 
+
   // Termination condition
   // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
   // or sw	gp,-56(t0) for new Imperas tests
   // or sd gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
   assign DCacheFlushStart = ecf & 
 			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
@@ -526,283 +450,103 @@ module testbench;
            ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
 
-  DCacheFlushFSM DCacheFlushFSM(.clk(clk),
-    			.reset(reset),
-	    		.start(DCacheFlushStart),
-		    	.done(DCacheFlushDone));
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
 
-
-  // initialize the branch predictor
-  if (`BPRED_SUPPORTED) begin
-    integer adrindex;
-
-    always @(*) begin
-      if(reset) begin
-        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-          force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
-        end
-        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-          force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
-        end
-          #1;
-        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-          release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
-        end 
-        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-          release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
-        end
-      end
-    end
-  end
-
-
-  if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enable;
-    logic  InvalDelayed, InvalEdge;
+  task automatic CheckSignature;
+    // This task must be declared inside this module as it needs access to parameter P.  There is
+    // no way to pass P to the task unless we convert it to a module.
     
-    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
-                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
-                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
-                    ~reset;
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
+    input string  pathname;
+    input string  TestName;
+    input logic   riscofTest;
+    input integer begin_signature_addr;
+    output integer errors;
 
-    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
-    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
-
-    initial begin
-      LogFile = $psprintf("ICache.log");
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
-    end
-    string AccessTypeString, HitMissString;
-    assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
-                           dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
-    always @(posedge clk) begin
-    if(resetEdge) $fwrite(file, "TRAIN\n");
-    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-    if(Enable) begin  // only log i cache reads
-      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
-    end
-    if(InvalEdge) $fwrite(file, "0 I X\n");
-    if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-
-  if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enabled;
-    string AccessTypeString, HitMissString;
-
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
-    assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
-                           (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
-                           dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
-    assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
-                              dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
-                              dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
-                              dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
-                              "NULL";
+    localparam SIGNATURESIZE = 5000000;
+    integer        i;
+    logic [31:0]   sig32[0:SIGNATURESIZE];
+    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
+    string            signame;
+    logic [P.XLEN-1:0] testadr, testadrNoBase;
     
-    assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
-                     ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
-                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
-                     (AccessTypeString != "NULL");
-
-    initial begin
-      LogFile = $psprintf("DCache.log");
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
+    // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+    // clear signature to prevent contamination from previous tests
+    for(i=0; i<SIGNATURESIZE; i=i+1) begin
+      sig32[i] = 'bx;
     end
-    always @(posedge clk) begin
-      if(resetEdge) $fwrite(file, "TRAIN\n");
-      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-      if(Enabled) begin
-        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
+    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
+    else signame = {pathname, TestName, ".signature.output"};
+    // read signature, reformat in 64 bits if necessary
+    $readmemh(signame, sig32);
+    i = 0;
+    while (i < SIGNATURESIZE) begin
+      if (P.XLEN == 32) begin
+        signature[i] = sig32[i];
+        i = i+1;
+      end else begin
+        signature[i/2] = {sig32[i+1], sig32[i]};
+        i = i + 2;
       end
-      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
-      if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-  if (`BPRED_SUPPORTED) begin : BranchLogger
-    if (`BPRED_LOGGER) begin
-      string direction;
-      int    file;
-      logic  PCSrcM;
-      string LogFile;
-      logic  resetD, resetEdge;
-      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
-      flop #(1) ResetDReg(clk, reset, resetD);
-      assign resetEdge = ~reset & resetD;
-      initial begin
-        LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
-        file = $fopen(LogFile, "w");
-      end
-      always @(posedge clk) begin
-        if(resetEdge) $fwrite(file, "TRAIN\n");
-        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
-        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-          direction = PCSrcM ? "t" : "n";
-          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
-        end
-        if(EndSample) $fwrite(file, "END %s\n", memfilename);
+      if (i >= 4 & sig32[i-4] === 'bx) begin
+        if (i == 4) begin
+          i = SIGNATURESIZE+1; // flag empty file
+          $display("  Error: empty test file");
+        end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
       end
     end
-  end
 
-  // check for hang up.
-  logic [`XLEN-1:0] OldPCW;
-  integer           WatchDogTimerCount;
-  localparam        WatchDogTimerThreshold = 1000000;
-  logic             WatchDogTimeOut;
-  always_ff @(posedge clk) begin
-    OldPCW <= PCW;
-    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
-    else WatchDogTimerCount = '0;
-  end
+    // Check errors
+    errors = (i == SIGNATURESIZE+1); // error if file is empty
+    i = 0;
+    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
+    /* verilator lint_off INFINITELOOP */
+    while (signature[i] !== 'bx) begin
+      logic [P.XLEN-1:0] sig;
+      if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+      else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+      if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
+        errors = errors+1;
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $stop; //***debug
+      end
+      i = i + 1;
+    end
+    /* verilator lint_on INFINITELOOP */
+    if (errors == 0) begin
+      $display("%s succeeded.  Brilliant!!!", TestName);
+    end else begin
+      $display("%s failed with %d errors. :(", TestName, errors);
+      //totalerrors = totalerrors+1;
+    end
 
-  always_comb begin
-    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
-    if(WatchDogTimeOut) begin
-      $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
-      $stop;
-	  end
-  end
+  endtask //
   
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+
 endmodule
 
 /* verilator lint_on STMTDLY */
 /* verilator lint_on WIDTH */
 
-module DCacheFlushFSM
-  (input logic clk,
-   input logic reset,
-   input logic start,
-   output logic done);
-
-  genvar adr;
-
-  logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
-  
-  if(`DCACHE_SUPPORTED) begin
-    localparam numlines       = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
-    localparam numways        = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
-    localparam linebytelen    = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
-    localparam linelen        = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
-    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
-    localparam numwords       = sramlen/`XLEN;
-    localparam lognumlines    = $clog2(numlines);
-    localparam loglinebytelen = $clog2(linebytelen);
-    localparam lognumways     = $clog2(numways);
-    localparam tagstart       = lognumlines + loglinebytelen;
-
-
-
-    genvar               index, way, cacheWord;
-    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [sramlen-1:0]  cacheline;
-    logic [`XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [`PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    for(index = 0; index < numlines; index++) begin
-      for(way = 0; way < numways; way++) begin
-        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
-          copyShadow #(.tagstart(tagstart),
-          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
-          copyShadow(.clk,
-          .start,
-          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
-          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
-          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
-                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
-          .index(index),
-          .cacheWord(cacheWord),
-          .CacheData(CacheData[way][index][cacheWord]),
-          .CacheAdr(CacheAdr[way][index][cacheWord]),
-          .CacheTag(CacheTag[way][index][cacheWord]),
-          .CacheValid(CacheValid[way][index][cacheWord]),
-          .CacheDirty(CacheDirty[way][index][cacheWord]));
-        end
-      end
-    end
-
-    integer i, j, k, l;
-
-    always @(posedge clk) begin
-      if (start) begin #1
-        #1
-        for(i = 0; i < numlines; i++) begin
-          for(j = 0; j < numways; j++) begin
-            for(l = 0; l < cachesramwords; l++) begin
-              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
-                for(k = 0; k < numwords; k++) begin
-                  //cacheline = CacheData[j][i][0];
-                  // does not work with modelsim
-                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
-                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
-                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
-                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
-                end
-              end
-            end
-          end
-        end
-      end
-    end  
-  end
-  flop #(1) doneReg(.clk, .d(start), .q(done));
-endmodule
-
-module copyShadow
-  #(parameter tagstart, loglinebytelen, sramlen)
-  (input  logic                       clk,
-   input  logic                       start,
-   input  logic [`PA_BITS-1:tagstart] tag,
-   input  logic                       valid, dirty,
-   input  logic [sramlen-1:0]         data,
-   input  logic [32-1:0]              index,
-   input  logic [32-1:0]              cacheWord,
-   output logic [sramlen-1:0]         CacheData,
-   output logic [`PA_BITS-1:0]        CacheAdr,
-   output logic [`XLEN-1:0]           CacheTag,
-   output logic                       CacheValid,
-   output logic                       CacheDirty);
-  
-
-  always_ff @(posedge clk) begin
-    if(start) begin
-      CacheTag = tag;
-      CacheValid = valid;
-      CacheDirty = dirty;
-      CacheData = data;
-      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
-    end
-  end
-  
-endmodule
-
 task automatic updateProgramAddrLabelArray;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
   input string ProgramAddrMapFile, ProgramLabelMapFile;
   inout  integer ProgramAddrLabelArray [string];
   // Gets the memory location of begin_signature
   integer ProgramLabelMapFP, ProgramAddrMapFP;
   ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
   ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
-  
+
+
   if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    // *** RT: I'm a bit confused by the required initialization here.
+    ProgramAddrLabelArray["begin_signature"] = 0;
+    ProgramAddrLabelArray["tohost"] = 0;
     while (!$feof(ProgramLabelMapFP)) begin
       string label, adrstr;
       integer returncode;
@@ -813,5 +557,7 @@ task automatic updateProgramAddrLabelArray;
   end
   $fclose(ProgramLabelMapFP);
   $fclose(ProgramAddrMapFP);
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
 endtask
 
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index b6d22feaf..0ca45420a 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -25,39 +25,44 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
+
 
 // This is set from the command line script
 // `define USE_IMPERAS_DV
 
 `ifdef USE_IMPERAS_DV
-  `include "rvvi/imperasDV.svh"
+  `include "idv/idv.svh"
 `endif
 
+import cvw::*;
+
 module testbench;
   parameter DEBUG=0;
 
 `ifdef USE_IMPERAS_DV
-  import rvviPkg::*;
+  import idvPkg::*;
   import rvviApiPkg::*;
   import idvApiPkg::*;
 `endif
 
+  `include "parameter-defs.vh"
+
   logic        clk;
   logic        reset_ext, reset;
 
 
-  logic [`XLEN-1:0] testadr, testadrNoBase;
+  logic [P.XLEN-1:0] testadr, testadrNoBase;
   string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
   logic [31:0] InstrW;
 
   logic [3:0]  dummy;
 
-  logic [`AHBW-1:0] HRDATAEXT;
+  logic [P.AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0] HWDATA;
-  logic [`XLEN/8-1:0] HWSTRB;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0] HWDATA;
+  logic [P.XLEN/8-1:0] HWSTRB;
   logic             HWRITE;
   logic [2:0]       HSIZE;
   logic [2:0]       HBURST;
@@ -65,7 +70,7 @@ module testbench;
   logic [1:0]       HTRANS;
   logic             HMASTLOCK;
   logic             HCLK, HRESETn;
-  logic [`XLEN-1:0] PCW;
+  logic [P.XLEN-1:0] PCW;
 
   string ProgramAddrMapFile, ProgramLabelMapFile;
   integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
@@ -108,7 +113,7 @@ module testbench;
           $error("Must specify test directory using plusarg testDir");
       end
 
-      if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
 	  else $error("Imperas test bench requires BUS.");
 
       ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"};
@@ -123,8 +128,8 @@ module testbench;
 
 `ifdef USE_IMPERAS_DV
 
-    rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
-    wallyTracer wallyTracer(rvvi);
+    rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
+    wallyTracer #(P) wallyTracer(rvvi);
 
     trace2log idv_trace2log(rvvi);
     trace2cov idv_trace2cov(rvvi);
@@ -140,7 +145,7 @@ module testbench;
 
     initial begin 
       
-      MAX_ERRS = 3;
+      IDV_MAX_ERRS = 3;
 
       // Initialize REF (do this before initializing the DUT)
       if (!rvviVersionCheck(RVVI_API_VERSION)) begin
@@ -171,23 +176,23 @@ module testbench;
       // Privileges for PMA are set in the imperas.ic
       // volatile (IO) regions are defined here
       // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
-      if (`CLINT_SUPPORTED) begin
-          void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
+      if (P.CLINT_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
       end
-      if (`GPIO_SUPPORTED) begin
-          void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
+      if (P.GPIO_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
       end
-      if (`UART_SUPPORTED) begin
-          void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
+      if (P.UART_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
       end
-      if (`PLIC_SUPPORTED) begin
-          void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));
+      if (P.PLIC_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
       end
-      if (`SDC_SUPPORTED) begin
-          void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
+      if (P.SDC_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
       end
 
-      if(`XLEN==32) begin
+      if(P.XLEN==32) begin
           void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
           void'(rvviRefCsrSetVolatile(0, 32'hB80));   // MCYCLEH
           void'(rvviRefCsrSetVolatile(0, 32'hC82));   // INSTRETH
@@ -211,19 +216,19 @@ module testbench;
 
 `endif
 
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr #(P.XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
-  riscvassertions riscvassertions();
+  riscvassertions #(P) riscvassertions();
 
 
   // instantiate device to be tested
   assign GPIOIN = 0;
   assign UARTSin = 1;
 
-  if(`EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+  if(P.EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
          .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
          .HWSTRB);
@@ -233,7 +238,7 @@ module testbench;
     assign HRDATAEXT = 0;
   end
 
-  if(`FPGA) begin : sdcard
+  if(P.FPGA) begin : sdcard
     sdModel sdcard
       (.sdClk(SDCCLK),
        .cmd(SDCCmd), 
@@ -247,7 +252,7 @@ module testbench;
     assign SDCDat = '0;
   end
 
-  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
@@ -287,7 +292,7 @@ module testbench;
 
   // track the current function or global label
   if (DEBUG == 1) begin : FunctionName
-    FunctionName FunctionName(.reset(reset),
+    FunctionName #(P) FunctionName(.reset(reset),
 			      .clk(clk),
 			      .ProgramAddrMapFile(ProgramAddrMapFile),
 			      .ProgramLabelMapFile(ProgramLabelMapFile));
@@ -299,7 +304,7 @@ module testbench;
   // or sd gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
   assign DCacheFlushStart = ecf & 
 			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
@@ -309,13 +314,13 @@ module testbench;
            ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
 
-  DCacheFlushFSM DCacheFlushFSM(.clk(clk),
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
     			.reset(reset),
 	    		.start(DCacheFlushStart),
 		    	.done(DCacheFlushDone));
 
   // initialize the branch predictor
-  if (`BPRED_SUPPORTED == 1)
+  if (P.BPRED_SUPPORTED == 1)
     begin
       genvar adrindex;
       
@@ -331,24 +336,7 @@ module testbench;
       end
     end
 
-  // check for hange up.
-  logic [`XLEN-1:0] OldPCW;
-  integer 			WatchDogTimerCount;
-  localparam WatchDogTimerThreshold = 1000000;
-  logic 			WatchDogTimeOut;
-  always_ff @(posedge clk) begin
-	OldPCW <= PCW;
-	if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
-	else WatchDogTimerCount = '0;
-  end
-
-  always_comb begin
-	WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
-	if(WatchDogTimeOut) begin
-	  $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
-	  $stop;
-	end
-  end
+  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
 
 endmodule
 
@@ -356,120 +344,6 @@ endmodule
 /* verilator lint_on STMTDLY */
 /* verilator lint_on WIDTH */
 
-module DCacheFlushFSM
-  (input logic clk,
-   input logic reset,
-   input logic start,
-   output logic done);
-
-  genvar adr;
-
-  logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
-  
-	if(`DCACHE_SUPPORTED) begin
-	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
-	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
-	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
-	  localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
-	  localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-	  localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
-      
-//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
-	  localparam integer numwords = sramlen/`XLEN;
-      localparam integer lognumlines = $clog2(numlines);
-	  localparam integer loglinebytelen = $clog2(linebytelen);
-	  localparam integer lognumways = $clog2(numways);
-	  localparam integer tagstart = lognumlines + loglinebytelen;
-
-
-
-	  genvar 			 index, way, cacheWord;
-	  logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-      logic [sramlen-1:0] cacheline;
-	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    for(index = 0; index < numlines; index++) begin
-		  for(way = 0; way < numways; way++) begin
-		    for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
-			    copyShadow #(.tagstart(tagstart),
-					.loglinebytelen(loglinebytelen), .sramlen(sramlen))
-			    copyShadow(.clk,
-          .start,
-          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
-          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
-          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
-                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
-          .index(index),
-          .cacheWord(cacheWord),
-          .CacheData(CacheData[way][index][cacheWord]),
-          .CacheAdr(CacheAdr[way][index][cacheWord]),
-          .CacheTag(CacheTag[way][index][cacheWord]),
-          .CacheValid(CacheValid[way][index][cacheWord]),
-          .CacheDirty(CacheDirty[way][index][cacheWord]));
-        end
-      end
-    end
-
-    integer i, j, k, l;
-
-    always @(posedge clk) begin
-      if (start) begin #1
-        #1
-        for(i = 0; i < numlines; i++) begin
-          for(j = 0; j < numways; j++) begin
-            for(l = 0; l < cachesramwords; l++) begin
-              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
-                for(k = 0; k < numwords; k++) begin
-                  //cacheline = CacheData[j][i][0];
-                  // does not work with modelsim
-                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
-                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
-                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
-                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
-                end
-              end
-            end
-          end
-        end
-      end
-    end  
-  end
-  flop #(1) doneReg(.clk, .d(start), .q(done));
-endmodule
-
-module copyShadow
-  #(parameter tagstart, loglinebytelen, sramlen)
-  (input logic clk,
-   input logic 			     start,
-   input logic [`PA_BITS-1:tagstart] tag,
-   input logic 			     valid, dirty,
-   input logic [sramlen-1:0] 	     data,
-   input logic [32-1:0] 	     index,
-   input logic [32-1:0] 	     cacheWord,
-   output logic [sramlen-1:0] 	     CacheData,
-   output logic [`PA_BITS-1:0] 	     CacheAdr,
-   output logic [`XLEN-1:0] 	     CacheTag,
-   output logic 		     CacheValid,
-   output logic 		     CacheDirty);
-  
-
-  always_ff @(posedge clk) begin
-    if(start) begin
-      CacheTag = tag;
-      CacheValid = valid;
-      CacheDirty = dirty;
-      CacheData = data;
-      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
-    end
-  end
-  
-  
-endmodule
 
 task automatic updateProgramAddrLabelArray;
   input string ProgramAddrMapFile, ProgramLabelMapFile;
diff --git a/testbench/tests.vh b/testbench/tests.vh
index a450b057d..116d39424 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -52,18 +52,20 @@ string tvpaths[] = '{
     "fpu",
     "lsu",
     "vm64check",
-    "pmp",
+    "tlbASID",
+    "tlbGLB",
+    "tlbMP",
+    "tlbGP",
+    "tlbTP",
+    "ifuCamlineWrite",
     "dcache1",
     "dcache2",
+    "pmp",
     "pmpcfg",
     "pmpcfg1",
     "pmpcfg2",
-    "tlbKP",
-    "tlbMP",
-    "tlbM3",
-    "tlbASID",
-    "tlbGLB",
-    "ifuCamlineWrite"
+    "pmppriority",
+    "pmpadrdecs"
   };
 
   string coremark[] = '{
@@ -73,26 +75,26 @@ string tvpaths[] = '{
 
   string embench[] = '{
     `EMBENCH,
-    "bd_speedopt_speed/src/nsichneu/nsichneu",
-    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/aha-mont64/aha-mont64",
     "bd_speedopt_speed/src/crc32/crc32",
+    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/edn/edn",
     "bd_speedopt_speed/src/huffbench/huffbench",
     "bd_speedopt_speed/src/matmult-int/matmult-int",
-    // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
+     "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
     "bd_speedopt_speed/src/minver/minver",
     "bd_speedopt_speed/src/nettle-aes/nettle-aes",
     "bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
+    "bd_speedopt_speed/src/nsichneu/nsichneu",
     "bd_speedopt_speed/src/nbody/nbody",
     "bd_speedopt_speed/src/picojpeg/picojpeg",
-    // "bd_speedopt_speed/src/primecount/primecount",
+     "bd_speedopt_speed/src/primecount/primecount",
     "bd_speedopt_speed/src/qrduino/qrduino",
     "bd_speedopt_speed/src/sglib-combined/sglib-combined",
     "bd_speedopt_speed/src/slre/slre",
     "bd_speedopt_speed/src/st/st",
     "bd_speedopt_speed/src/statemate/statemate",
-    // "bd_speedopt_speed/src/tarfind/tarfind",
+     "bd_speedopt_speed/src/tarfind/tarfind",
     "bd_speedopt_speed/src/ud/ud",
     "bd_speedopt_speed/src/wikisort/wikisort",
     "bd_sizeopt_speed/src/aha-mont64/aha-mont64",
@@ -101,20 +103,20 @@ string tvpaths[] = '{
     "bd_sizeopt_speed/src/edn/edn",
     "bd_sizeopt_speed/src/huffbench/huffbench",
     "bd_sizeopt_speed/src/matmult-int/matmult-int",
-    // "bd_sizeopt_speed/src/md5sum/md5sum",
+     "bd_sizeopt_speed/src/md5sum/md5sum",
     "bd_sizeopt_speed/src/minver/minver",
     "bd_sizeopt_speed/src/nbody/nbody",
     "bd_sizeopt_speed/src/nettle-aes/nettle-aes",
     "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256",
     "bd_sizeopt_speed/src/nsichneu/nsichneu",
     "bd_sizeopt_speed/src/picojpeg/picojpeg",
-    // "bd_sizeopt_speed/src/primecount/primecount",
+     "bd_sizeopt_speed/src/primecount/primecount",
     "bd_sizeopt_speed/src/qrduino/qrduino",
     "bd_sizeopt_speed/src/sglib-combined/sglib-combined",
     "bd_sizeopt_speed/src/slre/slre",
     "bd_sizeopt_speed/src/st/st",
     "bd_sizeopt_speed/src/statemate/statemate",
-    // "bd_sizeopt_speed/src/tarfind/tarfind",
+     "bd_sizeopt_speed/src/tarfind/tarfind",
     "bd_sizeopt_speed/src/ud/ud",
     "bd_sizeopt_speed/src/wikisort/wikisort"
   };
@@ -1064,6 +1066,14 @@ string imperas32f[] = '{
     "rv64i_m/I/src/xori-01.S"
   };
 
+  string arch64f_fma[] = '{
+    `RISCVARCHTEST,
+    //"rv64i_m/F/src/fmadd_b15-01.S",
+    "rv64i_m/F/src/fmsub_b15-01.S"
+    // "rv64i_m/F/src/fnmadd_b15-01.S",
+    // "rv64i_m/F/src/fnmsub_b15-01.S"
+  };
+
   string arch64f[] = '{
     `RISCVARCHTEST,
     "rv64i_m/F/src/fdiv_b1-01.S",
@@ -1086,8 +1096,6 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fsqrt_b7-01.S",
     "rv64i_m/F/src/fsqrt_b8-01.S",
     "rv64i_m/F/src/fsqrt_b9-01.S",
-
-
     "rv64i_m/F/src/fadd_b10-01.S",
     "rv64i_m/F/src/fadd_b1-01.S",
     "rv64i_m/F/src/fadd_b11-01.S",
@@ -1138,7 +1146,6 @@ string imperas32f[] = '{
     "rv64i_m/F/src/flw-align-01.S",
     "rv64i_m/F/src/fmadd_b1-01.S",
     "rv64i_m/F/src/fmadd_b14-01.S",
-    //"rv64i_m/F/src/fmadd_b15-01.S",
     "rv64i_m/F/src/fmadd_b16-01.S",
     "rv64i_m/F/src/fmadd_b17-01.S",
     "rv64i_m/F/src/fmadd_b18-01.S",
@@ -1155,7 +1162,6 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fmin_b19-01.S",
     "rv64i_m/F/src/fmsub_b1-01.S",
     "rv64i_m/F/src/fmsub_b14-01.S",
-    "rv64i_m/F/src/fmsub_b15-01.S",
     "rv64i_m/F/src/fmsub_b16-01.S",
     "rv64i_m/F/src/fmsub_b17-01.S",
     "rv64i_m/F/src/fmsub_b18-01.S",
@@ -1186,7 +1192,6 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fmv.x.w_b29-01.S",
     "rv64i_m/F/src/fnmadd_b1-01.S",
     "rv64i_m/F/src/fnmadd_b14-01.S",
-    // "rv64i_m/F/src/fnmadd_b15-01.S",
     "rv64i_m/F/src/fnmadd_b16-01.S",
     "rv64i_m/F/src/fnmadd_b17-01.S",
     "rv64i_m/F/src/fnmadd_b18-01.S",
@@ -1199,7 +1204,6 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fnmadd_b8-01.S",
     "rv64i_m/F/src/fnmsub_b1-01.S",
     "rv64i_m/F/src/fnmsub_b14-01.S",
-    // "rv64i_m/F/src/fnmsub_b15-01.S",
     "rv64i_m/F/src/fnmsub_b16-01.S",
     "rv64i_m/F/src/fnmsub_b17-01.S",
     "rv64i_m/F/src/fnmsub_b18-01.S",
@@ -1236,6 +1240,13 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fsw-align-01.S"
     };
 
+  string arch64d_fma[] = '{
+    `RISCVARCHTEST,
+    //"rv64i_m/D/src/fmadd.d_b15-01.S",
+    //"rv64i_m/D/src/fmsub.d_b15-01.S",
+     "rv64i_m/D/src/fnmadd.d_b15-01.S"
+    // "rv64i_m/D/src/fnmsub.d_b15-01.S"
+  };
 
   string arch64d[] = '{
     `RISCVARCHTEST,
@@ -1260,7 +1271,6 @@ string imperas32f[] = '{
     "rv64i_m/D/src/fsqrt.d_b7-01.S",
     "rv64i_m/D/src/fsqrt.d_b8-01.S",
     "rv64i_m/D/src/fsqrt.d_b9-01.S",
-
     "rv64i_m/D/src/fadd.d_b10-01.S",
     "rv64i_m/D/src/fadd.d_b1-01.S",
     "rv64i_m/D/src/fadd.d_b11-01.S",
@@ -1456,7 +1466,7 @@ string arch64zbb[] = '{
     "rv64i_m/B/src/andn-01.S",
     "rv64i_m/B/src/orn-01.S",
     "rv64i_m/B/src/xnor-01.S",
-    "rv64i_m/B/src/zext.h-01.S",
+    "rv64i_m/B/src/zext.h_64-01.S",
     "rv64i_m/B/src/sext.b-01.S",
     "rv64i_m/B/src/sext.h-01.S",
     "rv64i_m/B/src/clz-01.S",
@@ -1524,6 +1534,14 @@ string arch64zbs[] = '{
     "rv32i_m/M/src/mulhu-01.S"
    };
 
+  string arch32f_fma[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/F/src/fmadd_b15-01.S"
+    //"rv32i_m/F/src/fmsub_b15-01.S",
+    // "rv32i_m/F/src/fnmadd_b15-01.S",
+    // "rv32i_m/F/src/fnmsub_b15-01.S"
+  };
+
   string arch32f[] = '{
     `RISCVARCHTEST,
     "rv32i_m/F/src/fdiv_b20-01.S",
@@ -1577,7 +1595,6 @@ string arch64zbs[] = '{
     "rv32i_m/F/src/flw-align-01.S",
     "rv32i_m/F/src/fmadd_b1-01.S",
     "rv32i_m/F/src/fmadd_b14-01.S",
-    "rv32i_m/F/src/fmadd_b15-01.S",
     "rv32i_m/F/src/fmadd_b16-01.S",
     "rv32i_m/F/src/fmadd_b17-01.S",
     "rv32i_m/F/src/fmadd_b18-01.S",
@@ -1594,7 +1611,6 @@ string arch64zbs[] = '{
     "rv32i_m/F/src/fmin_b19-01.S",
     "rv32i_m/F/src/fmsub_b1-01.S",
     "rv32i_m/F/src/fmsub_b14-01.S",
-    //"rv32i_m/F/src/fmsub_b15-01.S",
     "rv32i_m/F/src/fmsub_b16-01.S",
     "rv32i_m/F/src/fmsub_b17-01.S",
     "rv32i_m/F/src/fmsub_b18-01.S",
@@ -1625,7 +1641,6 @@ string arch64zbs[] = '{
     "rv32i_m/F/src/fmv.x.w_b29-01.S",
     "rv32i_m/F/src/fnmadd_b1-01.S",
     "rv32i_m/F/src/fnmadd_b14-01.S",
-    // "rv32i_m/F/src/fnmadd_b15-01.S",
     "rv32i_m/F/src/fnmadd_b16-01.S",
     "rv32i_m/F/src/fnmadd_b17-01.S",
     "rv32i_m/F/src/fnmadd_b18-01.S",
@@ -1638,7 +1653,6 @@ string arch64zbs[] = '{
     "rv32i_m/F/src/fnmadd_b8-01.S",
     "rv32i_m/F/src/fnmsub_b1-01.S",
     "rv32i_m/F/src/fnmsub_b14-01.S",
-    // "rv32i_m/F/src/fnmsub_b15-01.S",
     "rv32i_m/F/src/fnmsub_b16-01.S",
     "rv32i_m/F/src/fnmsub_b17-01.S",
     "rv32i_m/F/src/fnmsub_b18-01.S",
@@ -1675,6 +1689,14 @@ string arch64zbs[] = '{
     "rv32i_m/F/src/fsw-align-01.S"
     };
 
+  string arch32d_fma[] = '{
+    `RISCVARCHTEST,
+    //"rv32i_m/D/src/fmadd.d_b15-01.S",
+    //"rv32i_m/D/src/fmsub.d_b15-01.S",
+    // "rv32i_m/D/src/fnmadd.d_b15-01.S",
+    "rv32i_m/D/src/fnmsub.d_b15-01.S"
+  };
+
   string arch32d[] = '{
     `RISCVARCHTEST,
     "rv32i_m/D/src/fadd.d_b10-01.S",
@@ -2009,8 +2031,8 @@ string arch64zbs[] = '{
     "rv32i_m/privilege/src/WALLY-mie-01.S",
     "rv32i_m/privilege/src/WALLY-minfo-01.S",
     "rv32i_m/privilege/src/WALLY-misa-01.S",
-//    "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
-    "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S",
+    // "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",    // run this if SVADU_SUPPORTED = 0
+    "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S", // run this if SVADU_SUPPORTED = 1
     "rv32i_m/privilege/src/WALLY-mtvec-01.S",
     "rv32i_m/privilege/src/WALLY-pma-01.S",
     "rv32i_m/privilege/src/WALLY-pmp-01.S",
@@ -2055,8 +2077,8 @@ string arch64zbs[] = '{
 
  string custom[] = '{
     `CUSTOM,
-    "debug",
     "simple",
+    "debug",
     "cacheTest"
  };
   string testsBP64[] = '{
diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv
new file mode 100644
index 000000000..1a13392d1
--- /dev/null
+++ b/testbench/wallywrapper.sv
@@ -0,0 +1,82 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+
+import cvw::*;
+
+module wallywrapper;
+ 
+`include "parameter-defs.vh"
+
+  logic        clk;
+  logic        reset_ext, reset;
+
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                HWRITE;
+  logic [2:0]          HSIZE;
+  logic [2:0]          HBURST;
+  logic [3:0]          HPROT;
+  logic [1:0]          HTRANS;
+  logic                HMASTLOCK;
+  logic                HCLK, HRESETn;
+
+  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1  [3:0]  SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+  
+  // instantiate device to be tested
+  assign GPIOIN = 0;
+  assign UARTSin = 1;
+
+    assign HREADYEXT = 1;
+    assign HRESPEXT = 0;
+    assign HRDATAEXT = 0;
+
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+endmodule
diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h
index 6b6dd6dd9..ec179a0dd 100644
--- a/tests/coverage/WALLY-init-lib.h
+++ b/tests/coverage/WALLY-init-lib.h
@@ -63,6 +63,9 @@ trap_handler:
     bgez t0, exception  # if msb is clear, it is an exception
 
 interrupt:              # must be a timer interrupt 
+    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
+    li t1, 0x02004000   # MTIMECMP in CLINT
+    sd t0, 0(t1)        
     j trap_return       # clean up and return
 
 exception:
diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S
index 41d211467..63ee00c38 100644
--- a/tests/coverage/csrwrites.S
+++ b/tests/coverage/csrwrites.S
@@ -33,5 +33,8 @@ main:
     csrrw t0, satp, zero
     csrrw t0, stvec, zero
     csrrw t0, sscratch, zero
+    li t0, -2
+    csrrw t1, menvcfg, t0
+    csrrw t2, senvcfg, t0
 
     j done
diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S
index b2a52be06..29ad9b418 100644
--- a/tests/coverage/fpu.S
+++ b/tests/coverage/fpu.S
@@ -28,7 +28,7 @@
 
 main:
 
-    #bseti t0, zero, 14  # turn on FPU
+    bseti t0, zero, 14  # turn on FPU
     csrs mstatus, t0
 
     #Pull denormalized FP number from memory and pass it to fclass.S for coverage
@@ -94,7 +94,10 @@ main:
     fcvt.wu.q a0, ft3
     fcvt.l.q a0, ft3
     fcvt.lu.q a0, ft3
-
+    fcvt.l.s a0, ft0
+    fcvt.lu.s a0, ft0
+    fcvt.s.l ft0, t0
+    fcvt.s.lu ft0, t0
 
     // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
     # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
@@ -105,6 +108,25 @@ main:
     # fcvt.w.q a0, ft0
     # fcvt.q.d ft3, ft0
 
+    // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives)
+    // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes.
+    li t0, 0x3F812345 # random value slightly bigger than 1
+    li t1, 0x3F823456
+    fmv.w.x ft0, t0  # move int to fp register
+    fmv.w.x ft1, t1
+    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
+    li t1, 0x02004000   # MTIMECMP in CLINT
+    sd t0, 0(t1)
+    csrsi mstatus, 0b1000   # enable interrupts with mstatus.MIE
+    li t1, 0x0200bff8   # read MTIME in CLINT
+    ld t0, 0(t1)        
+    addi t0, t0, 11
+    li t1, 0x02004000   # MTIMECMP in CLINT
+    sd t0, 0(t1)        # write mtime+10 to cause interrupt soon  This is very touchy timing and is sensitive to cache line fetch latency
+    nop
+    fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
+    csrci mstatus, 0b1000   # disable interrupts with mstatus.MIE
+
     # Completing branch coverage in fctrl.sv
     .word 0x38007553    // Testing the all False case for 119 - funct7 under, op = 101 0011
     .word 0x40000053    // Line 145 All False Test case - illegal instruction?
@@ -134,6 +156,10 @@ main:
     .word 0x43007053 // illegal fcvt.d.* (bad Rs2D)
     .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1])
 
+    # Test floating point convert to integer and using result
+    fcvt.w.s t0, f0
+    add t1, t0, t0
+
     j done
 
 .section .data
@@ -145,4 +171,5 @@ TestData2:
 .word 0x7f800000 #INF
 .int 0xbf800000 #FP -1.0
 .int 0x7fa00000 #SNaN
-.int 0x3fffffff #OverFlow Test
\ No newline at end of file
+.int 0x3fffffff #OverFlow Test
+DivTestData:
diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S
new file mode 100644
index 000000000..51ca4d148
--- /dev/null
+++ b/tests/coverage/pmpadrdecs.S
@@ -0,0 +1,22 @@
+// pmpadrdecs
+// Liam Chalk, lchalk@hmc.edu, 4/27/2023
+// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
+
+#include "WALLY-init-lib.h" 
+main: 
+
+    # Writing values to pmpcfg0 to change AdrMode to 2 or 3
+    # pmpadrdec[0]
+    li t0, 0x0000000010
+    csrw pmpcfg0, t0
+    # pmpadrdec[1]
+    li t0, 0x0000001800
+    csrw pmpcfg0, t0
+    # pmpadrdec[2]
+    li t0, 0x0000180000
+    csrw pmpcfg0, t0
+    # pmpadrdec[4]
+    li t0, 0x1000000000
+    csrw pmpcfg0, t0
+
+    j done
\ No newline at end of file
diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S
index 5b3e37b56..bcc8f3950 100644
--- a/tests/coverage/pmpcfg.S
+++ b/tests/coverage/pmpcfg.S
@@ -1,6 +1,6 @@
 // pmpcfg part 1
 // Kevin Wan, kewan@hmc.edu, 4/18/2023
-// Liam Chalk, lchalk@hmc.edu, 4/19/2023
+// Liam Chalk, lchalk@hmc.edu, 4/25/2023
 // locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
 // See the next part in pmpcfg1.S
 
@@ -19,34 +19,59 @@ main:
 
     li t0, 0x90000000
     csrw pmpaddr0, t0
-    li t0, 0x00000017
+    li t0, 0x00001700
+    csrw pmpcfg0, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00001700
     csrw pmpcfg1, t0
 
     li t0, 0x90000000
     csrw pmpaddr0, t0
-    li t0, 0x00000017
+    li t0, 0x00001700
     csrw pmpcfg2, t0
 
     li t0, 0x90000000
     csrw pmpaddr0, t0
-    li t0, 0x00000017
+    li t0, 0x00001700
     csrw pmpcfg3, t0
 
     li t0, 0x90000000
     csrw pmpaddr1, t0
-    li t0, 0x00000017
+    li t0, 0x00001700
     csrw pmpcfg1, t0
 
     li t0, 0x90000000
-    csrw pmpaddr1, t0
-    li t0, 0x00000017
+    csrw pmpaddr2, t0
+    li t0, 0x00001700
     csrw pmpcfg2, t0
 
     li t0, 0x90000000
-    csrw pmpaddr1, t0
-    li t0, 0x00000017
+    csrw pmpaddr3, t0
+    li t0, 0x00001700
     csrw pmpcfg3, t0
 
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00170000
+    csrw pmpcfg0, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr2, t0
+    li t0, 0x00170000
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x17000000
+    csrw pmpcfg0, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr2, t0
+    li t0, 0x17000000
+    csrw pmpcfg2, t0
+
     li t0, 0x8800000000000000
     csrw pmpcfg2, t0
     li t0, 0x88000000000000
diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S
new file mode 100644
index 000000000..da2f0f40c
--- /dev/null
+++ b/tests/coverage/pmppriority.S
@@ -0,0 +1,161 @@
+// pmppriority test cases
+// Kevin Wan kewan@hmc.edu 4/27/2023
+// want memory ranges to match:
+// 1. only the most significant address and none of the lower ones, 
+// 2. the most significant address and ANY of the lower ones. 
+
+
+
+#include "WALLY-init-lib.h" 
+main: 
+
+    li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
+    csrw pmpaddr0, t1  
+    csrw pmpaddr1, t1
+    csrw pmpaddr2, t1  
+    csrw pmpaddr3, t1
+    csrw pmpaddr4, t1  
+    csrw pmpaddr5, t1
+    csrw pmpaddr6, t1
+    csrw pmpaddr7, t1
+
+    csrw pmpaddr8, t1
+    csrw pmpaddr9, t1
+    csrw pmpaddr10, t1  
+    csrw pmpaddr11, t1
+    csrw pmpaddr12, t1  
+    csrw pmpaddr13, t1
+    csrw pmpaddr14, t1
+    csrw pmpaddr15, t1
+
+
+    li t0, 0x1F
+    csrw pmpcfg0, t0 //set to XWR and NAPOT
+    sw zero, 0(sp)
+
+    li t0, 0x1F00
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F0000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F000000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F00000000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F0000000000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F000000000000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F1F1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x1F00000000000000
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+    
+    li t0, 0x1F1F1F1F1F1F1F1F
+    csrw pmpcfg0, t0 
+    sw zero, 0(sp)
+
+    li t0, 0x0
+    csrw pmpcfg0, t0
+    li t0, 0x1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F00
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F0000
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F00000000
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F0000000000
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F000000000000
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F00000000000000
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F1F1F1F1F
+    csrw pmpcfg0, t0
+    li t0, 0x1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+    li t0, 0x1F1F1F1F1F1F1F1F
+    csrw pmpcfg2, t0
+    sw zero, 0(sp)
+
+
+
+    j done
+
+
+    
\ No newline at end of file
diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S
index 5e187866b..d311f2a06 100644
--- a/tests/coverage/priv.S
+++ b/tests/coverage/priv.S
@@ -169,6 +169,24 @@ main:
     csrw mcounteren, t0
     csrw scounteren, t0
 
+    #getting the remainder of PMD instructions
+
+    #go to user mode
+    li a0, 0
+    ecall
+    #set status TVM to 0 by writing to bit 20 of mstatus as 0
+    #bseti t0, zero, 20 
+    sfence.vma zero, zero
+
+    # Go to supervisor mode
+    li a0, 1
+    ecall
+
+    sfence.vma zero, zero
+
+    li a0, 3
+    ecall
+
     # Write to satp when status.TVM is 1 from machine mode
     bseti t0, zero, 20 
     csrs mstatus, t0
@@ -203,6 +221,30 @@ main:
 
     csrr t0, hpmcounter22
 
+    #getting the mpp and mstatus Mpriv condition met
+    #go to machine mode
+    li a0, 3
+    ecall
+    # set bit 17 of mstatus to enable STATUS_MPRV
+    bseti t1, zero, 17
+    csrs mstatus, t1
+
+    li a0, 3
+    ecall
+
+    # set bit 21 of mstatus to 0 to disable STATUS_TW
+    csrr t1, mstatus
+    bseti t2, zero, 21
+    not t2, t2
+    and t1, t1, t2
+    csrs mstatus, t1
+
+    # go to user mode
+    li a0, 0
+    ecall
+
+    wfi
+
     j done
 
 
diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S
index bf71c0491..278568147 100644
--- a/tests/coverage/tlbASID.S
+++ b/tests/coverage/tlbASID.S
@@ -46,26 +46,21 @@ main:
     li t5, 0            # j = 0 // now use as a counter for new asid loop 
     li t3, 32     # Max amount of Loops = 32
 
-loop: bge t2, t3, nASID   # exit loop if i >= loops
-    lw t1, 0(t0)
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    li t5, 0x9001000000080080 // try making asid = 1 
+    csrw satp, t5
+    jalr t0
+     li t5, 0x9000000000080080 // try making asid = 0
+    csrw satp, t5
     li t4, 0x1000
     add t0, t0, t4
     addi t2, t2, 1
     j loop
-
-nASID: bne t5, zero, finished
-    li a0, 3   // go
-    ecall
-    li t5, 0x9000100000080080 // try making asid = 1 
-    csrw satp, t5
-    li a0, 1   
-    ecall
-    li t2, 0
-    li t0, 0xC0000000
-    li t5, 1 // make this not zero. 
-    j loop
-
-
+    
 finished:
     j done
 
@@ -130,4 +125,4 @@ pagetable:
     .8byte 0x200088CF
     .8byte 0x20008CCF
 
-    
\ No newline at end of file
+    
diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S
index 77e3a31c1..e6ae534bd 100644
--- a/tests/coverage/tlbGLB.S
+++ b/tests/coverage/tlbGLB.S
@@ -3,8 +3,9 @@
 //
 // Written: mmendozamanriquez@hmc.edu 4 April 2023
 //          nlimpert@hmc.edu
+// Modified: kevin.j.thomas@okstate.edu May/4/20203
 //
-// Purpose: coverage for the global check. 
+// Purpose: Coverage for the Page Table Entry Global flag check.
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -35,40 +36,47 @@ main:
     li t5, 0x9000000000080080 // try making asid = 0. 
     csrw satp, t5
 
-    # sfence.vma x0, x0
-
     # switch to supervisor mode
-    li a0, 1   
+    li a0, 1
     ecall
 
-    li t0, 0xC0000000
+    li t5, 0            # j = 0, run nASID only once
+    li t3, 32                       //Max amount of Loops = 32
+    li t4, 0x1000                   //offset between addressses.
+    li t1, 0x00008067               //load in jalr x0 x1 0 instruction to be stored
 
+setup:
+    li t0, 0xC0000000               //starting address
     li t2, 0             # i = 0
-    li t5, 0            # j = 0 // now use as a counter for new asid loop 
-    li t3, 32     # Max amount of Loops = 32
+    beq t5, zero, loop              //jump to first loop
 
-loop: bge t2, t3, nASID   # exit loop if i >= loops
-    lw t1, 0(t0)
-    li t4, 0x1000
-    add t0, t0, t4
-    addi t2, t2, 1
+loop2:  #jump to each of the addresses in different address space
+    bge t2, t3, done
+    jalr t0                         //jump to instruction at the virtual address
+    add t0, t0, t4                  //change address for next loop
+    addi t2, t2, 1                  //keep track of number of loops ran
+    j loop2
+
+loop:   #store jalr across memory
+    bge t2, t3, nASID   # exit loop if i >= loops
+    sw t1, 0(t0)                    //stores this jalr in the virtual address
+    fence.I                         //invalidate instruction cache
+    jalr t0                         //jump to instruction at the virtual address
+    add t0, t0, t4                  //change address for next loop
+    addi t2, t2, 1                  //keep track of number of loops ran
     j loop
 
-nASID: bne t5, zero, finished
-    li a0, 3   // go
+nASID:   #swap to different address space -> jump to each address
+    li a0, 3                        //swap to machine mode
     ecall
-    li t5, 0x9000100000080080 // try making asid = 1 
+    li t5, 0x9000100000080080       //swap to address space 1 from 0
     csrw satp, t5
-    li a0, 1   
+    li a0, 1                        // change back to supervisor mode.
     ecall
-    li t2, 0
-    li t0, 0xC0000000
-    li t5, 1 // make this not zero. 
-    j loop
+    li t5, 1                        //flag for finished after loops
+    j setup
 
 
-finished:
-    j done
 
 .data
 .align 19
@@ -79,17 +87,17 @@ pagetable:
 .align 12 // level 2 page table, contains direction to a gigapageg
     .8byte 0x0
     .8byte 0x0
-    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
-    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+    .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200208E1 // pointer to next page table entry at 8008 2000
 
 .align 12 // level 1 page table, points to level 0 page table
     .8byte 0x20020CE1
 
 .align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
-    .8byte 0x200000CF // access xC000 0000
-    .8byte 0x200004CF // access xC000 1000
-    .8byte 0x200008CF // access xC000 2000
-    .8byte 0x20000CCF // access xC000 3000
+    .8byte 0x200000EF // access xC000 0000
+    .8byte 0x200004EF // access xC000 1000
+    .8byte 0x200008EF // access xC000 2000
+    .8byte 0x20000CEF // access xC000 3000
 
     .8byte 0x200010EF // access xC000 4000
     .8byte 0x200014EF
@@ -131,4 +139,46 @@ pagetable:
     .8byte 0x200088EF
     .8byte 0x20008CEF
 
+        .8byte 0x200010EF // access xC000 4000
+    .8byte 0x200014EF
+    .8byte 0x200018EF
+    .8byte 0x20001CEF
+
+    .8byte 0x200020EF // access xC000 8000
+    .8byte 0x200024EF
+    .8byte 0x200028EF
+    .8byte 0x20002CEF
+
+    .8byte 0x200030EF // access xC000 C000
+    .8byte 0x200034EF
+    .8byte 0x200038EF
+    .8byte 0x20003CEF
+
+    .8byte 0x200040EF // access xC001 0000
+    .8byte 0x200044EF
+    .8byte 0x200048EF
+    .8byte 0x20004CEF
+
+    .8byte 0x200050EF // access xC001 4000
+    .8byte 0x200054EF
+    .8byte 0x200058EF
+    .8byte 0x20005CEF
+
+    .8byte 0x200060EF // access xC001 8000
+    .8byte 0x200064EF
+    .8byte 0x200068EF
+    .8byte 0x20006CEF
+
+    .8byte 0x200070EF // access xC001 C000
+    .8byte 0x200074eF
+    .8byte 0x200078EF
+    .8byte 0x20007CEF
+
+    .8byte 0x200080EF // access xC002 0000
+    .8byte 0x200084EF
+    .8byte 0x200088EF
+    .8byte 0x20008CEF
+
+
+
     
\ No newline at end of file
diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S
new file mode 100644
index 000000000..ede79f13e
--- /dev/null
+++ b/tests/coverage/tlbGP.S
@@ -0,0 +1,158 @@
+///////////////////////////////////////////
+// tlbGP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Create Page tables and access gigapages
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0xC0200000 // go to first gigapage 
+    li t4, 0x40000000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 64     # Max amount of Loops = 16
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1
+
+.align 12 
+    .8byte 0x000000CF  //8000 0000
+    .8byte 0x100000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF 
+
+
+
+
+    
diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S
index 6981d1f36..043e5dc4a 100644
--- a/tests/coverage/tlbMP.S
+++ b/tests/coverage/tlbMP.S
@@ -39,25 +39,22 @@ main:
     # switch to supervisor mode
     li a0, 1   
     ecall
+
     li t5, 0 
     li t0, 0x84000000 // go to first megapage
-    li t4, 0x1000 // put this outside the loop.
+    li t4, 0x200000 // put this outside the loop.
     li t2, 0      # i = 0
     li t3, 32     # Max amount of Loops = 16
 
-loop: bge t2, t3, lKP   # exit loop if i >= loops
-    lw t1, 0(t0)
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
     add t0, t0, t4
     addi t2, t2, 1
     j loop
 
-lKP: bne t5, zero, finished
-    li t0, 0x80000000 
-    slli t4, t4, 9
-    addi t5, t5, 1
-    li t2, 0
-    j loop
-
 finished:
     j done
 
@@ -116,6 +113,46 @@ pagetable:
     .8byte 0x20F000CF 
     .8byte 0x20F800CF
 
+    .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME.
+    .8byte 0x200800CF // access 8020,0000 
+    .8byte 0x201000CF // acesss 8040,0000
+    .8byte 0x201800CF // acesss 8060,0000
+
+    .8byte 0x202000CF // access 8080,0000
+    .8byte 0x202800CF // access 80A0,0000
+    .8byte 0x203000CF // access 80C0,0000
+    .8byte 0x203800CF // access 80E0,0000
+
+    .8byte 0x204000CF // access 8100,0000
+    .8byte 0x204800CF 
+    .8byte 0x205000CF 
+    .8byte 0x205800CF 
+
+    .8byte 0x206000CF // access 8180,0000
+    .8byte 0x206800CF 
+    .8byte 0x207000CF 
+    .8byte 0x207800CF 
+
+    .8byte 0x208000CF // access 8200,0000
+    .8byte 0x208800CF 
+    .8byte 0x209000CF 
+    .8byte 0x209800CF 
+
+    .8byte 0x20A000CF // access 8280,0000
+    .8byte 0x20A800CF 
+    .8byte 0x20B000CF 
+    .8byte 0x20B800CF 
+
+    .8byte 0x20C000CF // access 8300,0000
+    .8byte 0x20C800CF 
+    .8byte 0x20D000CF 
+    .8byte 0x20D800CF
+
+    .8byte 0x20E000CF // access 8380,0000
+    .8byte 0x20E800CF 
+    .8byte 0x20F000CF 
+    .8byte 0x20F800CF
+
     .8byte 0x20004CC1
      // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
                       // point to ... 
diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S
new file mode 100644
index 000000000..54857afbd
--- /dev/null
+++ b/tests/coverage/tlbTP.S
@@ -0,0 +1,144 @@
+///////////////////////////////////////////
+// tlbTP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0x80000000 // go to first gigapage 
+    li t4, 0x8000000000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 64     # run through 64 PTEs
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    li t1, 0x00008067
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
\ No newline at end of file
diff --git a/tests/fp/combined_IF_vectors/create_IF_vectors.sh b/tests/fp/combined_IF_vectors/create_IF_vectors.sh
index d6b83f599..707b2d5f4 100755
--- a/tests/fp/combined_IF_vectors/create_IF_vectors.sh
+++ b/tests/fp/combined_IF_vectors/create_IF_vectors.sh
@@ -3,6 +3,3 @@
 
 ./extract_testfloat_vectors.py
 ./extract_arch_vectors.py
-
-# to create tvs for evaluation of combined IFdivsqrt
-#./combined_IF_vectors/create_IF_vectors.sh
\ No newline at end of file
diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
index c80c7a843..12669bc58 100755
--- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py
+++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
@@ -1,7 +1,7 @@
 #! /usr/bin/python3
 
-# author: Alessandro Maiuolo
-# contact: amaiuolo@g.hmc.edu
+# author: Alessandro Maiuolo, Kevin Kim
+# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
 # date created: 3-29-2023
 
 # extract all arch test vectors
@@ -77,7 +77,7 @@ def create_vectors(my_config):
         rounding_mode = "X"
         flags = "XX"
         # use name to create our new tv
-        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
+        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w')
         # open vectors
         src_file1 = open(source_dir1 + vector1,'r')
         src_file2 = open(source_dir2 + vector2,'r')
@@ -144,7 +144,7 @@ def create_vectors(my_config):
                 answer2 = src_file2.readline().strip()
                 answer1 = src_file2.readline().strip()
                 answer = answer1 + answer2
-                # print(answer1,answer2)
+                #print(answer1,answer2)
                 if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
                     # parse through .S file
                     detected = False
@@ -179,13 +179,56 @@ def create_vectors(my_config):
                 else:
                     # print("read false")
                     reading = False
+        elif my_config.letter == "M" and my_config.bits == 32:
+            reading = True
+            while reading:
+                # print("trigger 64M")
+                # get answer from Ref...signature
+                # answers span two lines and are reversed
+                answer = src_file2.readline().strip()
+                print(f"Answer: {answer}")
+                #print(answer1,answer2)
+                if not (answer == "6f5ca309"): # if there is still stuff to read
+                    # parse through .S file
+                    detected = False
+                    done = False
+                    op1val = "0"
+                    op2val = "0"
+                    while not (detected or done):
+                        # print("det1")
+                        line = src_file1.readline()
+                        # print(line)
+                        if "op1val" in line:
+                            # print("det2")
+                            # parse line
+                            op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+                            if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+                                op1val = twos_comp(my_config.bits, op1val)
+                            if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
+                                op2val = line.split("op2val")[1].split("x")[1].strip()
+                                if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+                                if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+                                    op2val = twos_comp(my_config.bits, op2val)
+                            # go to next test in vector
+                            detected = True
+                        elif "RVTEST_CODE_END" in line:
+                            done = True
+                    # ints don't have flags
+                    flags = "XX"
+                    # put it all together
+                    if not done:
+                        translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
+                        dest_file.write(translation + "\n")
+                else:
+                    # print("read false")
+                    reading = False 
         else:
             while reading:
                 # get answer and flags from Ref...signature
                 answer = src_file2.readline()
-                # print(answer)
+                print(answer)
                 packed = src_file2.readline()[6:]
-                # print(packed)
+                print("Packed: ", packed)
                 if len(packed.strip())>0: # if there is still stuff to read
                     # print("packed")
                     # parse through .S file
@@ -223,13 +266,13 @@ def create_vectors(my_config):
                 else:
                     # print("read false")
                     reading = False
-        print("out")
+        # print("out")
         dest_file.close()
         src_file1.close()
         src_file2.close()
 
 config_list = [
-Config(32, "M", "div", "div_", 0),
+Config(32, "M", "div", "div-", 0),
 Config(32, "F", "fdiv", "fdiv", 1),
 Config(32, "F", "fsqrt", "fsqrt", 2),
 Config(32, "M", "rem", "rem-", 3),
diff --git a/tests/fp/create_all_vectors.sh b/tests/fp/create_all_vectors.sh
index 38cfd555a..bbade6d11 100755
--- a/tests/fp/create_all_vectors.sh
+++ b/tests/fp/create_all_vectors.sh
@@ -5,4 +5,4 @@ mkdir -p vectors
 ./remove_spaces.sh
 
 # to create tvs for evaluation of combined IFdivsqrt
-#./combined_IF_vectors/create_IF_vectors.sh
\ No newline at end of file
+cd combined_IF_vectors; ./create_IF_vectors.sh
\ No newline at end of file
diff --git a/tests/riscof/sail_cSim/env/model_test.h b/tests/riscof/sail_cSim/env/model_test.h
index be07d625d..62611529b 100644
--- a/tests/riscof/sail_cSim/env/model_test.h
+++ b/tests/riscof/sail_cSim/env/model_test.h
@@ -51,5 +51,17 @@
 
 #define RVMODEL_CLEAR_MEXT_INT
 
+#define RVMODEL_CLR_MSW_INT
+#define RVMODEL_CLR_MTIMER_INT
+#define RVMODEL_CLR_MEXT_INT
+#define RVMODEL_SET_SSW_INT
+#define RVMODEL_CLR_SSW_INT
+#define RVMODEL_CLR_STIMER_INT
+#define RVMODEL_CLR_SEXT_INT
+#define RVMODEL_SET_VSW_INT
+#define RVMODEL_CLR_VSW_INT
+#define RVMODEL_CLR_VTIMER_INT
+#define RVMODEL_CLR_VEXT_INT
+
 
 #endif // _COMPLIANCE_MODEL_H
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index aa32757ca..972b838e1 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -94,7 +94,8 @@ class sail_cSim(pluginTemplate):
 
             execute = "@cd "+testentry['work_dir']+";"
 
-            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
+#            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
+            cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
             compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
             execute+=compile_cmd+";"
 
@@ -129,4 +130,5 @@ class sail_cSim(pluginTemplate):
             make.add_target(execute)
 #        make.execute_all(self.work_dir)
 # DH 7/26/22 increase timeout so sim will finish on slow machines
-        make.execute_all(self.work_dir, timeout = 1800)
+# DH 5/17/23 increase timeout to 3600 seconds
+        make.execute_all(self.work_dir, timeout = 3600)
diff --git a/tests/riscof/spike/env/model_test.h b/tests/riscof/spike/env/model_test.h
index 3890c4985..0757f6c49 100644
--- a/tests/riscof/spike/env/model_test.h
+++ b/tests/riscof/spike/env/model_test.h
@@ -56,5 +56,17 @@
 
 #define RVMODEL_CLEAR_MEXT_INT
 
+#define RVMODEL_CLR_MSW_INT
+#define RVMODEL_CLR_MTIMER_INT
+#define RVMODEL_CLR_MEXT_INT
+#define RVMODEL_SET_SSW_INT
+#define RVMODEL_CLR_SSW_INT
+#define RVMODEL_CLR_STIMER_INT
+#define RVMODEL_CLR_SEXT_INT
+#define RVMODEL_SET_VSW_INT
+#define RVMODEL_CLR_VSW_INT
+#define RVMODEL_CLR_VTIMER_INT
+#define RVMODEL_CLR_VEXT_INT
+
 
 #endif // _COMPLIANCE_MODEL_H
diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py
index 308d55f28..4a5b68b96 100644
--- a/tests/riscof/spike/riscof_spike.py
+++ b/tests/riscof/spike/riscof_spike.py
@@ -159,7 +159,8 @@ class spike(pluginTemplate):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-          cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros)
+#          cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros)
+          cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen, test, elf, compile_macros)
 
 	  # if the user wants to disable running the tests and only compile the tests, then
 	  # the "else" clause is executed below assigning the sim command to simple no action
@@ -190,7 +191,8 @@ class spike(pluginTemplate):
       # parallel using the make command set above.
       #make.execute_all(self.work_dir)
       # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines
-      make.execute_all(self.work_dir, timeout = 1800) 
+      # DH 5/17/23 increase timeout to 3600 seconds
+      make.execute_all(self.work_dir, timeout = 3600) 
 
 
       # if target runs are not required then we simply exit as this point after running all
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
index d885ab6c0..d5a114ab3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,3 +1,5 @@
+FFFFFFFF # stimecmp readback
+80000000 # menvcfg readback
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
 00000000 # mtval of faulting instruction address (0x0)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 277f67274..c51eec965 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -280,7 +280,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
-
+ 
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
index 7aac05823..b0ad29128 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
index a43531cc7..8223b8bf6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
index ace47a806..bbaf214c0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
index c13dde253..01097e03f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",endianness)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
index 21ff79d10..94021491d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
index 6c91f64fc..bbb9fca5c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
index 3a4626b64..b1f801ba2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
index 888011ba6..06e419eb2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
index 0faa5b2e9..4df3a9e0f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",mmu)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
index 409fae185..f864d255c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
index e2865be3e..4c2f3dcc8 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mtvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
index febab70ef..4c06a2def 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
@@ -23,7 +23,7 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 // this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); 
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
index 414fb44b3..038b9ce00 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
index a6ed546a8..f48771c5e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
index 3000ddcde..0c1c7bbb2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
@@ -36,7 +36,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
index 0f93d4086..4daddb3fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
index dd412abe7..1c7d0edb0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
index 64c0567cb..d4d6c4f35 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
index 1b091238d..75afdb0b8 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32IAF")
+RVTEST_ISA("RV32IAF_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-fp-enabled)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
index 1fc792a98..bb3c1d738 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-mie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
index 81e230273..60e9c5c8b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
index 48df172f4..8f323c1c2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;", status-tvm)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
index 15155fb76..faa2598f3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tw)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
index e42ffb6dc..f666c421e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",stvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
index 9385e3547..2b5daf264 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Sstc_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -34,8 +34,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
-
+WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
+WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
 // test 5.3.1.4 Basic trap tests 
 
 // instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
index 85758b101..d779f74fa 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def NO_SAIL=True;",trap-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
index e0f81a2c0..c4041c972 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
index df812db64..98da8180e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
index deba11c29..101154923 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
index 9e19ff202..2ed238e23 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
 
 .equ UART, 0x10000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
index 720d83956..61d73a4f7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I")
+RVTEST_ISA("RV32I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
index 701b28235..330ea5c63 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
@@ -9,7 +9,7 @@
 #include "arch_test.h"
 
 # Test Virtual Machine (TVM) used by program.
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zifencei")
 
 # Test code region
 .section .text.init
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
index cb872b5b8..5c9b816fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,3 +1,7 @@
+FFFFFFFF # stimecmp low bits
+00000000 # stimecmp high bits
+00000000 # menvcfg low bits
+80000000 # menvcfg high bits
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 44a4ea66f..1e887b9fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -274,7 +274,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
-
+ 
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
index 838e4654d..3aaa58706 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
index 2ff2e99f2..4512bd9cb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
index 848186a98..5bd6c458b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
index 38bc6fd18..b5505e1b1 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
index 6e3ebcbcb..c991721ea 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
index 664e8ce08..df688afbd 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mie)
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
index 5f4ae446a..f7e183ba7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
index 9dc0b5c43..543df7cbf 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
index ed11d0bda..76ce91bfb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",mmu-sv39)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
index cd35b9a2c..80df44a1a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
index 4948abe20..ce2685428 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sv48)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
index 702645b63..9b8925fb5 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
index b192d229c..3cb9b2421 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",mtvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
index 69562c59d..6c985c98b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
@@ -23,7 +23,7 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 // this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); 
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
index b50b20f96..ce15c0525 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
index 5a6dc34e2..3f312c9b3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
index 3048c1ebc..a5385e001 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
@@ -35,7 +35,7 @@
 #define PLIC_RANGE     0x03FFFFFF
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
index fc3864d38..140c0d97d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
index 7a565c71d..a711e4729 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
index 28df4374c..fa2bd599c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
index 8479dbde5..7ce55f79a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64IAF")
+RVTEST_ISA("RV64IAF_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;",status-fp-enabled)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
index 6fc868984..2d24f92b4 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-mie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
index e9a9e443b..c52f23c3d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
index 72d3a8600..efef21093 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-64.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;", status-tvm)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
index 184b022ed..43ddf8cc9 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
@@ -23,7 +23,7 @@
 
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-tw)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
index ad3a3e6f7..1fba96a74 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
index 05ecf515a..92e3709c5 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",stvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
index b44b6440d..24caa603a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Sstc_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -33,7 +33,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
+WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
+WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
 
 // test 5.3.1.4 Basic trap tests 
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
index 525e79276..4ed0941ae 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
index 78692fd1c..041d548ad 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
index e10e5d988..af0d9f32d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
index 3cbf3591b..2c2b2ab07 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
index c67d3c24a..6430f2078 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
 
 INIT_TESTS