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Only sample if rvvi is valid

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Jordan Carlin 2025-02-08 23:22:45 -08:00
parent 51986982a2
commit 578441bfc3
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1 changed files with 4 additions and 2 deletions
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testbench/common/trace2riscvISACOV.sv
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@ -19,7 +19,9 @@ module trace2riscvISACOV(rvviTrace rvvi);
// If RVVI accepts more than one instruction or hart, iterate over all of them in the // If RVVI accepts more than one instruction or hart, iterate over all of them in the
// correct order of retirement (TODO: multiple instructions/harts not implemented) // correct order of retirement (TODO: multiple instructions/harts not implemented)
always_ff @(posedge rvvi.clk) begin always_ff @(posedge rvvi.clk) begin
riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); if (rvvi.valid[0][0] == 1) begin
$display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass});
$display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass);
end
end end
endmodule endmodule