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28 lines
1.1 KiB
Systemverilog
28 lines
1.1 KiB
Systemverilog
// trace2riscvISACOV.sv
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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`include "RISCV_coverage.svh"
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module trace2riscvISACOV(rvviTrace rvvi);
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// Connect coverage class to RVVI trace interface
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coverage #(rvvi.ILEN, rvvi.XLEN, rvvi.FLEN, rvvi.VLEN, rvvi.NHART, rvvi.RETIRE) riscvISACOV;
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initial begin
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riscvISACOV = new(rvvi);
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$display("trace2riscvISACOV: coverage initialized");
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end
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// Dissassemble instruction from RVVI trace for processing by coverage model
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string disass;
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dissassembler #(rvvi.XLEN) dissassembler(rvvi.insn[0][0], disass);
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// Invoke the riscvISACOV sample function on each clock edge for the current Instruction
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// If RVVI accepts more than one instruction or hart, iterate over all of them in the
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// correct order of retirement (TODO: multiple instructions/harts not implemented)
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always_ff @(posedge rvvi.clk) begin
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if (rvvi.valid[0][0] == 1) begin
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riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass});
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$display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass);
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end
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end
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endmodule
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