From 5591b447d62909823e4f695fefc7a022a6c93bf1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 16 Apr 2023 13:25:02 -0500 Subject: [PATCH] Fixed more issues with arty a7 constarints. --- fpga/constraints/constraints-ArtyA7.xdc | 127 ++++++++++++------------ fpga/generator/Makefile | 1 + fpga/generator/xlnx_mmcm.tcl | 6 +- 3 files changed, 68 insertions(+), 66 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index e1a23c1e7..a9b78a78d 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -1,13 +1,13 @@ # The main clocks are all autogenerated by the Xilinx IP -# mmcm_clkout1 is the 22Mhz clock from the DDR3 IP used to drive wally and the AHB Bus. +# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus. # mmcm_clkout0 is the clock output of the DDR3 memory interface / 4. # This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP. -# clock comes from pin E3 and is 100Mhz -# output of mmcm is /4 => 25Mhz -#create_clock -period 25.000 -name mmcm_clkout1 -waveform {0.000 12.500} [get_nets xlnx_ddr3_c0/ui_clk] +create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +##### clock ##### +set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] +set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}] ##### GPI #### set_property PACKAGE_PIN D9 [get_ports {GPI[0]}] @@ -18,8 +18,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}] -set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports {GPI[*]}] set_max_delay -from [get_ports {GPI[*]}] 10.000 ##### GPO #### @@ -28,14 +28,14 @@ set_property PACKAGE_PIN F6 [get_ports {GPO[1]}] set_property PACKAGE_PIN E1 [get_ports {GPO[2]}] set_property PACKAGE_PIN G3 [get_ports {GPO[4]}] set_property PACKAGE_PIN J4 [get_ports {GPO[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}] set_max_delay -to [get_ports {GPO[*]}] 10.000 -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] ##### UART ##### @@ -47,16 +47,16 @@ set_max_delay -to [get_ports UARTSout] 10.000 set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] set_property IOSTANDARD LVCMOS33 [get_ports UARTSout] set_property DRIVE 4 [get_ports UARTSout] -set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin] -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports UARTSin] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout] ##### reset ##### #************** reset is inverted -set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports reset] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports reset] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports reset] set_max_delay -from [get_ports reset] 15.000 set_false_path -from [get_ports reset] set_property PACKAGE_PIN C2 [get_ports {reset}] @@ -104,54 +104,54 @@ set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] # ddr3 -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[1] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[2] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[3] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[4] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[5] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[6] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[7] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[8] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[9] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[10] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[11] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[12] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[13] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[14] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[15] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[13] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[12] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[11] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[10] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[9] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[8] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[7] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[6] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[5] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[4] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[3] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[2] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[1] -set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[2] -set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[1] -set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0] set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0] set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n -set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n -set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n -set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n -set_property IOSTANDARD SSTL15 [get_ports ddr3_cke[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_odt[0] -set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n +set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0] +set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0] set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] @@ -205,6 +205,7 @@ set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] # **** may have to bring this one back -#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 +#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 15.000 +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 2d6a3a142..843e2438a 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -28,6 +28,7 @@ FPGA: PreProcessFiles IP SDC IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr3-ArtyA7.log \ + $(dst)/xlnx_mmcm.log \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl index 74efa74a9..2f003e7a5 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/xlnx_mmcm.tcl @@ -13,10 +13,10 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {false} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {167} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ - CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]