mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Lots more python updates
This commit is contained in:
Jordan Carlin
parent
21e35c9068
commit
51c3d59605
@ -65,10 +65,7 @@ with open(resultfile, mode='w', newline='') as csvfile:
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# Loop through each architecture and run the make commands
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for arch in arch_list:
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if(str in arch):
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xlen_value='32'
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else:
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xlen_value='64'
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xlen_value = "32" if str in arch else "64"
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os.system("make clean")
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make_all = f"make all XLEN={xlen_value} ARCH={arch}"
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os.system(make_all)
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@ -30,12 +30,8 @@ def tabulate_arch_sweep(directory):
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file = case+"_"+arch+".json"
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file_path = os.path.join(directory, file)
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lines = []
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try:
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f = open(file_path)
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with open(file_path) as f:
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lines = f.readlines()
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except:
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f.close()
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#print(file_path+" does not exist")
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for line in lines:
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#print("File: "+file+" Line: "+line)
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#p = re.compile('".*" : .*,')
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@ -16,7 +16,7 @@ def loadCoremark():
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keywordlist = ["CoreMark 1.0", "CoreMark Size", "MTIME", "MINSTRET", "Branches Miss Predictions", "BTB Misses"]
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for keyword in keywordlist:
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bashInst = "cat " + coremarkPath + " | grep \"" + keyword + "\" | cut -d \':\' -f 2 | cut -d \" \" -f 2 | tail -1"
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bashInst = "cat " + coremarkPath + ' | grep "' + keyword + "\" | cut -d ':' -f 2 | cut -d \" \" -f 2 | tail -1"
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result = subprocess.run(bashInst, stdout=subprocess.PIPE, shell=True)
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if (debug): print(result)
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coremarkData[keyword] = int(result.stdout)
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@ -25,8 +25,8 @@ def loadCoremark():
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def loadEmbench(embenchPath, embenchData):
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"""loads the embench data dictionary"""
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f = open(embenchPath)
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embenchData = json.load(f)
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with open(embenchPath) as f:
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embenchData = json.load(f)
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if (debug): print(embenchData)
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return embenchData
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@ -284,7 +284,7 @@ def main(args):
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elif lninfo[1] == 'A':
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atoms += 1
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if not result == lninfo[2]:
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if result != lninfo[2]:
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print(f"Result mismatch at address {lninfo[0]}. Wally: {lninfo[2]}, Sim: {result}")
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mismatches += 1
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if args.dist:
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@ -473,7 +473,7 @@ class TestRunner:
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if failed_configs:
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md_file.write("## Failed Configurations\n\n")
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for config, log_file in failed_configs:
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md_file.write(f"- <span class=\"failure\" style=\"color: red;\">{config}</span> ({log_file})\n")
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md_file.write(f'- <span class="failure" style="color: red;">{config}</span> ({log_file})\n')
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md_file.write("\n")
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else:
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md_file.write("## Failed Configurations\n")
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@ -481,7 +481,7 @@ class TestRunner:
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md_file.write("\n## Passed Configurations\n")
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for config in passed_configs:
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md_file.write(f"- <span class=\"success\" style=\"color: green;\">{config}</span>\n")
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md_file.write(f'- <span class="success" style="color: green;">{config}</span>\n')
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self.logger.info("writing test outputs to markdown")
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@ -526,7 +526,7 @@ class TestRunner:
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md_file.write("\n")
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except subprocess.CalledProcessError as e:
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# Handle if the command fails
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md_file.write(f"Failed to identify host and Operating System information: {str(e)}")
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md_file.write(f"Failed to identify host and Operating System information: {e!s}")
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# Which tests did we run
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md_file.write(f"\n**Tests made:** `make {test_type}`\n")
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@ -548,7 +548,7 @@ class TestRunner:
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if len(item) == 0:
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md_file.write("\n")
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md_file.write("* <span class=\"no-failure\" style=\"color: green;\">No failures</span>\n")
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md_file.write('* <span class="no-failure" style="color: green;">No failures</span>\n')
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md_file.write("\n")
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else:
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for failed_test in item:
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@ -556,7 +556,7 @@ class TestRunner:
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log_file = failed_test[1]
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md_file.write("\n")
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md_file.write(f"* <span class=\"failure\" style=\"color: red;\">{config}</span> ({log_file})\n")
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md_file.write(f'* <span class="failure" style="color: red;">{config}</span> ({log_file})\n')
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md_file.write("\n")
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# Successful Tests
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@ -571,14 +571,14 @@ class TestRunner:
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if len(item) == 0:
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md_file.write("\n")
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md_file.write("* <span class=\"no-successes\" style=\"color: red;\">No successes</span>\n")
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md_file.write('* <span class="no-successes" style="color: red;">No successes</span>\n')
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md_file.write("\n")
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else:
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for passed_tests in item:
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config = passed_tests
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md_file.write("\n")
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md_file.write(f"* <span class=\"success\" style=\"color: green;\">{config}</span>\n")
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md_file.write(f'* <span class="success" style="color: green;">{config}</span>\n')
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md_file.write("\n")
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self.logger.info("Combining markdown files")
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@ -800,7 +800,7 @@ def main():
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logger.info(f"The total failures for all tests ran are: {total_number_failures}")
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# Copy actual test logs from sim/questa, sim/verilator, sim/vcs
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if not args.tests == "test_lint":
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if args.tests != 'test_lint':
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test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"])
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#############################################
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@ -46,14 +46,14 @@ def ParseBranchListFile(path):
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is formated in row columns. Each row is a trace with the file, branch predictor type, and the parameters.
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parameters can be any number and depend on the predictor type. Returns a list of lists.'''
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lst = []
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BranchList = open(path)
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for line in BranchList:
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tokens = line.split()
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predictorLog = os.path.dirname(path) + '/' + tokens[0]
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predictorType = tokens[1]
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predictorParams = tokens[2::]
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lst.append([predictorLog, predictorType, predictorParams])
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#print(predictorLog, predictorType, predictorParams)
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with open(path) as BranchList:
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for line in BranchList:
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tokens = line.split()
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predictorLog = os.path.dirname(path) + '/' + tokens[0]
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predictorType = tokens[1]
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predictorParams = tokens[2::]
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lst.append([predictorLog, predictorType, predictorParams])
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#print(predictorLog, predictorType, predictorParams)
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return lst
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def ProcessFile(fileName):
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@ -62,22 +62,22 @@ def ProcessFile(fileName):
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# 1 find lines with Read memfile and extract test name
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# 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
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benchmarks = []
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transcript = open(fileName)
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HPMClist = { }
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testName = ''
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for line in transcript.readlines():
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lineToken = line.split()
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if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
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opt = lineToken[3].split('/')[-4]
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testName = lineToken[3].split('/')[-1].split('.')[0]
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HPMClist = { }
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elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
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countToken = line.split('=')[1].split()
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value = int(countToken[0]) if countToken[0] != 'x' else 0
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name = ' '.join(countToken[1:])
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HPMClist[name] = value
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elif ('is done' in line):
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benchmarks.append((testName, opt, HPMClist))
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with open(fileName) as transcript:
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for line in transcript.readlines():
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lineToken = line.split()
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if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
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opt = lineToken[3].split('/')[-4]
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testName = lineToken[3].split('/')[-1].split('.')[0]
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HPMClist = { }
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elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
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countToken = line.split('=')[1].split()
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value = int(countToken[0]) if countToken[0] != 'x' else 0
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name = ' '.join(countToken[1:])
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HPMClist[name] = value
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elif ('is done' in line):
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benchmarks.append((testName, opt, HPMClist))
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return benchmarks
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@ -268,21 +268,12 @@ def addTests(tests, sim):
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for test in tests:
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config = test[0]
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suites = test[1]
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if len(test) >= 3:
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args = f" --args {test[2]}"
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else:
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args = ""
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if len(test) >= 4:
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gs = test[3]
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else:
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gs = "All tests ran without failures"
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args = f" --args {test[2]}" if len(test) >= 3 else ""
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gs = test[3] if len(test) >= 4 else "All tests ran without failures"
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cmdPrefix=f"wsim --sim {sim} {coverStr} {config}"
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for t in suites:
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sim_log = f"{sim_logdir}{config}_{t}.log"
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if len(test) >= 5:
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grepfile = sim_logdir + test[4]
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else:
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grepfile = sim_log
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grepfile = sim_logdir + test[4] if len(test) >= 5 else sim_log
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tc = TestCase(
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name=t,
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variant=config,
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@ -535,9 +526,7 @@ def main():
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os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
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elif args.buildroot:
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TIMEOUT_DUR = 60*1440 # 1 day
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elif args.testfloat:
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TIMEOUT_DUR = 30*60 # seconds
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elif args.nightly:
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elif args.testfloat or args.nightly:
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TIMEOUT_DUR = 30*60 # seconds
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else:
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TIMEOUT_DUR = 10*60 # seconds
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@ -545,10 +534,7 @@ def main():
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# Scale the number of concurrent processes to the number of test cases, but
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# max out at a limited number of concurrent processes to not overwhelm the system
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# right now fcov, ccov, nightly all use Imperas
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if (args.ccov or args.fcov or args.nightly):
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ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses
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else:
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ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests
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ImperasDVLicenseCount = 16 if args.ccov or args.fcov or args.nightly else 10000
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with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
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num_fail = 0
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results = {}
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@ -67,8 +67,8 @@ def main():
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parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
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parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
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args = parser.parse_args()
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simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1"
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testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"
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simargs = "I_CACHE_ADDR_LOGGER=1\\'b1 D_CACHE_ADDR_LOGGER=1\\'b1"
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testcmd = "wsim --sim " + args.sim + ' rv64gc {} --params "' + simargs + '" > /dev/null'
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#cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose"
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cachecmd = "CacheSim.py 64 4 56 44 -f {}"
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mismatches = 0
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@ -13,8 +13,8 @@ if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'):
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print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier')
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print('==============================================================')
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else:
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urlFile = open(sys.path[0]+'/slack-webhook-url.txt')
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url = urlFile.readline().strip('\n')
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with open(sys.path[0]+'/slack-webhook-url.txt') as urlFile:
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url = urlFile.readline().strip('\n')
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# Traverse 3 parents up the process tree
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result = subprocess.check_output('ps -o ppid -p $PPID',shell=True)
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@ -25,7 +25,7 @@ else:
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result = subprocess.check_output('ps -o cmd -p '+PPID3,shell=True)
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cmdName = str(result).split('\\n')[1]
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# Get current time
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timezone_offset = -8.0 # Pacific Standard Time (UTC−08:00)
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timezone_offset = -8.0 # Pacific Standard Time (UTC-08:00)
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tzinfo = timezone(timedelta(hours=timezone_offset))
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time = datetime.now(tzinfo).strftime('%I:%M %p')
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# Send message
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@ -24,7 +24,7 @@ def runFindCommand(cmd):
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res = subprocess.check_output(cmd, shell=True, )
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res = str(res)
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res = res.replace("\\n", " ") # replace newline with space
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res = res.replace("\'", "") # strip off quotation marks
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res = res.replace("'", "") # strip off quotation marks
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res = res[1:] # strip off leading b from byte string
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return res
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@ -81,13 +81,10 @@ def processArgs(wkdir, args):
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def setupParamOverrides(wkdir, args):
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paramOverrideFile = os.path.join(wkdir, "param_overrides.txt")
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with open(paramOverrideFile, "w", encoding="utf-8") as f:
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with open(paramOverrideFile, "w") as f:
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for param in args.params.split():
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[param, value] = param.split("=")
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if r"\'" in value: # for bit values
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value = value.replace(r"\'", "'")
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else: # for strings
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value = f'"{value}"'
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value = value.replace("\\'", "'") if "\\'" in value else f'"{value}"' # transform quotes/bit indicators
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f.write(f"assign {value} {args.tb}/{param}\n")
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return f" -parameters {wkdir}/param_overrides.txt "
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@ -27,48 +27,44 @@ def synthsintocsv():
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specReg = re.compile('[a-zA-Z0-9]+')
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metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
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file = open("Summary.csv", "w")
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writer = csv.writer(file)
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writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
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with open("Summary.csv", "w") as file:
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writer = csv.writer(file)
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writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
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for oneSynth in allSynths:
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descrip = specReg.findall(oneSynth)
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# print("From " + oneSynth + " Find ")
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# for d in descrip:
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# print(d)
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if (descrip[3] == "sram"):
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base = 4
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else:
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base = 3
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width = descrip[base][:4]
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config = descrip[base][4:]
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if descrip[base+1][-2:] == 'nm':
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mod = ''
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else:
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mod = descrip[base+1]
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descrip = descrip[1:]
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tech = descrip[base+1][:-2]
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freq = descrip[base+2]
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# print(width, config, mod, tech, freq)
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metrics = []
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for phrase in ['Path Slack', 'Design Area']:
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bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
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bashCommand = bashCommand.format(phrase)
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# print(bashCommand)
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try:
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output = subprocess.check_output(['bash','-c', bashCommand])
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nums = metricReg.findall(str(output))
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nums = [float(m) for m in nums]
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metrics += nums
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except:
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print(width + config + tech + '_' + freq + " doesn't have reports")
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if metrics == []:
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pass
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else:
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delay = 1000/int(freq) - metrics[0]
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area = metrics[1]
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writer.writerow([width, config, mod, tech, freq, delay, area])
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file.close()
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for oneSynth in allSynths:
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descrip = specReg.findall(oneSynth)
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# print("From " + oneSynth + " Find ")
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# for d in descrip:
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# print(d)
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base = 4 if descrip[3] == "sram" else 3
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width = descrip[base][:4]
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config = descrip[base][4:]
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if descrip[base+1][-2:] == 'nm':
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mod = ''
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else:
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mod = descrip[base+1]
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descrip = descrip[1:]
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tech = descrip[base+1][:-2]
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freq = descrip[base+2]
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# print(width, config, mod, tech, freq)
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metrics = []
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for phrase in ['Path Slack', 'Design Area']:
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bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
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bashCommand = bashCommand.format(phrase)
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# print(bashCommand)
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try:
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output = subprocess.check_output(['bash','-c', bashCommand])
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nums = metricReg.findall(str(output))
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nums = [float(m) for m in nums]
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metrics += nums
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except:
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print(width + config + tech + '_' + freq + " doesn't have reports")
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if metrics == []:
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pass
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else:
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delay = 1000/int(freq) - metrics[0]
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area = metrics[1]
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writer.writerow([width, config, mod, tech, freq, delay, area])
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def synthsfromcsv(filename):
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@ -93,7 +89,7 @@ def freqPlot(tech, width, config):
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freqsL, delaysL, areasL = ([[], []] for i in range(3))
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for oneSynth in allSynths:
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if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
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if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & (oneSynth.mod == 'orig'):
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ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period
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freqsL[ind] += [oneSynth.freq]
|
||||
delaysL[ind] += [oneSynth.delay]
|
||||
@ -101,10 +97,7 @@ def freqPlot(tech, width, config):
|
||||
|
||||
fig, (ax1, ax2) = plt.subplots(2, 1, sharex=True)
|
||||
allFreqs = list(flatten(freqsL))
|
||||
if allFreqs != []:
|
||||
median = np.median(allFreqs)
|
||||
else:
|
||||
median = 0
|
||||
median = np.median(allFreqs) if allFreqs != [] else 0
|
||||
|
||||
for ind in [0,1]:
|
||||
areas = areasL[ind]
|
||||
@ -169,11 +162,10 @@ def plotFeatures(tech, width, config):
|
||||
delays, areas, labels = ([] for i in range(3))
|
||||
freq = techdict[tech].targfreq
|
||||
for oneSynth in allSynths:
|
||||
if (tech == oneSynth.tech) & (freq == oneSynth.freq):
|
||||
if (oneSynth.config == config) & (width == oneSynth.width):
|
||||
delays += [oneSynth.delay]
|
||||
areas += [oneSynth.area]
|
||||
labels += [oneSynth.mod]
|
||||
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.config == config) & (width == oneSynth.width):
|
||||
delays += [oneSynth.delay]
|
||||
areas += [oneSynth.area]
|
||||
labels += [oneSynth.mod]
|
||||
|
||||
if (delays == []):
|
||||
print("No delays found for tech ", tech, " freq ", freq, ". Did you set --sky130freq, --sky90freq and --tsmcfreq?\n")
|
||||
|
||||
@ -50,49 +50,48 @@ def synthsintocsv():
|
||||
specReg = re.compile("[a-zA-Z0-9]+")
|
||||
metricReg = re.compile("-?\d+\.\d+[e]?[-+]?\d*")
|
||||
|
||||
file = open("ppaData.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Module",
|
||||
"Tech",
|
||||
"Width",
|
||||
"Target Freq",
|
||||
"Delay",
|
||||
"Area",
|
||||
"L Power (nW)",
|
||||
"D energy (nJ)",
|
||||
]
|
||||
)
|
||||
with open("ppaData.csv", "w") as file:
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Module",
|
||||
"Tech",
|
||||
"Width",
|
||||
"Target Freq",
|
||||
"Delay",
|
||||
"Area",
|
||||
"L Power (nW)",
|
||||
"D energy (nJ)",
|
||||
]
|
||||
)
|
||||
|
||||
for oneSynth in allSynths:
|
||||
module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
|
||||
tech = tech[:-2]
|
||||
metrics = []
|
||||
for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
|
||||
bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
|
||||
bashCommand = bashCommand.format(*phrase)
|
||||
try:
|
||||
output = subprocess.check_output(["bash", "-c", bashCommand])
|
||||
except:
|
||||
print(module + width + tech + freq + " doesn't have reports")
|
||||
print("Consider running cleanup() first")
|
||||
nums = metricReg.findall(str(output))
|
||||
nums = [float(m) for m in nums]
|
||||
metrics += nums
|
||||
delay = 1000 / int(freq) - metrics[0]
|
||||
area = metrics[1]
|
||||
lpower = metrics[4]
|
||||
tpower = (metrics[2] + metrics[3] + metrics[4]*.000001)
|
||||
denergy = (
|
||||
(tpower) / int(freq) * 1000
|
||||
) # (switching + internal powers)*delay, more practical units for regression coefs
|
||||
for oneSynth in allSynths:
|
||||
module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
|
||||
tech = tech[:-2]
|
||||
metrics = []
|
||||
for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
|
||||
bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
|
||||
bashCommand = bashCommand.format(*phrase)
|
||||
try:
|
||||
output = subprocess.check_output(["bash", "-c", bashCommand])
|
||||
except:
|
||||
print(module + width + tech + freq + " doesn't have reports")
|
||||
print("Consider running cleanup() first")
|
||||
nums = metricReg.findall(str(output))
|
||||
nums = [float(m) for m in nums]
|
||||
metrics += nums
|
||||
delay = 1000 / int(freq) - metrics[0]
|
||||
area = metrics[1]
|
||||
lpower = metrics[4]
|
||||
tpower = (metrics[2] + metrics[3] + metrics[4]*.000001)
|
||||
denergy = (
|
||||
(tpower) / int(freq) * 1000
|
||||
) # (switching + internal powers)*delay, more practical units for regression coefs
|
||||
|
||||
if "flop" in module: # since two flops in each module
|
||||
[area, lpower, denergy] = [n / 2 for n in [area, lpower, denergy]]
|
||||
if "flop" in module: # since two flops in each module
|
||||
[area, lpower, denergy] = [n / 2 for n in [area, lpower, denergy]]
|
||||
|
||||
writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
|
||||
file.close()
|
||||
writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
|
||||
|
||||
|
||||
def cleanup():
|
||||
@ -129,10 +128,7 @@ def getVals(tech, module, var, freq=None, width=None):
|
||||
works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width
|
||||
"""
|
||||
|
||||
if width is not None:
|
||||
widthsToGet = width
|
||||
else:
|
||||
widthsToGet = widths
|
||||
widthsToGet = width if width is not None else widths
|
||||
|
||||
metric = []
|
||||
widthL = []
|
||||
@ -171,37 +167,30 @@ def csvOfBest(filename):
|
||||
m = np.Inf # large number to start
|
||||
best = None
|
||||
for oneSynth in allSynths: # best achievable, rightmost green
|
||||
if (
|
||||
(oneSynth.width == w)
|
||||
& (oneSynth.tech == tech)
|
||||
& (oneSynth.module == mod)
|
||||
):
|
||||
if (oneSynth.delay < m) & (
|
||||
1000 / oneSynth.delay > oneSynth.freq
|
||||
):
|
||||
if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod):
|
||||
if (oneSynth.delay < m) & (1000 / oneSynth.delay > oneSynth.freq):
|
||||
m = oneSynth.delay
|
||||
best = oneSynth
|
||||
|
||||
if (best is not None) & (best not in bestSynths):
|
||||
bestSynths += [best]
|
||||
|
||||
file = open(filename, "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Module",
|
||||
"Tech",
|
||||
"Width",
|
||||
"Target Freq",
|
||||
"Delay",
|
||||
"Area",
|
||||
"L Power (nW)",
|
||||
"D energy (nJ)",
|
||||
]
|
||||
)
|
||||
for synth in bestSynths:
|
||||
writer.writerow(list(synth))
|
||||
file.close()
|
||||
with open(filename, "w") as file:
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Module",
|
||||
"Tech",
|
||||
"Width",
|
||||
"Target Freq",
|
||||
"Delay",
|
||||
"Area",
|
||||
"L Power (nW)",
|
||||
"D energy (nJ)",
|
||||
]
|
||||
)
|
||||
for synth in bestSynths:
|
||||
writer.writerow(list(synth))
|
||||
return bestSynths
|
||||
|
||||
|
||||
@ -229,7 +218,7 @@ def genLegend(fits, coefs, r2=None, spec=None, ale=False):
|
||||
eq = ""
|
||||
ind = 0
|
||||
|
||||
for k in eqDict.keys():
|
||||
for k in eqDict:
|
||||
if k in fits:
|
||||
if str(coefsr[ind]) != "0":
|
||||
eq += " + " + coefsr[ind] + eqDict[k]
|
||||
@ -277,10 +266,7 @@ def oneMetricPlot(
|
||||
modFit = fitDict[module]
|
||||
fits = modFit[ale]
|
||||
|
||||
if freq:
|
||||
ls = "--"
|
||||
else:
|
||||
ls = "-"
|
||||
ls = "--" if freq else "-"
|
||||
|
||||
for spec in techSpecs:
|
||||
# print(f"Searching for module of spec {spec} and module {module} and var {var}")
|
||||
@ -403,72 +389,16 @@ def makeCoefTable():
|
||||
"""writes CSV with each line containing the coefficients for a regression fit
|
||||
to a particular combination of module, metric (including both techs, normalized)
|
||||
"""
|
||||
file = open("ppaFitting.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
["Module", "Metric", "Target", "1", "N", "N^2", "log2(N)", "Nlog2(N)", "R^2"]
|
||||
)
|
||||
with open("ppaFitting.csv", "w") as file:
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
["Module", "Metric", "Target", "1", "N", "N^2", "log2(N)", "Nlog2(N)", "R^2"]
|
||||
)
|
||||
|
||||
for module in modules:
|
||||
for freq in [10, None]:
|
||||
target = "easy" if freq else "hard"
|
||||
for var in ["delay", "area", "lpower", "denergy"]:
|
||||
ale = var != "delay"
|
||||
metL = []
|
||||
modFit = fitDict[module]
|
||||
fits = modFit[ale]
|
||||
|
||||
for spec in techSpecs:
|
||||
metric = getVals(spec.tech, module, var, freq=freq)
|
||||
techdict = spec._asdict()
|
||||
norm = techdict[var]
|
||||
metL += [m / norm for m in metric]
|
||||
|
||||
xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
|
||||
coefs = np.ndarray.tolist(coefs)
|
||||
coefsToWrite = [None] * 5
|
||||
fitTerms = "clsgn"
|
||||
ind = 0
|
||||
for i in range(len(fitTerms)):
|
||||
if fitTerms[i] in fits:
|
||||
coefsToWrite[i] = coefs[ind]
|
||||
ind += 1
|
||||
row = [module, var, target] + coefsToWrite + [r2]
|
||||
writer.writerow(row)
|
||||
|
||||
file.close()
|
||||
|
||||
|
||||
def sigfig(num, figs):
|
||||
return "{:g}".format(float("{:.{p}g}".format(num, p=figs)))
|
||||
|
||||
|
||||
def makeEqTable():
|
||||
"""writes CSV with each line containing the equations for fits for each metric
|
||||
to a particular module (including both techs, normalized)
|
||||
"""
|
||||
file = open("ppaEquations.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Element",
|
||||
"Best delay",
|
||||
"Fast area",
|
||||
"Fast leakage",
|
||||
"Fast energy",
|
||||
"Small area",
|
||||
"Small leakage",
|
||||
"Small energy",
|
||||
]
|
||||
)
|
||||
|
||||
for module in modules:
|
||||
eqs = []
|
||||
for freq in [None, 10]:
|
||||
for var in ["delay", "area", "lpower", "denergy"]:
|
||||
if (var == "delay") and (freq == 10):
|
||||
pass
|
||||
else:
|
||||
for module in modules:
|
||||
for freq in [10, None]:
|
||||
target = "easy" if freq else "hard"
|
||||
for var in ["delay", "area", "lpower", "denergy"]:
|
||||
ale = var != "delay"
|
||||
metL = []
|
||||
modFit = fitDict[module]
|
||||
@ -482,12 +412,63 @@ def makeEqTable():
|
||||
|
||||
xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
|
||||
coefs = np.ndarray.tolist(coefs)
|
||||
eqs += [genLegend(fits, coefs, ale=ale)]
|
||||
row = [module] + eqs
|
||||
writer.writerow(row)
|
||||
coefsToWrite = [None] * 5
|
||||
fitTerms = "clsgn"
|
||||
ind = 0
|
||||
for i in range(len(fitTerms)):
|
||||
if fitTerms[i] in fits:
|
||||
coefsToWrite[i] = coefs[ind]
|
||||
ind += 1
|
||||
row = [module, var, target] + coefsToWrite + [r2]
|
||||
writer.writerow(row)
|
||||
|
||||
file.close()
|
||||
|
||||
def sigfig(num, figs):
|
||||
return "{:g}".format(float("{:.{p}g}".format(num, p=figs)))
|
||||
|
||||
|
||||
def makeEqTable():
|
||||
"""writes CSV with each line containing the equations for fits for each metric
|
||||
to a particular module (including both techs, normalized)
|
||||
"""
|
||||
with open("ppaEquations.csv", "w") as file:
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(
|
||||
[
|
||||
"Element",
|
||||
"Best delay",
|
||||
"Fast area",
|
||||
"Fast leakage",
|
||||
"Fast energy",
|
||||
"Small area",
|
||||
"Small leakage",
|
||||
"Small energy",
|
||||
]
|
||||
)
|
||||
|
||||
for module in modules:
|
||||
eqs = []
|
||||
for freq in [None, 10]:
|
||||
for var in ["delay", "area", "lpower", "denergy"]:
|
||||
if (var == "delay") and (freq == 10):
|
||||
pass
|
||||
else:
|
||||
ale = var != "delay"
|
||||
metL = []
|
||||
modFit = fitDict[module]
|
||||
fits = modFit[ale]
|
||||
|
||||
for spec in techSpecs:
|
||||
metric = getVals(spec.tech, module, var, freq=freq)
|
||||
techdict = spec._asdict()
|
||||
norm = techdict[var]
|
||||
metL += [m / norm for m in metric]
|
||||
|
||||
xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
|
||||
coefs = np.ndarray.tolist(coefs)
|
||||
eqs += [genLegend(fits, coefs, ale=ale)]
|
||||
row = [module] + eqs
|
||||
writer.writerow(row)
|
||||
|
||||
def genFuncs(fits="clsgn"):
|
||||
"""helper function for regress()
|
||||
@ -819,10 +800,7 @@ def stdDevError():
|
||||
norm = techdict[var]
|
||||
metL += [m / norm for m in metric]
|
||||
|
||||
if ale:
|
||||
ws = [w / normAddWidth for w in widths]
|
||||
else:
|
||||
ws = widths
|
||||
ws = [w / normAddWidth for w in widths] if ale else widths
|
||||
ws = ws * 2
|
||||
mat = []
|
||||
for w in ws:
|
||||
@ -896,7 +874,7 @@ if __name__ == "__main__":
|
||||
"flop": ["c", "l", "l"],
|
||||
"binencoder": ["cg", "l", "l"],
|
||||
}
|
||||
fitDict.update(dict.fromkeys(["mux2", "mux4", "mux8"], ["cg", "l", "l"]))
|
||||
fitDict.update({key: ["cg", "l", "l"] for key in ["mux2", "mux4", "mux8"]})
|
||||
|
||||
TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
|
||||
# FO4 delay information information
|
||||
|
||||
@ -21,53 +21,46 @@ args=parser.parse_args()
|
||||
|
||||
fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0]
|
||||
|
||||
fin = open(fin_path)
|
||||
with open(fin_path) as fin:
|
||||
lines = fin.readlines()
|
||||
|
||||
lines = fin.readlines()
|
||||
# keeps track of what line number the module header begins
|
||||
lineModuleStart = 0
|
||||
|
||||
# keeps track of what line number the module header begins
|
||||
lineModuleStart = 0
|
||||
# keeps track of what line number the module header ends
|
||||
lineModuleEnd = 0
|
||||
|
||||
# keeps track of what line number the module header ends
|
||||
lineModuleEnd = 0
|
||||
# keeps track of module name
|
||||
moduleName = ""
|
||||
|
||||
# keeps track of module name
|
||||
moduleName = ""
|
||||
# string that will keep track of the running module header
|
||||
buf = 'import cvw::*;\n`include "config.vh"\n`include "parameter-defs.vh"\n'
|
||||
|
||||
# string that will keep track of the running module header
|
||||
buf = "import cvw::*;\n`include \"config.vh\"\n`include \"parameter-defs.vh\"\n"
|
||||
# are we writing into the buffer
|
||||
writeBuf=False
|
||||
|
||||
# are we writing into the buffer
|
||||
writeBuf=False
|
||||
index=0
|
||||
|
||||
index=0
|
||||
# string copy logic
|
||||
for l in lines:
|
||||
if l.lstrip().find("module") == 0:
|
||||
lineModuleStart = index
|
||||
moduleName = l.split()[1]
|
||||
writeBuf = True
|
||||
buf += f"module {moduleName}wrapper (\n"
|
||||
continue
|
||||
if (writeBuf):
|
||||
buf += l
|
||||
if l.lstrip().find (");") == 0:
|
||||
lineModuleEnd = index
|
||||
break
|
||||
index+=1
|
||||
|
||||
# string copy logic
|
||||
for l in lines:
|
||||
if l.lstrip().find("module") == 0:
|
||||
lineModuleStart = index
|
||||
moduleName = l.split()[1]
|
||||
writeBuf = True
|
||||
buf += f"module {moduleName}wrapper (\n"
|
||||
continue
|
||||
if (writeBuf):
|
||||
buf += l
|
||||
if l.lstrip().find (");") == 0:
|
||||
lineModuleEnd = index
|
||||
break
|
||||
index+=1
|
||||
# post-processing buffer: add DUT and endmodule lines
|
||||
buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
|
||||
|
||||
# post-processing buffer: add DUT and endmodule lines
|
||||
buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
|
||||
# path to wrapper
|
||||
wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
|
||||
|
||||
# path to wrapper
|
||||
wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
|
||||
|
||||
fout = open(wrapperPath, "w")
|
||||
|
||||
fout.write(buf)
|
||||
|
||||
fin.close()
|
||||
fout.close()
|
||||
|
||||
#print(buf)
|
||||
with open(wrapperPath, "w") as fout:
|
||||
fout.write(buf)
|
||||
|
||||
@ -7,10 +7,7 @@ import argparse
|
||||
|
||||
def runSynth(config, mod, tech, freq, maxopt, usesram):
|
||||
global pool
|
||||
if (usesram):
|
||||
prefix = "syn_sram_"
|
||||
else:
|
||||
prefix = "syn_"
|
||||
prefix = "syn_sram_" if usesram else "syn_"
|
||||
cfg = prefix + config
|
||||
command = f"make synth DESIGN=wallypipelinedcore CONFIG={cfg} MOD={mod} TECH={tech} DRIVE=FLOP FREQ={freq} MAXOPT={maxopt} USESRAM={usesram} MAXCORES=1"
|
||||
pool.map(mask, [command])
|
||||
|
||||
@ -6,8 +6,9 @@ import fileinput
|
||||
address = 0
|
||||
|
||||
|
||||
for line in fileinput.input('-'):
|
||||
# the 14- is to reverse the byte order to little endian
|
||||
formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
|
||||
sys.stdout.write(f'@{address:08x} {formatedLine:s}\n')
|
||||
address+=8
|
||||
with fileinput.input('-') as f:
|
||||
for line in f:
|
||||
# the 14- is to reverse the byte order to little endian
|
||||
formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
|
||||
sys.stdout.write(f'@{address:08x} {formatedLine:s}\n')
|
||||
address+=8
|
||||
|
||||
@ -40,9 +40,9 @@ mem_addr = mem_start_addr
|
||||
|
||||
def wl(line="", comment=None, fname=test_name):
|
||||
with open(fname, "a") as f:
|
||||
instr = False if (":" in line or
|
||||
".align" in line or
|
||||
"# include" in line) else True
|
||||
instr = not (":" in line or
|
||||
".align" in line or
|
||||
"# include" in line)
|
||||
indent = 6 if instr else 0
|
||||
comment = "// " + comment if comment is not None else ""
|
||||
to_write = " " * indent + line + comment + "\n"
|
||||
|
||||
@ -76,218 +76,212 @@ def create_vectors(my_config):
|
||||
operation = my_config.op_code
|
||||
rounding_mode = "X"
|
||||
flags = "XX"
|
||||
# use name to create our new tv
|
||||
dest_file = open(f"{dest_dir}cvw_{my_config.bits}_{vector1[:-2]}.tv", 'w')
|
||||
# open vectors
|
||||
src_file1 = open(source_dir1 + vector1)
|
||||
src_file2 = open(source_dir2 + vector2)
|
||||
# for each test in the vector
|
||||
reading = True
|
||||
src_file2.readline() #skip first bc junk
|
||||
# print(my_config.bits, my_config.letter)
|
||||
if my_config.letter == "F" and my_config.bits == 64:
|
||||
# use name to create our new tv and open vectors
|
||||
with open(f"{dest_dir}cvw_{my_config.bits}_{vector1[:-2]}.tv", 'w') as dest_file, open(source_dir1 + vector1) as src_file1, open(source_dir2 + vector2) as src_file2:
|
||||
# for each test in the vector
|
||||
reading = True
|
||||
# print("trigger 64F")
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
# answers are before deadbeef (first line of 4)
|
||||
# flags are after deadbeef (third line of 4)
|
||||
answer = src_file2.readline().strip()
|
||||
deadbeef = src_file2.readline().strip()
|
||||
# print(answer)
|
||||
if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
|
||||
# get flags
|
||||
packed = src_file2.readline().strip()[6:]
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
# skip 00000000 buffer
|
||||
src_file2.readline()
|
||||
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
else:
|
||||
op2val = 32*"X"
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 64:
|
||||
reading = True
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer2 = src_file2.readline().strip()
|
||||
answer1 = src_file2.readline().strip()
|
||||
answer = answer1 + answer2
|
||||
#print(answer1,answer2)
|
||||
if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 32:
|
||||
reading = True
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer = src_file2.readline().strip()
|
||||
# print(f"Answer: {answer}")
|
||||
#print(answer1,answer2)
|
||||
if not (answer == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
else:
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
answer = src_file2.readline()
|
||||
#print(answer)
|
||||
packed = src_file2.readline()[6:]
|
||||
#print("Packed: ", packed)
|
||||
if len(packed.strip())>0: # if there is still stuff to read
|
||||
# print("packed")
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# rounding mode for float
|
||||
if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
|
||||
src_file2.readline() #skip first bc junk
|
||||
# print(my_config.bits, my_config.letter)
|
||||
if my_config.letter == "F" and my_config.bits == 64:
|
||||
reading = True
|
||||
# print("trigger 64F")
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
# answers are before deadbeef (first line of 4)
|
||||
# flags are after deadbeef (third line of 4)
|
||||
answer = src_file2.readline().strip()
|
||||
deadbeef = src_file2.readline().strip()
|
||||
# print(answer)
|
||||
if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
|
||||
# get flags
|
||||
packed = src_file2.readline().strip()[6:]
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
# print("out")
|
||||
dest_file.close()
|
||||
src_file1.close()
|
||||
src_file2.close()
|
||||
# skip 00000000 buffer
|
||||
src_file2.readline()
|
||||
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
else:
|
||||
op2val = 32*"X"
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 64:
|
||||
reading = True
|
||||
#skip first 2 lines bc junk
|
||||
src_file2.readline()
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer2 = src_file2.readline().strip()
|
||||
answer1 = src_file2.readline().strip()
|
||||
answer = answer1 + answer2
|
||||
#print(answer1,answer2)
|
||||
if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 32:
|
||||
reading = True
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer = src_file2.readline().strip()
|
||||
# print(f"Answer: {answer}")
|
||||
#print(answer1,answer2)
|
||||
if answer != '6f5ca309': # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
else:
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
answer = src_file2.readline()
|
||||
#print(answer)
|
||||
packed = src_file2.readline()[6:]
|
||||
#print("Packed: ", packed)
|
||||
if len(packed.strip())>0: # if there is still stuff to read
|
||||
# print("packed")
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
|
||||
# handle special case where destination register is hardwired to zero
|
||||
if "dest:x0" in line:
|
||||
answer = "x" * len(answer)
|
||||
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# rounding mode for float
|
||||
if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
# print("out")
|
||||
|
||||
config_list = [
|
||||
Config(32, "M", "div", "div-", 0),
|
||||
|
||||
@ -39,19 +39,15 @@ for vector in div_vectors:
|
||||
config_list = vector.split(".")[0].split("_")
|
||||
operation = "1" #float div
|
||||
rounding_mode = round_dict[str(config_list[2])]
|
||||
# use name to create our new tv
|
||||
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||
# open vector
|
||||
src_file = open(source_dir + vector)
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = f"{operation}_{ext_bits(input_1)}_{ext_bits(input_2)}_{ext_bits(answer)}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
dest_file.close()
|
||||
src_file.close()
|
||||
# use name to create our new tv and open vector
|
||||
with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = f"{operation}_{ext_bits(input_1)}_{ext_bits(input_2)}_{ext_bits(answer)}_{flags.strip()}_{rounding_mode}"
|
||||
dest_file.write(translation + "\n")
|
||||
|
||||
|
||||
print("creating testfloat sqrt test vectors")
|
||||
@ -64,16 +60,12 @@ for vector in sqrt_vectors:
|
||||
config_list = vector.split(".")[0].split("_")
|
||||
operation = "2" #sqrt
|
||||
rounding_mode = round_dict[str(config_list[2])]
|
||||
# use name to create our new tv
|
||||
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||
# open vector
|
||||
src_file = open(source_dir + vector)
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
dest_file.close()
|
||||
src_file.close()
|
||||
# use name to create our new tv and open vector
|
||||
with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
|
||||
# for each test in the vector
|
||||
for i in src_file.readlines():
|
||||
translation = "" # this stores the test that we are currently working on
|
||||
[input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||
# put it all together, strip nec for removing \n on the end of the flags
|
||||
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
|
||||
dest_file.write(translation + "\n")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user