diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py
index 8cfce025d..9a2bb48d9 100755
--- a/benchmarks/coremark/coremark_sweep.py
+++ b/benchmarks/coremark/coremark_sweep.py
@@ -65,10 +65,7 @@ with open(resultfile, mode='w', newline='') as csvfile:
# Loop through each architecture and run the make commands
for arch in arch_list:
- if(str in arch):
- xlen_value='32'
- else:
- xlen_value='64'
+ xlen_value = "32" if str in arch else "64"
os.system("make clean")
make_all = f"make all XLEN={xlen_value} ARCH={arch}"
os.system(make_all)
diff --git a/benchmarks/embench/embench_arch_sweep.py b/benchmarks/embench/embench_arch_sweep.py
index 5b76ea219..20c0c800e 100755
--- a/benchmarks/embench/embench_arch_sweep.py
+++ b/benchmarks/embench/embench_arch_sweep.py
@@ -30,12 +30,8 @@ def tabulate_arch_sweep(directory):
file = case+"_"+arch+".json"
file_path = os.path.join(directory, file)
lines = []
- try:
- f = open(file_path)
+ with open(file_path) as f:
lines = f.readlines()
- except:
- f.close()
- #print(file_path+" does not exist")
for line in lines:
#print("File: "+file+" Line: "+line)
#p = re.compile('".*" : .*,')
diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py
index 59f05944d..9501f09ec 100755
--- a/benchmarks/graphGen.py
+++ b/benchmarks/graphGen.py
@@ -16,7 +16,7 @@ def loadCoremark():
keywordlist = ["CoreMark 1.0", "CoreMark Size", "MTIME", "MINSTRET", "Branches Miss Predictions", "BTB Misses"]
for keyword in keywordlist:
- bashInst = "cat " + coremarkPath + " | grep \"" + keyword + "\" | cut -d \':\' -f 2 | cut -d \" \" -f 2 | tail -1"
+ bashInst = "cat " + coremarkPath + ' | grep "' + keyword + "\" | cut -d ':' -f 2 | cut -d \" \" -f 2 | tail -1"
result = subprocess.run(bashInst, stdout=subprocess.PIPE, shell=True)
if (debug): print(result)
coremarkData[keyword] = int(result.stdout)
@@ -25,8 +25,8 @@ def loadCoremark():
def loadEmbench(embenchPath, embenchData):
"""loads the embench data dictionary"""
- f = open(embenchPath)
- embenchData = json.load(f)
+ with open(embenchPath) as f:
+ embenchData = json.load(f)
if (debug): print(embenchData)
return embenchData
diff --git a/bin/CacheSim.py b/bin/CacheSim.py
index 5f00d29a0..f95c1ed03 100755
--- a/bin/CacheSim.py
+++ b/bin/CacheSim.py
@@ -284,7 +284,7 @@ def main(args):
elif lninfo[1] == 'A':
atoms += 1
- if not result == lninfo[2]:
+ if result != lninfo[2]:
print(f"Result mismatch at address {lninfo[0]}. Wally: {lninfo[2]}, Sim: {result}")
mismatches += 1
if args.dist:
diff --git a/bin/nightly_build.py b/bin/nightly_build.py
index 510c24ab7..00360e80d 100755
--- a/bin/nightly_build.py
+++ b/bin/nightly_build.py
@@ -473,7 +473,7 @@ class TestRunner:
if failed_configs:
md_file.write("## Failed Configurations\n\n")
for config, log_file in failed_configs:
- md_file.write(f"- {config} ({log_file})\n")
+ md_file.write(f'- {config} ({log_file})\n')
md_file.write("\n")
else:
md_file.write("## Failed Configurations\n")
@@ -481,7 +481,7 @@ class TestRunner:
md_file.write("\n## Passed Configurations\n")
for config in passed_configs:
- md_file.write(f"- {config}\n")
+ md_file.write(f'- {config}\n')
self.logger.info("writing test outputs to markdown")
@@ -526,7 +526,7 @@ class TestRunner:
md_file.write("\n")
except subprocess.CalledProcessError as e:
# Handle if the command fails
- md_file.write(f"Failed to identify host and Operating System information: {str(e)}")
+ md_file.write(f"Failed to identify host and Operating System information: {e!s}")
# Which tests did we run
md_file.write(f"\n**Tests made:** `make {test_type}`\n")
@@ -548,7 +548,7 @@ class TestRunner:
if len(item) == 0:
md_file.write("\n")
- md_file.write("* No failures\n")
+ md_file.write('* No failures\n')
md_file.write("\n")
else:
for failed_test in item:
@@ -556,7 +556,7 @@ class TestRunner:
log_file = failed_test[1]
md_file.write("\n")
- md_file.write(f"* {config} ({log_file})\n")
+ md_file.write(f'* {config} ({log_file})\n')
md_file.write("\n")
# Successful Tests
@@ -571,14 +571,14 @@ class TestRunner:
if len(item) == 0:
md_file.write("\n")
- md_file.write("* No successes\n")
+ md_file.write('* No successes\n')
md_file.write("\n")
else:
for passed_tests in item:
config = passed_tests
md_file.write("\n")
- md_file.write(f"* {config}\n")
+ md_file.write(f'* {config}\n')
md_file.write("\n")
self.logger.info("Combining markdown files")
@@ -800,7 +800,7 @@ def main():
logger.info(f"The total failures for all tests ran are: {total_number_failures}")
# Copy actual test logs from sim/questa, sim/verilator, sim/vcs
- if not args.tests == "test_lint":
+ if args.tests != 'test_lint':
test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"])
#############################################
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 912b288b9..ff704c71b 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -46,14 +46,14 @@ def ParseBranchListFile(path):
is formated in row columns. Each row is a trace with the file, branch predictor type, and the parameters.
parameters can be any number and depend on the predictor type. Returns a list of lists.'''
lst = []
- BranchList = open(path)
- for line in BranchList:
- tokens = line.split()
- predictorLog = os.path.dirname(path) + '/' + tokens[0]
- predictorType = tokens[1]
- predictorParams = tokens[2::]
- lst.append([predictorLog, predictorType, predictorParams])
- #print(predictorLog, predictorType, predictorParams)
+ with open(path) as BranchList:
+ for line in BranchList:
+ tokens = line.split()
+ predictorLog = os.path.dirname(path) + '/' + tokens[0]
+ predictorType = tokens[1]
+ predictorParams = tokens[2::]
+ lst.append([predictorLog, predictorType, predictorParams])
+ #print(predictorLog, predictorType, predictorParams)
return lst
def ProcessFile(fileName):
@@ -62,22 +62,22 @@ def ProcessFile(fileName):
# 1 find lines with Read memfile and extract test name
# 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
benchmarks = []
- transcript = open(fileName)
HPMClist = { }
testName = ''
- for line in transcript.readlines():
- lineToken = line.split()
- if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
- opt = lineToken[3].split('/')[-4]
- testName = lineToken[3].split('/')[-1].split('.')[0]
- HPMClist = { }
- elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
- countToken = line.split('=')[1].split()
- value = int(countToken[0]) if countToken[0] != 'x' else 0
- name = ' '.join(countToken[1:])
- HPMClist[name] = value
- elif ('is done' in line):
- benchmarks.append((testName, opt, HPMClist))
+ with open(fileName) as transcript:
+ for line in transcript.readlines():
+ lineToken = line.split()
+ if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
+ opt = lineToken[3].split('/')[-4]
+ testName = lineToken[3].split('/')[-1].split('.')[0]
+ HPMClist = { }
+ elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
+ countToken = line.split('=')[1].split()
+ value = int(countToken[0]) if countToken[0] != 'x' else 0
+ name = ' '.join(countToken[1:])
+ HPMClist[name] = value
+ elif ('is done' in line):
+ benchmarks.append((testName, opt, HPMClist))
return benchmarks
diff --git a/bin/regression-wally b/bin/regression-wally
index 6561ff7b0..86dee5382 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -268,21 +268,12 @@ def addTests(tests, sim):
for test in tests:
config = test[0]
suites = test[1]
- if len(test) >= 3:
- args = f" --args {test[2]}"
- else:
- args = ""
- if len(test) >= 4:
- gs = test[3]
- else:
- gs = "All tests ran without failures"
+ args = f" --args {test[2]}" if len(test) >= 3 else ""
+ gs = test[3] if len(test) >= 4 else "All tests ran without failures"
cmdPrefix=f"wsim --sim {sim} {coverStr} {config}"
for t in suites:
sim_log = f"{sim_logdir}{config}_{t}.log"
- if len(test) >= 5:
- grepfile = sim_logdir + test[4]
- else:
- grepfile = sim_log
+ grepfile = sim_logdir + test[4] if len(test) >= 5 else sim_log
tc = TestCase(
name=t,
variant=config,
@@ -535,9 +526,7 @@ def main():
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
elif args.buildroot:
TIMEOUT_DUR = 60*1440 # 1 day
- elif args.testfloat:
- TIMEOUT_DUR = 30*60 # seconds
- elif args.nightly:
+ elif args.testfloat or args.nightly:
TIMEOUT_DUR = 30*60 # seconds
else:
TIMEOUT_DUR = 10*60 # seconds
@@ -545,10 +534,7 @@ def main():
# Scale the number of concurrent processes to the number of test cases, but
# max out at a limited number of concurrent processes to not overwhelm the system
# right now fcov, ccov, nightly all use Imperas
- if (args.ccov or args.fcov or args.nightly):
- ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses
- else:
- ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests
+ ImperasDVLicenseCount = 16 if args.ccov or args.fcov or args.nightly else 10000
with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
num_fail = 0
results = {}
diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py
index 9de361237..1151e6305 100755
--- a/sim/rv64gc_CacheSim.py
+++ b/sim/rv64gc_CacheSim.py
@@ -67,8 +67,8 @@ def main():
parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
args = parser.parse_args()
- simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1"
- testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"
+ simargs = "I_CACHE_ADDR_LOGGER=1\\'b1 D_CACHE_ADDR_LOGGER=1\\'b1"
+ testcmd = "wsim --sim " + args.sim + ' rv64gc {} --params "' + simargs + '" > /dev/null'
#cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose"
cachecmd = "CacheSim.py 64 4 56 44 -f {}"
mismatches = 0
diff --git a/sim/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py
index 029db0983..b202adacd 100755
--- a/sim/slack-notifier/slack-notifier.py
+++ b/sim/slack-notifier/slack-notifier.py
@@ -13,8 +13,8 @@ if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'):
print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier')
print('==============================================================')
else:
- urlFile = open(sys.path[0]+'/slack-webhook-url.txt')
- url = urlFile.readline().strip('\n')
+ with open(sys.path[0]+'/slack-webhook-url.txt') as urlFile:
+ url = urlFile.readline().strip('\n')
# Traverse 3 parents up the process tree
result = subprocess.check_output('ps -o ppid -p $PPID',shell=True)
@@ -25,7 +25,7 @@ else:
result = subprocess.check_output('ps -o cmd -p '+PPID3,shell=True)
cmdName = str(result).split('\\n')[1]
# Get current time
- timezone_offset = -8.0 # Pacific Standard Time (UTC−08:00)
+ timezone_offset = -8.0 # Pacific Standard Time (UTC-08:00)
tzinfo = timezone(timedelta(hours=timezone_offset))
time = datetime.now(tzinfo).strftime('%I:%M %p')
# Send message
diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs
index 3ab47cea9..7e9e8961f 100755
--- a/sim/vcs/run_vcs
+++ b/sim/vcs/run_vcs
@@ -24,7 +24,7 @@ def runFindCommand(cmd):
res = subprocess.check_output(cmd, shell=True, )
res = str(res)
res = res.replace("\\n", " ") # replace newline with space
- res = res.replace("\'", "") # strip off quotation marks
+ res = res.replace("'", "") # strip off quotation marks
res = res[1:] # strip off leading b from byte string
return res
@@ -81,13 +81,10 @@ def processArgs(wkdir, args):
def setupParamOverrides(wkdir, args):
paramOverrideFile = os.path.join(wkdir, "param_overrides.txt")
- with open(paramOverrideFile, "w", encoding="utf-8") as f:
+ with open(paramOverrideFile, "w") as f:
for param in args.params.split():
[param, value] = param.split("=")
- if r"\'" in value: # for bit values
- value = value.replace(r"\'", "'")
- else: # for strings
- value = f'"{value}"'
+ value = value.replace("\\'", "'") if "\\'" in value else f'"{value}"' # transform quotes/bit indicators
f.write(f"assign {value} {args.tb}/{param}\n")
return f" -parameters {wkdir}/param_overrides.txt "
diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index b31fe3225..9f2624391 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -27,48 +27,44 @@ def synthsintocsv():
specReg = re.compile('[a-zA-Z0-9]+')
metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
- file = open("Summary.csv", "w")
- writer = csv.writer(file)
- writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
+ with open("Summary.csv", "w") as file:
+ writer = csv.writer(file)
+ writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
- for oneSynth in allSynths:
- descrip = specReg.findall(oneSynth)
-# print("From " + oneSynth + " Find ")
-# for d in descrip:
-# print(d)
- if (descrip[3] == "sram"):
- base = 4
- else:
- base = 3
- width = descrip[base][:4]
- config = descrip[base][4:]
- if descrip[base+1][-2:] == 'nm':
- mod = ''
- else:
- mod = descrip[base+1]
- descrip = descrip[1:]
- tech = descrip[base+1][:-2]
- freq = descrip[base+2]
-# print(width, config, mod, tech, freq)
- metrics = []
- for phrase in ['Path Slack', 'Design Area']:
- bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
- bashCommand = bashCommand.format(phrase)
-# print(bashCommand)
- try:
- output = subprocess.check_output(['bash','-c', bashCommand])
- nums = metricReg.findall(str(output))
- nums = [float(m) for m in nums]
- metrics += nums
- except:
- print(width + config + tech + '_' + freq + " doesn't have reports")
- if metrics == []:
- pass
- else:
- delay = 1000/int(freq) - metrics[0]
- area = metrics[1]
- writer.writerow([width, config, mod, tech, freq, delay, area])
- file.close()
+ for oneSynth in allSynths:
+ descrip = specReg.findall(oneSynth)
+ # print("From " + oneSynth + " Find ")
+ # for d in descrip:
+ # print(d)
+ base = 4 if descrip[3] == "sram" else 3
+ width = descrip[base][:4]
+ config = descrip[base][4:]
+ if descrip[base+1][-2:] == 'nm':
+ mod = ''
+ else:
+ mod = descrip[base+1]
+ descrip = descrip[1:]
+ tech = descrip[base+1][:-2]
+ freq = descrip[base+2]
+ # print(width, config, mod, tech, freq)
+ metrics = []
+ for phrase in ['Path Slack', 'Design Area']:
+ bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
+ bashCommand = bashCommand.format(phrase)
+ # print(bashCommand)
+ try:
+ output = subprocess.check_output(['bash','-c', bashCommand])
+ nums = metricReg.findall(str(output))
+ nums = [float(m) for m in nums]
+ metrics += nums
+ except:
+ print(width + config + tech + '_' + freq + " doesn't have reports")
+ if metrics == []:
+ pass
+ else:
+ delay = 1000/int(freq) - metrics[0]
+ area = metrics[1]
+ writer.writerow([width, config, mod, tech, freq, delay, area])
def synthsfromcsv(filename):
@@ -93,7 +89,7 @@ def freqPlot(tech, width, config):
freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths:
- if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
+ if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & (oneSynth.mod == 'orig'):
ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period
freqsL[ind] += [oneSynth.freq]
delaysL[ind] += [oneSynth.delay]
@@ -101,10 +97,7 @@ def freqPlot(tech, width, config):
fig, (ax1, ax2) = plt.subplots(2, 1, sharex=True)
allFreqs = list(flatten(freqsL))
- if allFreqs != []:
- median = np.median(allFreqs)
- else:
- median = 0
+ median = np.median(allFreqs) if allFreqs != [] else 0
for ind in [0,1]:
areas = areasL[ind]
@@ -169,11 +162,10 @@ def plotFeatures(tech, width, config):
delays, areas, labels = ([] for i in range(3))
freq = techdict[tech].targfreq
for oneSynth in allSynths:
- if (tech == oneSynth.tech) & (freq == oneSynth.freq):
- if (oneSynth.config == config) & (width == oneSynth.width):
- delays += [oneSynth.delay]
- areas += [oneSynth.area]
- labels += [oneSynth.mod]
+ if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.config == config) & (width == oneSynth.width):
+ delays += [oneSynth.delay]
+ areas += [oneSynth.area]
+ labels += [oneSynth.mod]
if (delays == []):
print("No delays found for tech ", tech, " freq ", freq, ". Did you set --sky130freq, --sky90freq and --tsmcfreq?\n")
diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py
index ab2115734..4baa2f8be 100755
--- a/synthDC/ppa/ppaAnalyze.py
+++ b/synthDC/ppa/ppaAnalyze.py
@@ -50,49 +50,48 @@ def synthsintocsv():
specReg = re.compile("[a-zA-Z0-9]+")
metricReg = re.compile("-?\d+\.\d+[e]?[-+]?\d*")
- file = open("ppaData.csv", "w")
- writer = csv.writer(file)
- writer.writerow(
- [
- "Module",
- "Tech",
- "Width",
- "Target Freq",
- "Delay",
- "Area",
- "L Power (nW)",
- "D energy (nJ)",
- ]
- )
+ with open("ppaData.csv", "w") as file:
+ writer = csv.writer(file)
+ writer.writerow(
+ [
+ "Module",
+ "Tech",
+ "Width",
+ "Target Freq",
+ "Delay",
+ "Area",
+ "L Power (nW)",
+ "D energy (nJ)",
+ ]
+ )
- for oneSynth in allSynths:
- module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
- tech = tech[:-2]
- metrics = []
- for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
- bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
- bashCommand = bashCommand.format(*phrase)
- try:
- output = subprocess.check_output(["bash", "-c", bashCommand])
- except:
- print(module + width + tech + freq + " doesn't have reports")
- print("Consider running cleanup() first")
- nums = metricReg.findall(str(output))
- nums = [float(m) for m in nums]
- metrics += nums
- delay = 1000 / int(freq) - metrics[0]
- area = metrics[1]
- lpower = metrics[4]
- tpower = (metrics[2] + metrics[3] + metrics[4]*.000001)
- denergy = (
- (tpower) / int(freq) * 1000
- ) # (switching + internal powers)*delay, more practical units for regression coefs
+ for oneSynth in allSynths:
+ module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
+ tech = tech[:-2]
+ metrics = []
+ for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
+ bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
+ bashCommand = bashCommand.format(*phrase)
+ try:
+ output = subprocess.check_output(["bash", "-c", bashCommand])
+ except:
+ print(module + width + tech + freq + " doesn't have reports")
+ print("Consider running cleanup() first")
+ nums = metricReg.findall(str(output))
+ nums = [float(m) for m in nums]
+ metrics += nums
+ delay = 1000 / int(freq) - metrics[0]
+ area = metrics[1]
+ lpower = metrics[4]
+ tpower = (metrics[2] + metrics[3] + metrics[4]*.000001)
+ denergy = (
+ (tpower) / int(freq) * 1000
+ ) # (switching + internal powers)*delay, more practical units for regression coefs
- if "flop" in module: # since two flops in each module
- [area, lpower, denergy] = [n / 2 for n in [area, lpower, denergy]]
+ if "flop" in module: # since two flops in each module
+ [area, lpower, denergy] = [n / 2 for n in [area, lpower, denergy]]
- writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
- file.close()
+ writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
def cleanup():
@@ -129,10 +128,7 @@ def getVals(tech, module, var, freq=None, width=None):
works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width
"""
- if width is not None:
- widthsToGet = width
- else:
- widthsToGet = widths
+ widthsToGet = width if width is not None else widths
metric = []
widthL = []
@@ -171,37 +167,30 @@ def csvOfBest(filename):
m = np.Inf # large number to start
best = None
for oneSynth in allSynths: # best achievable, rightmost green
- if (
- (oneSynth.width == w)
- & (oneSynth.tech == tech)
- & (oneSynth.module == mod)
- ):
- if (oneSynth.delay < m) & (
- 1000 / oneSynth.delay > oneSynth.freq
- ):
+ if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod):
+ if (oneSynth.delay < m) & (1000 / oneSynth.delay > oneSynth.freq):
m = oneSynth.delay
best = oneSynth
if (best is not None) & (best not in bestSynths):
bestSynths += [best]
- file = open(filename, "w")
- writer = csv.writer(file)
- writer.writerow(
- [
- "Module",
- "Tech",
- "Width",
- "Target Freq",
- "Delay",
- "Area",
- "L Power (nW)",
- "D energy (nJ)",
- ]
- )
- for synth in bestSynths:
- writer.writerow(list(synth))
- file.close()
+ with open(filename, "w") as file:
+ writer = csv.writer(file)
+ writer.writerow(
+ [
+ "Module",
+ "Tech",
+ "Width",
+ "Target Freq",
+ "Delay",
+ "Area",
+ "L Power (nW)",
+ "D energy (nJ)",
+ ]
+ )
+ for synth in bestSynths:
+ writer.writerow(list(synth))
return bestSynths
@@ -229,7 +218,7 @@ def genLegend(fits, coefs, r2=None, spec=None, ale=False):
eq = ""
ind = 0
- for k in eqDict.keys():
+ for k in eqDict:
if k in fits:
if str(coefsr[ind]) != "0":
eq += " + " + coefsr[ind] + eqDict[k]
@@ -277,10 +266,7 @@ def oneMetricPlot(
modFit = fitDict[module]
fits = modFit[ale]
- if freq:
- ls = "--"
- else:
- ls = "-"
+ ls = "--" if freq else "-"
for spec in techSpecs:
# print(f"Searching for module of spec {spec} and module {module} and var {var}")
@@ -403,72 +389,16 @@ def makeCoefTable():
"""writes CSV with each line containing the coefficients for a regression fit
to a particular combination of module, metric (including both techs, normalized)
"""
- file = open("ppaFitting.csv", "w")
- writer = csv.writer(file)
- writer.writerow(
- ["Module", "Metric", "Target", "1", "N", "N^2", "log2(N)", "Nlog2(N)", "R^2"]
- )
+ with open("ppaFitting.csv", "w") as file:
+ writer = csv.writer(file)
+ writer.writerow(
+ ["Module", "Metric", "Target", "1", "N", "N^2", "log2(N)", "Nlog2(N)", "R^2"]
+ )
- for module in modules:
- for freq in [10, None]:
- target = "easy" if freq else "hard"
- for var in ["delay", "area", "lpower", "denergy"]:
- ale = var != "delay"
- metL = []
- modFit = fitDict[module]
- fits = modFit[ale]
-
- for spec in techSpecs:
- metric = getVals(spec.tech, module, var, freq=freq)
- techdict = spec._asdict()
- norm = techdict[var]
- metL += [m / norm for m in metric]
-
- xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
- coefs = np.ndarray.tolist(coefs)
- coefsToWrite = [None] * 5
- fitTerms = "clsgn"
- ind = 0
- for i in range(len(fitTerms)):
- if fitTerms[i] in fits:
- coefsToWrite[i] = coefs[ind]
- ind += 1
- row = [module, var, target] + coefsToWrite + [r2]
- writer.writerow(row)
-
- file.close()
-
-
-def sigfig(num, figs):
- return "{:g}".format(float("{:.{p}g}".format(num, p=figs)))
-
-
-def makeEqTable():
- """writes CSV with each line containing the equations for fits for each metric
- to a particular module (including both techs, normalized)
- """
- file = open("ppaEquations.csv", "w")
- writer = csv.writer(file)
- writer.writerow(
- [
- "Element",
- "Best delay",
- "Fast area",
- "Fast leakage",
- "Fast energy",
- "Small area",
- "Small leakage",
- "Small energy",
- ]
- )
-
- for module in modules:
- eqs = []
- for freq in [None, 10]:
- for var in ["delay", "area", "lpower", "denergy"]:
- if (var == "delay") and (freq == 10):
- pass
- else:
+ for module in modules:
+ for freq in [10, None]:
+ target = "easy" if freq else "hard"
+ for var in ["delay", "area", "lpower", "denergy"]:
ale = var != "delay"
metL = []
modFit = fitDict[module]
@@ -482,12 +412,63 @@ def makeEqTable():
xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
coefs = np.ndarray.tolist(coefs)
- eqs += [genLegend(fits, coefs, ale=ale)]
- row = [module] + eqs
- writer.writerow(row)
+ coefsToWrite = [None] * 5
+ fitTerms = "clsgn"
+ ind = 0
+ for i in range(len(fitTerms)):
+ if fitTerms[i] in fits:
+ coefsToWrite[i] = coefs[ind]
+ ind += 1
+ row = [module, var, target] + coefsToWrite + [r2]
+ writer.writerow(row)
- file.close()
+def sigfig(num, figs):
+ return "{:g}".format(float("{:.{p}g}".format(num, p=figs)))
+
+
+def makeEqTable():
+ """writes CSV with each line containing the equations for fits for each metric
+ to a particular module (including both techs, normalized)
+ """
+ with open("ppaEquations.csv", "w") as file:
+ writer = csv.writer(file)
+ writer.writerow(
+ [
+ "Element",
+ "Best delay",
+ "Fast area",
+ "Fast leakage",
+ "Fast energy",
+ "Small area",
+ "Small leakage",
+ "Small energy",
+ ]
+ )
+
+ for module in modules:
+ eqs = []
+ for freq in [None, 10]:
+ for var in ["delay", "area", "lpower", "denergy"]:
+ if (var == "delay") and (freq == 10):
+ pass
+ else:
+ ale = var != "delay"
+ metL = []
+ modFit = fitDict[module]
+ fits = modFit[ale]
+
+ for spec in techSpecs:
+ metric = getVals(spec.tech, module, var, freq=freq)
+ techdict = spec._asdict()
+ norm = techdict[var]
+ metL += [m / norm for m in metric]
+
+ xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
+ coefs = np.ndarray.tolist(coefs)
+ eqs += [genLegend(fits, coefs, ale=ale)]
+ row = [module] + eqs
+ writer.writerow(row)
def genFuncs(fits="clsgn"):
"""helper function for regress()
@@ -819,10 +800,7 @@ def stdDevError():
norm = techdict[var]
metL += [m / norm for m in metric]
- if ale:
- ws = [w / normAddWidth for w in widths]
- else:
- ws = widths
+ ws = [w / normAddWidth for w in widths] if ale else widths
ws = ws * 2
mat = []
for w in ws:
@@ -896,7 +874,7 @@ if __name__ == "__main__":
"flop": ["c", "l", "l"],
"binencoder": ["cg", "l", "l"],
}
- fitDict.update(dict.fromkeys(["mux2", "mux4", "mux8"], ["cg", "l", "l"]))
+ fitDict.update({key: ["cg", "l", "l"] for key in ["mux2", "mux4", "mux8"]})
TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
# FO4 delay information information
diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py
index 862c1abbd..7cc406369 100755
--- a/synthDC/scripts/wrapperGen.py
+++ b/synthDC/scripts/wrapperGen.py
@@ -21,53 +21,46 @@ args=parser.parse_args()
fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0]
-fin = open(fin_path)
+with open(fin_path) as fin:
+ lines = fin.readlines()
-lines = fin.readlines()
+ # keeps track of what line number the module header begins
+ lineModuleStart = 0
-# keeps track of what line number the module header begins
-lineModuleStart = 0
+ # keeps track of what line number the module header ends
+ lineModuleEnd = 0
-# keeps track of what line number the module header ends
-lineModuleEnd = 0
+ # keeps track of module name
+ moduleName = ""
-# keeps track of module name
-moduleName = ""
+ # string that will keep track of the running module header
+ buf = 'import cvw::*;\n`include "config.vh"\n`include "parameter-defs.vh"\n'
-# string that will keep track of the running module header
-buf = "import cvw::*;\n`include \"config.vh\"\n`include \"parameter-defs.vh\"\n"
+ # are we writing into the buffer
+ writeBuf=False
-# are we writing into the buffer
-writeBuf=False
+ index=0
-index=0
+ # string copy logic
+ for l in lines:
+ if l.lstrip().find("module") == 0:
+ lineModuleStart = index
+ moduleName = l.split()[1]
+ writeBuf = True
+ buf += f"module {moduleName}wrapper (\n"
+ continue
+ if (writeBuf):
+ buf += l
+ if l.lstrip().find (");") == 0:
+ lineModuleEnd = index
+ break
+ index+=1
-# string copy logic
-for l in lines:
- if l.lstrip().find("module") == 0:
- lineModuleStart = index
- moduleName = l.split()[1]
- writeBuf = True
- buf += f"module {moduleName}wrapper (\n"
- continue
- if (writeBuf):
- buf += l
- if l.lstrip().find (");") == 0:
- lineModuleEnd = index
- break
- index+=1
+ # post-processing buffer: add DUT and endmodule lines
+ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
-# post-processing buffer: add DUT and endmodule lines
-buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
+ # path to wrapper
+ wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
-# path to wrapper
-wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
-
-fout = open(wrapperPath, "w")
-
-fout.write(buf)
-
-fin.close()
-fout.close()
-
-#print(buf)
+ with open(wrapperPath, "w") as fout:
+ fout.write(buf)
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index d4b0387e5..350064a0d 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -7,10 +7,7 @@ import argparse
def runSynth(config, mod, tech, freq, maxopt, usesram):
global pool
- if (usesram):
- prefix = "syn_sram_"
- else:
- prefix = "syn_"
+ prefix = "syn_sram_" if usesram else "syn_"
cfg = prefix + config
command = f"make synth DESIGN=wallypipelinedcore CONFIG={cfg} MOD={mod} TECH={tech} DRIVE=FLOP FREQ={freq} MAXOPT={maxopt} USESRAM={usesram} MAXCORES=1"
pool.map(mask, [command])
diff --git a/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py
index 330c8646f..6a6be9886 100755
--- a/testbench/sdc/ram2sdLoad.py
+++ b/testbench/sdc/ram2sdLoad.py
@@ -6,8 +6,9 @@ import fileinput
address = 0
-for line in fileinput.input('-'):
- # the 14- is to reverse the byte order to little endian
- formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
- sys.stdout.write(f'@{address:08x} {formatedLine:s}\n')
- address+=8
+with fileinput.input('-') as f:
+ for line in f:
+ # the 14- is to reverse the byte order to little endian
+ formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
+ sys.stdout.write(f'@{address:08x} {formatedLine:s}\n')
+ address+=8
diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py
index 12196a1b3..728d58ae9 100644
--- a/tests/coverage/dcache1.py
+++ b/tests/coverage/dcache1.py
@@ -40,9 +40,9 @@ mem_addr = mem_start_addr
def wl(line="", comment=None, fname=test_name):
with open(fname, "a") as f:
- instr = False if (":" in line or
- ".align" in line or
- "# include" in line) else True
+ instr = not (":" in line or
+ ".align" in line or
+ "# include" in line)
indent = 6 if instr else 0
comment = "// " + comment if comment is not None else ""
to_write = " " * indent + line + comment + "\n"
diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
index 5212d01d7..14caa796e 100755
--- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py
+++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
@@ -76,218 +76,212 @@ def create_vectors(my_config):
operation = my_config.op_code
rounding_mode = "X"
flags = "XX"
- # use name to create our new tv
- dest_file = open(f"{dest_dir}cvw_{my_config.bits}_{vector1[:-2]}.tv", 'w')
- # open vectors
- src_file1 = open(source_dir1 + vector1)
- src_file2 = open(source_dir2 + vector2)
- # for each test in the vector
- reading = True
- src_file2.readline() #skip first bc junk
- # print(my_config.bits, my_config.letter)
- if my_config.letter == "F" and my_config.bits == 64:
+ # use name to create our new tv and open vectors
+ with open(f"{dest_dir}cvw_{my_config.bits}_{vector1[:-2]}.tv", 'w') as dest_file, open(source_dir1 + vector1) as src_file1, open(source_dir2 + vector2) as src_file2:
+ # for each test in the vector
reading = True
- # print("trigger 64F")
- #skip first 2 lines bc junk
- src_file2.readline()
- while reading:
- # get answer and flags from Ref...signature
- # answers are before deadbeef (first line of 4)
- # flags are after deadbeef (third line of 4)
- answer = src_file2.readline().strip()
- deadbeef = src_file2.readline().strip()
- # print(answer)
- if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
- # get flags
- packed = src_file2.readline().strip()[6:]
- flags, rounding_mode = unpack_rf(packed)
- # skip 00000000 buffer
- src_file2.readline()
-
- # parse through .S file
- detected = False
- done = False
- op1val = "0"
- op2val = "0"
- while not (detected or done):
- # print("det1")
- line = src_file1.readline()
- # print(line)
- if "op1val" in line:
- # print("det2")
- # parse line
-
- # handle special case where destination register is hardwired to zero
- if "dest:x0" in line:
- answer = "x" * len(answer)
-
- op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
- if my_config.op != "fsqrt": # sqrt doesn't have two input vals
- op2val = line.split("op2val")[1].split("x")[1].strip()
- if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
- else:
- op2val = 32*"X"
- # go to next test in vector
- detected = True
- elif "RVTEST_CODE_END" in line:
- done = True
- # put it all together
- if not done:
- translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
- dest_file.write(translation + "\n")
- else:
- # print("read false")
- reading = False
- elif my_config.letter == "M" and my_config.bits == 64:
- reading = True
- #skip first 2 lines bc junk
- src_file2.readline()
- while reading:
- # print("trigger 64M")
- # get answer from Ref...signature
- # answers span two lines and are reversed
- answer2 = src_file2.readline().strip()
- answer1 = src_file2.readline().strip()
- answer = answer1 + answer2
- #print(answer1,answer2)
- if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
- # parse through .S file
- detected = False
- done = False
- op1val = "0"
- op2val = "0"
- while not (detected or done):
- # print("det1")
- line = src_file1.readline()
- # print(line)
- if "op1val" in line:
- # print("det2")
- # parse line
- # handle special case where destination register is hardwired to zero
- if "dest:x0" in line:
- answer = "x" * len(answer)
- op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
- if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
- op1val = twos_comp(my_config.bits, op1val)
- if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
- op2val = line.split("op2val")[1].split("x")[1].strip()
- if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
- if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
- op2val = twos_comp(my_config.bits, op2val)
- # go to next test in vector
- detected = True
- elif "RVTEST_CODE_END" in line:
- done = True
- # ints don't have flags
- flags = "XX"
- # put it all together
- if not done:
- translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
- dest_file.write(translation + "\n")
- else:
- # print("read false")
- reading = False
- elif my_config.letter == "M" and my_config.bits == 32:
- reading = True
- while reading:
- # print("trigger 64M")
- # get answer from Ref...signature
- # answers span two lines and are reversed
- answer = src_file2.readline().strip()
- # print(f"Answer: {answer}")
- #print(answer1,answer2)
- if not (answer == "6f5ca309"): # if there is still stuff to read
- # parse through .S file
- detected = False
- done = False
- op1val = "0"
- op2val = "0"
- while not (detected or done):
- # print("det1")
- line = src_file1.readline()
- # print(line)
- if "op1val" in line:
- # print("det2")
- # parse line
- # handle special case where destination register is hardwired to zero
- if "dest:x0" in line:
- answer = "x" * len(answer)
- op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
- if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
- op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
- if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
- op1val = twos_comp(my_config.bits, op1val)
- if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
- op2val = line.split("op2val")[1].split("x")[1].strip()
- if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
- if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
- op2val = twos_comp(my_config.bits, op2val)
- # go to next test in vector
- detected = True
- elif "RVTEST_CODE_END" in line:
- done = True
- # ints don't have flags
- flags = "XX"
- # put it all together
- if not done:
- translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
- dest_file.write(translation + "\n")
- else:
- # print("read false")
- reading = False
- else:
- while reading:
- # get answer and flags from Ref...signature
- answer = src_file2.readline()
- #print(answer)
- packed = src_file2.readline()[6:]
- #print("Packed: ", packed)
- if len(packed.strip())>0: # if there is still stuff to read
- # print("packed")
- # parse through .S file
- detected = False
- done = False
- op1val = "0"
- op2val = "0"
- while not (detected or done):
- # print("det1")
- line = src_file1.readline()
- # print(line)
- if "op1val" in line:
- # print("det2")
- # parse line
-
- # handle special case where destination register is hardwired to zero
- if "dest:x0" in line:
- answer = "x" * len(answer)
-
- op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
- if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
- op1val = twos_comp(my_config.bits, op1val)
- if my_config.op != "fsqrt": # sqrt doesn't have two input vals
- op2val = line.split("op2val")[1].split("x")[1].strip()
- if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
- if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
- op2val = twos_comp(my_config.bits, op2val)
- # go to next test in vector
- detected = True
- elif "RVTEST_CODE_END" in line:
- done = True
- # rounding mode for float
- if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
+ src_file2.readline() #skip first bc junk
+ # print(my_config.bits, my_config.letter)
+ if my_config.letter == "F" and my_config.bits == 64:
+ reading = True
+ # print("trigger 64F")
+ #skip first 2 lines bc junk
+ src_file2.readline()
+ while reading:
+ # get answer and flags from Ref...signature
+ # answers are before deadbeef (first line of 4)
+ # flags are after deadbeef (third line of 4)
+ answer = src_file2.readline().strip()
+ deadbeef = src_file2.readline().strip()
+ # print(answer)
+ if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
+ # get flags
+ packed = src_file2.readline().strip()[6:]
flags, rounding_mode = unpack_rf(packed)
-
- # put it all together
- if not done:
- translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
- dest_file.write(translation + "\n")
- else:
- # print("read false")
- reading = False
- # print("out")
- dest_file.close()
- src_file1.close()
- src_file2.close()
+ # skip 00000000 buffer
+ src_file2.readline()
+
+ # parse through .S file
+ detected = False
+ done = False
+ op1val = "0"
+ op2val = "0"
+ while not (detected or done):
+ # print("det1")
+ line = src_file1.readline()
+ # print(line)
+ if "op1val" in line:
+ # print("det2")
+ # parse line
+
+ # handle special case where destination register is hardwired to zero
+ if "dest:x0" in line:
+ answer = "x" * len(answer)
+
+ op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+ if my_config.op != "fsqrt": # sqrt doesn't have two input vals
+ op2val = line.split("op2val")[1].split("x")[1].strip()
+ if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+ else:
+ op2val = 32*"X"
+ # go to next test in vector
+ detected = True
+ elif "RVTEST_CODE_END" in line:
+ done = True
+ # put it all together
+ if not done:
+ translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
+ dest_file.write(translation + "\n")
+ else:
+ # print("read false")
+ reading = False
+ elif my_config.letter == "M" and my_config.bits == 64:
+ reading = True
+ #skip first 2 lines bc junk
+ src_file2.readline()
+ while reading:
+ # print("trigger 64M")
+ # get answer from Ref...signature
+ # answers span two lines and are reversed
+ answer2 = src_file2.readline().strip()
+ answer1 = src_file2.readline().strip()
+ answer = answer1 + answer2
+ #print(answer1,answer2)
+ if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
+ # parse through .S file
+ detected = False
+ done = False
+ op1val = "0"
+ op2val = "0"
+ while not (detected or done):
+ # print("det1")
+ line = src_file1.readline()
+ # print(line)
+ if "op1val" in line:
+ # print("det2")
+ # parse line
+ # handle special case where destination register is hardwired to zero
+ if "dest:x0" in line:
+ answer = "x" * len(answer)
+ op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+ if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+ op1val = twos_comp(my_config.bits, op1val)
+ if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
+ op2val = line.split("op2val")[1].split("x")[1].strip()
+ if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+ if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+ op2val = twos_comp(my_config.bits, op2val)
+ # go to next test in vector
+ detected = True
+ elif "RVTEST_CODE_END" in line:
+ done = True
+ # ints don't have flags
+ flags = "XX"
+ # put it all together
+ if not done:
+ translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
+ dest_file.write(translation + "\n")
+ else:
+ # print("read false")
+ reading = False
+ elif my_config.letter == "M" and my_config.bits == 32:
+ reading = True
+ while reading:
+ # print("trigger 64M")
+ # get answer from Ref...signature
+ # answers span two lines and are reversed
+ answer = src_file2.readline().strip()
+ # print(f"Answer: {answer}")
+ #print(answer1,answer2)
+ if answer != '6f5ca309': # if there is still stuff to read
+ # parse through .S file
+ detected = False
+ done = False
+ op1val = "0"
+ op2val = "0"
+ while not (detected or done):
+ # print("det1")
+ line = src_file1.readline()
+ # print(line)
+ if "op1val" in line:
+ # print("det2")
+ # parse line
+ # handle special case where destination register is hardwired to zero
+ if "dest:x0" in line:
+ answer = "x" * len(answer)
+ op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+ if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+ op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+ if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+ op1val = twos_comp(my_config.bits, op1val)
+ if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
+ op2val = line.split("op2val")[1].split("x")[1].strip()
+ if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+ if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+ op2val = twos_comp(my_config.bits, op2val)
+ # go to next test in vector
+ detected = True
+ elif "RVTEST_CODE_END" in line:
+ done = True
+ # ints don't have flags
+ flags = "XX"
+ # put it all together
+ if not done:
+ translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
+ dest_file.write(translation + "\n")
+ else:
+ # print("read false")
+ reading = False
+ else:
+ while reading:
+ # get answer and flags from Ref...signature
+ answer = src_file2.readline()
+ #print(answer)
+ packed = src_file2.readline()[6:]
+ #print("Packed: ", packed)
+ if len(packed.strip())>0: # if there is still stuff to read
+ # print("packed")
+ # parse through .S file
+ detected = False
+ done = False
+ op1val = "0"
+ op2val = "0"
+ while not (detected or done):
+ # print("det1")
+ line = src_file1.readline()
+ # print(line)
+ if "op1val" in line:
+ # print("det2")
+ # parse line
+
+ # handle special case where destination register is hardwired to zero
+ if "dest:x0" in line:
+ answer = "x" * len(answer)
+
+ op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+ if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+ op1val = twos_comp(my_config.bits, op1val)
+ if my_config.op != "fsqrt": # sqrt doesn't have two input vals
+ op2val = line.split("op2val")[1].split("x")[1].strip()
+ if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+ if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+ op2val = twos_comp(my_config.bits, op2val)
+ # go to next test in vector
+ detected = True
+ elif "RVTEST_CODE_END" in line:
+ done = True
+ # rounding mode for float
+ if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
+ flags, rounding_mode = unpack_rf(packed)
+
+ # put it all together
+ if not done:
+ translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
+ dest_file.write(translation + "\n")
+ else:
+ # print("read false")
+ reading = False
+ # print("out")
config_list = [
Config(32, "M", "div", "div-", 0),
diff --git a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py b/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
index e5e2e18da..d6aaa75e1 100755
--- a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
+++ b/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
@@ -39,19 +39,15 @@ for vector in div_vectors:
config_list = vector.split(".")[0].split("_")
operation = "1" #float div
rounding_mode = round_dict[str(config_list[2])]
- # use name to create our new tv
- dest_file = open(dest_dir + "cvw_" + vector, 'a')
- # open vector
- src_file = open(source_dir + vector)
- # for each test in the vector
- for i in src_file.readlines():
- translation = "" # this stores the test that we are currently working on
- [input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
- # put it all together, strip nec for removing \n on the end of the flags
- translation = f"{operation}_{ext_bits(input_1)}_{ext_bits(input_2)}_{ext_bits(answer)}_{flags.strip()}_{rounding_mode}"
- dest_file.write(translation + "\n")
- dest_file.close()
- src_file.close()
+ # use name to create our new tv and open vector
+ with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
+ # for each test in the vector
+ for i in src_file.readlines():
+ translation = "" # this stores the test that we are currently working on
+ [input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
+ # put it all together, strip nec for removing \n on the end of the flags
+ translation = f"{operation}_{ext_bits(input_1)}_{ext_bits(input_2)}_{ext_bits(answer)}_{flags.strip()}_{rounding_mode}"
+ dest_file.write(translation + "\n")
print("creating testfloat sqrt test vectors")
@@ -64,16 +60,12 @@ for vector in sqrt_vectors:
config_list = vector.split(".")[0].split("_")
operation = "2" #sqrt
rounding_mode = round_dict[str(config_list[2])]
- # use name to create our new tv
- dest_file = open(dest_dir + "cvw_" + vector, 'a')
- # open vector
- src_file = open(source_dir + vector)
- # for each test in the vector
- for i in src_file.readlines():
- translation = "" # this stores the test that we are currently working on
- [input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
- # put it all together, strip nec for removing \n on the end of the flags
- translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
- dest_file.write(translation + "\n")
- dest_file.close()
- src_file.close()
+ # use name to create our new tv and open vector
+ with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
+ # for each test in the vector
+ for i in src_file.readlines():
+ translation = "" # this stores the test that we are currently working on
+ [input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
+ # put it all together, strip nec for removing \n on the end of the flags
+ translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
+ dest_file.write(translation + "\n")