mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
Rose Thompson
commit
4f59bd492d
@ -116,7 +116,7 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
# Wally needs Verilator 5.0 or later.
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||||
# Verilator needs to be built from scratch to get the latest version
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||||
# apt-get install verilator installs version 4.028 as of 6/8/23
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||||
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g
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||||
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g
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||||
sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
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cd $RISCV
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git clone https://github.com/verilator/verilator # Only first time
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@ -127,7 +127,7 @@ git pull # Make sure git repository is up-to-date
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git checkout master # Use development branch (e.g. recent bug fixes)
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autoconf # Create ./configure script
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./configure # Configure and create Makefile
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make -j NUM_THREADS # Build Verilator itself (if error, try just 'make')
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make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make')
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sudo make install
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# Sail (https://github.com/riscv/sail-riscv)
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@ -15,6 +15,8 @@ all: riscoftests memfiles coveragetests
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# Link Linux test vectors
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#cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
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wally-riscv-arch-test: wallyriscoftests memfiles
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coverage:
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#make -C ../tests/coverage --jobs
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#iter-elf.bash --cover --search ../tests/coverage
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@ -50,6 +52,10 @@ riscoftests:
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# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
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make -C ../tests/riscof/
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wallyriscoftests:
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# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
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make -C ../tests/riscof/ wally-riscv-arch-test
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memfiles:
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make -f makefile-memfile wally-sim-files --jobs
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@ -26,7 +26,7 @@
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--override cpu/Zicboz=T
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--override cmomp_bytes=64 # Zic64b
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--override cmoz_bytes=64 # Zic64b
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--override lr_sc_grain=64 # Za64rs
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--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size
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# 64 KiB continuous huge pages supported
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--override cpu/Svpbmt=T
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@ -56,8 +56,8 @@
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# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svadu=T
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--override cpu/updatePTEA=F
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--override cpu/updatePTED=F
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#--override cpu/updatePTEA=F
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#--override cpu/updatePTED=F
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# THIS NEEDS FIXING to 16
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@ -81,12 +81,12 @@
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#
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--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL
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--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
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--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC
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--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT
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--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC
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--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10069000 - 0x100600FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw--A- --4- " # SPI error - 0x10040000 - 0x10040FFF
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--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
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--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
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--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
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--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
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# Enable the Imperas instruction coverage
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@ -40,16 +40,20 @@ module lrsc import cvw::*; #(parameter cvw_t P) (
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output logic SquashSCW // Squash the store conditional by not allowing rf write
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);
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// reservation set size is XLEN for Wally
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localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
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localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
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// possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
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// Handle atomic load reserved / store conditional
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logic [P.PA_BITS-1:2] ReservationPAdrW;
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logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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logic SquashSCM;
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assign lrM = MemReadM & LSUAtomicM[0];
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assign scM = PreLSURWM[0] & LSUAtomicM[0];
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assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
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assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] == ReservationPAdrW) & ReservationValidW;
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assign SquashSCM = scM & ~WriteAdrMatchM;
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assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
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always_comb begin // ReservationValidM (next value of valid reservation)
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@ -59,7 +63,7 @@ module lrsc import cvw::*; #(parameter cvw_t P) (
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else ReservationValidM = ReservationValidW; // otherwise don't change valid
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end
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flopenr #(P.PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenr #(P.PA_BITS-RESERVATION_SET_ADDRESS_BITS) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS], ReservationPAdrW); // could drop clear on this one but not valid
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flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
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flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
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endmodule
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@ -90,6 +90,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
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logic Misaligned;
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logic MegapageMisaligned;
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logic PTE_N; // NAPOT page table entry
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logic NAPOT4; // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
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if(P.XLEN == 32) begin
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assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
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@ -105,10 +106,11 @@ module tlb import cvw::*; #(parameter cvw_t P,
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end
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assign VPN = VAdr[P.VPN_BITS+11:12];
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assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
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tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
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||||
.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush,
|
||||
.PTEAccessBits, .CAMHit, .Misaligned,
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.PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4,
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.TLBMiss, .TLBHit, .TLBPageFault,
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.UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);
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||||
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@ -41,6 +41,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
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input logic [11:0] PTEAccessBits,
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input logic CAMHit,
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input logic Misaligned,
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input logic NAPOT4, // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
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output logic TLBMiss,
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output logic TLBHit,
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output logic TLBPageFault,
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@ -86,7 +87,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
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// check if reserved, N, or PBMT bits are malformed w in RV64
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assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) |
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{PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs;
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assign BadNAPOT = PTE_N & ~P.SVNAPOT_SUPPORTED; // N must be be 0 if CVNAPOT is not supported
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assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region
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assign BadReserved = PTE_RESERVED; // Reserved bits must be zero
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// Check whether the access is allowed, page faulting if not.
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@ -296,6 +296,12 @@ write_file -format ddc -hierarchy -o $filename
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set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
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write_sdf $filename
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# Write SPEF file in case need more precision power exploration for TSMC28psyn
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if {$tech == "tsmc28psyn"} {
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set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"]
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redirect $filename { write_parasitics }
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}
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# QoR
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set filename [format "%s%s" $outputDir "/reports/qor.rep"]
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redirect $filename { report_qor }
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@ -88,7 +88,6 @@ module testbenchfp;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [P.DURLEN-1:0] Dur;
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// in-between FMA signals
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logic Mult;
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@ -145,11 +144,9 @@ module testbenchfp;
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initial begin
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// Information displayed for user on what is simulating
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//$display("\nThe start of simulation...");
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//$display("This simulation for TEST is %s", TEST);
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//$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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// $display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN);
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// $display("\nThe start of simulation...");
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// $display("This simulation for TEST is %s", TEST);
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// $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
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if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
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@ -781,19 +778,19 @@ module testbenchfp;
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end
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else if (UnitVal === `CVTFPUNIT) begin
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case (OpCtrlVal[1:0])
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4'b11: begin // quad
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||||
2'b11: begin // quad
|
||||
AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]);
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ResNaN = &Res[P.Q_LEN-2:P.NF]&(|Res[P.Q_NF-1:0]);
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||||
end
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4'b01: begin // double
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||||
2'b01: begin // double
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||||
AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
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ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
|
||||
end
|
||||
4'b00: begin // single
|
||||
2'b00: begin // single
|
||||
AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
|
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ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
|
||||
end
|
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4'b10: begin // half
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||||
2'b10: begin // half
|
||||
AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
|
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ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
|
||||
end
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||||
@ -801,19 +798,19 @@ module testbenchfp;
|
||||
end
|
||||
else begin
|
||||
case (FmtVal)
|
||||
4'b11: begin // quad
|
||||
2'b11: begin // quad
|
||||
AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]);
|
||||
ResNaN = &Res[P.Q_LEN-2:P.Q_NF]&(|Res[P.Q_NF-1:0]);
|
||||
end
|
||||
4'b01: begin // double
|
||||
2'b01: begin // double
|
||||
AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
|
||||
ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
|
||||
end
|
||||
4'b00: begin // single
|
||||
2'b00: begin // single
|
||||
AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
|
||||
ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
|
||||
end
|
||||
4'b10: begin // half
|
||||
2'b10: begin // half
|
||||
AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
|
||||
ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
|
||||
end
|
||||
@ -854,22 +851,22 @@ module testbenchfp;
|
||||
// arbitrary value and can be changed, if needed.
|
||||
case (FmtVal)
|
||||
// QP
|
||||
4'b11: begin
|
||||
2'b11: begin
|
||||
repeat (20)
|
||||
@(posedge clk);
|
||||
end
|
||||
// HP
|
||||
4'b10: begin
|
||||
2'b10: begin
|
||||
repeat (14)
|
||||
@(posedge clk);
|
||||
end
|
||||
// DP
|
||||
4'b01: begin
|
||||
2'b01: begin
|
||||
repeat (18)
|
||||
@(posedge clk);
|
||||
end
|
||||
// SP
|
||||
4'b00: begin
|
||||
2'b00: begin
|
||||
repeat (16)
|
||||
@(posedge clk);
|
||||
end
|
||||
@ -886,22 +883,22 @@ module testbenchfp;
|
||||
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
|
||||
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
|
||||
case (FmtVal)
|
||||
4'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
|
||||
(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
|
||||
4'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
|
||||
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
|
||||
4'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
|
||||
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
|
||||
4'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
|
||||
@ -967,14 +964,6 @@ module testbenchfp;
|
||||
|
||||
// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
|
||||
// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
|
||||
|
||||
// Note: Went through and determined that this is not needed with new module additions
|
||||
// Just needs to check flags against TestFloat (left just in case (remove after check one more time))
|
||||
// else if ((UnitVal === `CVTINTUNIT) &
|
||||
// ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
|
||||
// (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) |
|
||||
// (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
|
||||
// (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
else if ((UnitVal === `CVTINTUNIT) &
|
||||
~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
errors += 1;
|
||||
@ -995,8 +984,14 @@ module testbenchfp;
|
||||
// incemet the operation if all the rounding modes have been tested
|
||||
if (FrmNum === 4) OpCtrlNum += 1;
|
||||
// increment the rounding mode or loop back to rne
|
||||
if (FrmNum < 4) FrmNum += 1;
|
||||
else FrmNum = 0;
|
||||
if (FrmNum < 4)
|
||||
FrmNum += 1;
|
||||
else begin
|
||||
FrmNum = 0;
|
||||
// Add some time as a buffer between tests at the end of each test
|
||||
repeat (10)
|
||||
@(posedge clk);
|
||||
end
|
||||
// if no more Tests - finish
|
||||
if (Tests[TestNum] === "") begin
|
||||
$display("\nAll Tests completed with %d errors\n", errors);
|
||||
@ -1034,7 +1029,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
);
|
||||
|
||||
localparam Q_LEN = 32'd128;
|
||||
//`include "parameter-defs.vh"
|
||||
|
||||
logic XEn;
|
||||
logic YEn;
|
||||
@ -1113,7 +1107,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
if (OpCtrl[0])
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
#20;
|
||||
X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
if (~clk) #5;
|
||||
@ -1121,7 +1114,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
#20;
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
@ -1129,7 +1121,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
#20;
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
@ -1137,7 +1128,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b10: begin // half
|
||||
#20;
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
if (~clk) #5;
|
||||
@ -1148,7 +1138,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
else
|
||||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
#20;
|
||||
X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
|
||||
Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
@ -1157,7 +1146,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
#20;
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
@ -1166,7 +1154,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
#20;
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
@ -1175,7 +1162,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
DivStart = 1'b0;
|
||||
end
|
||||
2'b10: begin // half
|
||||
#20;
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
@ -1403,11 +1389,11 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
|
||||
assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
|
||||
assign ZEn = (Unit == `FMAUNIT);
|
||||
// Will fix with better activation - for now, this works (jes)
|
||||
assign FPUActive = 1'b1;
|
||||
|
||||
unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
|
||||
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
||||
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
||||
.XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -108,6 +108,10 @@ beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
|
||||
00000000
|
||||
BEEF0660 # Test 11.3.1.3.9: NAPOT read
|
||||
0550DEAD
|
||||
0000000d # Test 11.3.1.3.9: page fault on malformed NAPOT PTE
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0
|
||||
00000000
|
||||
00000009 # ecall from going to M mode from S mode
|
||||
|
||||
@ -48,7 +48,7 @@ RVMODEL_BOOT
|
||||
|
||||
# Testcase 1: Do an unsuccessful load-reserved / store conditional word operation
|
||||
addi x6, x6, 24
|
||||
addi x30, x31, 4
|
||||
addi x30, x31, 8 # 8 bytes later (reservation set size is 8 bytes)
|
||||
li x11, 43
|
||||
lr.w x10, (x30)
|
||||
sc.w x12, x11, (x31) # should fail because not reserved
|
||||
@ -59,7 +59,7 @@ RVMODEL_BOOT
|
||||
|
||||
# Testcase 2: Do a successful load-reserved / store conditional doubleword operation
|
||||
addi x6, x6, 24
|
||||
addi x31, x30, 4
|
||||
addi x31, x30, 8
|
||||
li x11, 44
|
||||
lr.d x10, (x31)
|
||||
sc.d x12, x11, (x31)
|
||||
|
||||
@ -86,22 +86,23 @@ test_cases:
|
||||
.8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1
|
||||
.8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2
|
||||
.8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3
|
||||
.8byte 0x0000000080018080, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018088, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018090, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018098, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180A0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180A8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180B0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180B8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180C0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180C8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180D0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180D8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180E0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180E8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180F0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180F8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018080, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018088, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018090, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018098, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180A0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180A8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180B0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180B8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180C0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180C8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180D0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180D8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180E0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180E8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180F0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x00000000800180F8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
|
||||
.8byte 0x0000000080018150, 0x80000000200800DF, write64_test# Vaddr 0x20000, Paddr = 0x80200000, NAPOT malformed with ppn[3] =0
|
||||
|
||||
# Level 0 page table B
|
||||
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
|
||||
@ -208,7 +209,7 @@ test_cases:
|
||||
|
||||
# Now set ADUE bit
|
||||
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
|
||||
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1
|
||||
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1
|
||||
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
|
||||
|
||||
# Since SVADU is 1, there are no faults when A/D=0
|
||||
@ -226,6 +227,9 @@ test_cases:
|
||||
# test 11.3.1.3.9 NAPOT read
|
||||
.8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page
|
||||
|
||||
# test 11.3.1.3.9 NAPOT read
|
||||
.8byte 0x2A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page with malformed PTE should page fault
|
||||
|
||||
# test 11.3.1.3.10 PBMT checks
|
||||
.8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0
|
||||
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
|
||||
|
||||
Loading…
Reference in New Issue
Block a user