From 68d96a929c6013a685819b6b9c54f3611d20efb1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 13 Dec 2023 16:37:54 -0800 Subject: [PATCH 1/9] Fixed hierarchical path to EcallFaultM in testbench --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ece7500d5..f9887fc52 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -271,7 +271,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (TEST == "coremark") - if (dut.core.EcallFaultM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end From 166c98b6f63d9185adc92da2ad759e5d52ae7fe6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 13 Dec 2023 19:43:17 -0800 Subject: [PATCH 2/9] Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn --- sim/Makefile | 6 +++ sim/imperas.ic | 4 +- src/mmu/tlb/tlb.sv | 4 +- src/mmu/tlb/tlbcontrol.sv | 7 ++-- ...9-svadu-svnapot-svpbmt-01.reference_output | 4 ++ .../WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S | 38 ++++++++++--------- 6 files changed, 40 insertions(+), 23 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 52f7efdcf..396f6aa9d 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -15,6 +15,8 @@ all: riscoftests memfiles coveragetests # Link Linux test vectors #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh +wally-riscv-arch-test: wallyriscoftests memfiles + coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage @@ -49,6 +51,10 @@ clean: riscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions make -C ../tests/riscof/ + +wallyriscoftests: +# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions + make -C ../tests/riscof/ wally-riscv-arch-test memfiles: make -f makefile-memfile wally-sim-files --jobs diff --git a/sim/imperas.ic b/sim/imperas.ic index 483666cca..77324e754 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -56,8 +56,8 @@ # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1 --override cpu/Svadu=T ---override cpu/updatePTEA=F ---override cpu/updatePTED=F +#--override cpu/updatePTEA=F +#--override cpu/updatePTED=F # THIS NEEDS FIXING to 16 diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 2685c831f..674e8ef33 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -90,6 +90,7 @@ module tlb import cvw::*; #(parameter cvw_t P, logic Misaligned; logic MegapageMisaligned; logic PTE_N; // NAPOT page table entry + logic NAPOT4; // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region if(P.XLEN == 32) begin assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 @@ -105,10 +106,11 @@ module tlb import cvw::*; #(parameter cvw_t P, end assign VPN = VAdr[P.VPN_BITS+11:12]; + assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4 tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush, - .PTEAccessBits, .CAMHit, .Misaligned, + .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, .TLBMiss, .TLBHit, .TLBPageFault, .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType); diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index d5047d9b9..ac630bc4e 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -41,6 +41,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( input logic [11:0] PTEAccessBits, input logic CAMHit, input logic Misaligned, + input logic NAPOT4, // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region output logic TLBMiss, output logic TLBHit, output logic TLBPageFault, @@ -85,9 +86,9 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( // check if reserved, N, or PBMT bits are malformed w in RV64 assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) | - {PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs; - assign BadNAPOT = PTE_N & ~P.SVNAPOT_SUPPORTED; // N must be be 0 if CVNAPOT is not supported - assign BadReserved = PTE_RESERVED; // Reserved bits must be zero + {PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs; + assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region + assign BadReserved = PTE_RESERVED; // Reserved bits must be zero // Check whether the access is allowed, page faulting if not. if (ITLB == 1) begin:itlb // Instruction TLB fault checking diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output index 320d3f9c4..ca5c4d38f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output @@ -108,6 +108,10 @@ beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1 00000000 BEEF0660 # Test 11.3.1.3.9: NAPOT read 0550DEAD +0000000d # Test 11.3.1.3.9: page fault on malformed NAPOT PTE +00000000 +00000bad +00000000 0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0 00000000 00000009 # ecall from going to M mode from S mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 7681438b6..0c4786729 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -86,22 +86,23 @@ test_cases: .8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1 .8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2 .8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3 -.8byte 0x0000000080018080, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018088, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018090, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018098, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180A0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180A8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180B0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180B8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180C0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180C8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180D0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180D8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180E0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180E8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180F0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180F8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018080, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018088, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018090, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018098, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180A0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180A8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180B0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180B8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180C0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180C8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180D0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180D8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180E0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180E8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180F0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180F8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018150, 0x80000000200800DF, write64_test# Vaddr 0x20000, Paddr = 0x80200000, NAPOT malformed with ppn[3] =0 # Level 0 page table B .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage @@ -208,7 +209,7 @@ test_cases: # Now set ADUE bit .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output -.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1 +.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1 .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output # Since SVADU is 1, there are no faults when A/D=0 @@ -226,6 +227,9 @@ test_cases: # test 11.3.1.3.9 NAPOT read .8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page +# test 11.3.1.3.9 NAPOT read +.8byte 0x2A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page with malformed PTE should page fault + # test 11.3.1.3.10 PBMT checks .8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0 .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output From 68d49c37db94a0e47b6ae91a0cafddafa4933c20 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 13 Dec 2023 20:49:26 -0800 Subject: [PATCH 3/9] Changed PMA settings in imperas.ic so that peripherals require aligned accesses. This fixes WALLY-trap in ImperasDV. --- sim/imperas.ic | 12 ++++++------ sim/wave.do | 8 -------- 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 77324e754..b7f63bcd2 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -81,12 +81,12 @@ # --callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL --callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM ---callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC ---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT ---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC ---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF ---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10069000 - 0x100600FF ---callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw--A- --4- " # SPI error - 0x10040000 - 0x10040FFF +--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC +--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT +--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC +--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF +--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF +--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF --callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM # Enable the Imperas instruction coverage diff --git a/sim/wave.do b/sim/wave.do index 0304c967c..63afd5734 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -99,19 +99,11 @@ add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr add wave -noupdate -expand -group lsu -group alignment -color Gold /testbench/dut/core/lsu/ziccslm_align/align/CurrState add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/MemRWM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/DTLBMissM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/CacheableM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/HalfSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/WordSpillM -add wave -noupdate -expand -group lsu -group alignment -color Orange /testbench/dut/core/lsu/ziccslm_align/align/SpillM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IEUAdrSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SaveByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskSaveM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillE add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/SelSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskMuxM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM From 29f57958a9b68460a1db90f647e55ee774020bf6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 14 Dec 2023 15:32:36 -0800 Subject: [PATCH 4/9] Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match --- sim/imperas.ic | 2 +- src/cache/cachefsm.sv | 1 + src/lsu/lrsc.sv | 10 +++++++--- .../rv64i_m/privilege/src/WALLY-lrsc-01.S | 4 ++-- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index b7f63bcd2..e716d78b6 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -26,7 +26,7 @@ --override cpu/Zicboz=T --override cmomp_bytes=64 # Zic64b --override cmoz_bytes=64 # Zic64b ---override lr_sc_grain=64 # Za64rs +--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size # 64 KiB continuous huge pages supported --override cpu/Svpbmt=T diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index cfc0a8c16..b67340989 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -79,6 +79,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, logic CMOWriteback; logic CMOZeroNoEviction; logic StallConditions; + logic StoreHazard; typedef enum logic [3:0]{STATE_READY, // hit states // miss states diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index cc6c94ba8..66a9956dc 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -40,16 +40,20 @@ module lrsc import cvw::*; #(parameter cvw_t P) ( output logic SquashSCW // Squash the store conditional by not allowing rf write ); + // reservation set size is XLEN for Wally + localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8; + localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64 + // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest. // Handle atomic load reserved / store conditional - logic [P.PA_BITS-1:2] ReservationPAdrW; + logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] ReservationPAdrW; logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; logic SquashSCM; assign lrM = MemReadM & LSUAtomicM[0]; assign scM = PreLSURWM[0] & LSUAtomicM[0]; - assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW; + assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] == ReservationPAdrW) & ReservationValidW; assign SquashSCM = scM & ~WriteAdrMatchM; assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM; always_comb begin // ReservationValidM (next value of valid reservation) @@ -59,7 +63,7 @@ module lrsc import cvw::*; #(parameter cvw_t P) ( else ReservationValidM = ReservationValidW; // otherwise don't change valid end - flopenr #(P.PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenr #(P.PA_BITS-RESERVATION_SET_ADDRESS_BITS) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS], ReservationPAdrW); // could drop clear on this one but not valid flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW); flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW); endmodule diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S index 3cf332f6b..fd8b6ceaa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S @@ -48,7 +48,7 @@ RVMODEL_BOOT # Testcase 1: Do an unsuccessful load-reserved / store conditional word operation addi x6, x6, 24 - addi x30, x31, 4 + addi x30, x31, 8 # 8 bytes later (reservation set size is 8 bytes) li x11, 43 lr.w x10, (x30) sc.w x12, x11, (x31) # should fail because not reserved @@ -59,7 +59,7 @@ RVMODEL_BOOT # Testcase 2: Do a successful load-reserved / store conditional doubleword operation addi x6, x6, 24 - addi x31, x30, 4 + addi x31, x30, 8 li x11, 44 lr.d x10, (x31) sc.d x12, x11, (x31) From 8d8bad61d42ef2bb97a26e960938fa2cc5706b65 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 15 Dec 2023 17:02:11 -0600 Subject: [PATCH 5/9] Fix to take care of Issue #507. Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507. Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity. --- testbench/testbench-fp.sv | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 761c49d35..2f5dedaca 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -145,11 +145,9 @@ module testbenchfp; initial begin // Information displayed for user on what is simulating - //$display("\nThe start of simulation..."); - //$display("This simulation for TEST is %s", TEST); - //$display("This simulation for TEST is of the operand size of %s", TEST_SIZE); - - // $display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN); + // $display("\nThe start of simulation..."); + // $display("This simulation for TEST is %s", TEST); + // $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion @@ -967,14 +965,6 @@ module testbenchfp; // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - - // Note: Went through and determined that this is not needed with new module additions - // Just needs to check flags against TestFloat (left just in case (remove after check one more time)) - // else if ((UnitVal === `CVTINTUNIT) & - // ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | - // (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | - // (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | - // (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin else if ((UnitVal === `CVTINTUNIT) & ~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin errors += 1; @@ -1034,7 +1024,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( ); localparam Q_LEN = 32'd128; - //`include "parameter-defs.vh" logic XEn; logic YEn; @@ -1113,7 +1102,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( if (OpCtrl[0]) case (Fmt) 2'b11: begin // quad - #20; X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; if (~clk) #5; @@ -1121,7 +1109,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b01: if (P.D_SUPPORTED) begin // double - #20; X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; if (~clk) #5; @@ -1129,7 +1116,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b00: if (P.S_SUPPORTED) begin // single - #20; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; if (~clk) #5; @@ -1137,7 +1123,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b10: begin // half - #20; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; if (~clk) #5; @@ -1148,7 +1133,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( else case (Fmt) 2'b11: begin // quad - #20; X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; @@ -1157,7 +1141,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b01: if (P.D_SUPPORTED) begin // double - #20; X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; @@ -1166,7 +1149,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b00: if (P.S_SUPPORTED) begin // single - #20; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; @@ -1175,7 +1157,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( DivStart = 1'b0; end 2'b10: begin // half - #20; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; @@ -1403,11 +1384,11 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); assign ZEn = (Unit == `FMAUNIT); - // Will fix with better activation - for now, this works (jes) assign FPUActive = 1'b1; unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, .XEn, .YEn, .ZEn, .XExpMax, .XPostBox); + endmodule From 01a246422fb671f91234cdd2cccb2f33ad92a3e3 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 15 Dec 2023 17:04:37 -0600 Subject: [PATCH 6/9] Update bug in wally-tool-chain-install.sh script due to misspelling for an environmental variable. In addition, zlibc was removed due to deprecation --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 373e354e9..c52ee485c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -116,7 +116,7 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Wally needs Verilator 5.0 or later. # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 -sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g +sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error) cd $RISCV git clone https://github.com/verilator/verilator # Only first time @@ -127,7 +127,7 @@ git pull # Make sure git repository is up-to-date git checkout master # Use development branch (e.g. recent bug fixes) autoconf # Create ./configure script ./configure # Configure and create Makefile -make -j NUM_THREADS # Build Verilator itself (if error, try just 'make') +make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') sudo make install # Sail (https://github.com/riscv/sail-riscv) From 27a79948477b5156152c7061c1cf88041bc4bef1 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 15 Dec 2023 17:21:24 -0600 Subject: [PATCH 7/9] Modify DC to export spef for DC extraction of parasitics. This file can be used to read in an ancillary tool (e.g., snps PrimeTime) to get more detail on power estimation --- synthDC/scripts/synth.tcl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index cd4d6ff27..6a360a836 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -296,6 +296,12 @@ write_file -format ddc -hierarchy -o $filename set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"] write_sdf $filename +# Write SPEF file in case need more precision power exploration for TSMC28psyn +if {$tech != "tsmc28psyn"} { + set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"] + redirect $filename { write_parasitics } +} + # QoR set filename [format "%s%s" $outputDir "/reports/qor.rep"] redirect $filename { report_qor } From 54b0285300f57352f6d0e2f3ed86b58fc48a12d6 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 15 Dec 2023 23:06:05 -0600 Subject: [PATCH 8/9] fix bad typo on spef integration for tsmc28psyn --- synthDC/scripts/synth.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 6a360a836..1699532d6 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -297,7 +297,7 @@ set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"] write_sdf $filename # Write SPEF file in case need more precision power exploration for TSMC28psyn -if {$tech != "tsmc28psyn"} { +if {$tech == "tsmc28psyn"} { set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"] redirect $filename { write_parasitics } } From f4c1713ed41e8be6a3b81d90dd66d8aad14c29c3 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sun, 17 Dec 2023 20:55:06 -0600 Subject: [PATCH 9/9] Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes. --- testbench/testbench-fp.sv | 43 ++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 2f5dedaca..4bc3153df 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -88,7 +88,6 @@ module testbenchfp; logic OldFDivBusyE; logic reset = 1'b0; logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt; - logic [P.DURLEN-1:0] Dur; // in-between FMA signals logic Mult; @@ -779,19 +778,19 @@ module testbenchfp; end else if (UnitVal === `CVTFPUNIT) begin case (OpCtrlVal[1:0]) - 4'b11: begin // quad + 2'b11: begin // quad AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]); ResNaN = &Res[P.Q_LEN-2:P.NF]&(|Res[P.Q_NF-1:0]); end - 4'b01: begin // double + 2'b01: begin // double AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]); ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]); end - 4'b00: begin // single + 2'b00: begin // single AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]); ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]); end - 4'b10: begin // half + 2'b10: begin // half AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]); ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]); end @@ -799,19 +798,19 @@ module testbenchfp; end else begin case (FmtVal) - 4'b11: begin // quad + 2'b11: begin // quad AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]); ResNaN = &Res[P.Q_LEN-2:P.Q_NF]&(|Res[P.Q_NF-1:0]); end - 4'b01: begin // double + 2'b01: begin // double AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]); ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]); end - 4'b00: begin // single + 2'b00: begin // single AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]); ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]); end - 4'b10: begin // half + 2'b10: begin // half AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]); ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]); end @@ -852,22 +851,22 @@ module testbenchfp; // arbitrary value and can be changed, if needed. case (FmtVal) // QP - 4'b11: begin + 2'b11: begin repeat (20) @(posedge clk); end // HP - 4'b10: begin + 2'b10: begin repeat (14) @(posedge clk); end // DP - 4'b01: begin + 2'b01: begin repeat (18) @(posedge clk); end // SP - 4'b00: begin + 2'b00: begin repeat (16) @(posedge clk); end @@ -884,22 +883,22 @@ module testbenchfp; // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) - 4'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | + 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) | (ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]}))); - 4'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | + 2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) | (ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]}))); - 4'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | + 2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) | (ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]}))); - 4'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | + 2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | @@ -985,8 +984,14 @@ module testbenchfp; // incemet the operation if all the rounding modes have been tested if (FrmNum === 4) OpCtrlNum += 1; // increment the rounding mode or loop back to rne - if (FrmNum < 4) FrmNum += 1; - else FrmNum = 0; + if (FrmNum < 4) + FrmNum += 1; + else begin + FrmNum = 0; + // Add some time as a buffer between tests at the end of each test + repeat (10) + @(posedge clk); + end // if no more Tests - finish if (Tests[TestNum] === "") begin $display("\nAll Tests completed with %d errors\n", errors);