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Fixed enabling of TransmitFIFOReadIncrement and ReceiveFIFOWriteIncrement

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This commit is contained in:
Jacob Pease 2024-10-30 16:19:46 -05:00
parent ca1c09041a
commit 4f0723f236
1 changed files with 14 additions and 4 deletions
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16
src/uncore/spi_apb.sv
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@ -231,9 +231,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) begin if (~PRESETn) begin
TransmitFIFOWriteIncrement <= 1'b0; TransmitFIFOWriteIncrement <= 1'b0;
TransmitFIFOReadIncrement <= 1'b0;
end else begin end else begin
TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull); TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
end
always_ff @(posedge PCLK)
if (~PRESETn) begin
TransmitFIFOReadIncrement <= 1'b0;
end else if (SCLKenable) begin
TransmitFIFOReadIncrement <= TransmitLoad; TransmitFIFOReadIncrement <= TransmitLoad;
end end
@ -241,7 +246,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK) begin always_ff @(posedge PCLK) begin
if (~PRESETn) begin if (~PRESETn) begin
CurrState <= READY; CurrState <= READY;
end else if (SCLKenable) begin end else begin
CurrState <= NextState; CurrState <= NextState;
end end
end end
@ -273,9 +278,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) begin if (~PRESETn) begin
ReceiveFIFOReadIncrement <= 1'b0; ReceiveFIFOReadIncrement <= 1'b0;
ReceiveFIFOWriteInc <= 1'b0;
end else begin end else begin
ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement); ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
end
always_ff @(posedge PCLK)
if (~PRESETn) begin
ReceiveFIFOWriteInc <= 1'b0;
end else if (SCLKenable) begin
ReceiveFIFOWriteInc <= EndOfFrameDelay; ReceiveFIFOWriteInc <= EndOfFrameDelay;
end end