From 4f0723f23618509255922671127d1eba00769c53 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Wed, 30 Oct 2024 16:19:46 -0500
Subject: [PATCH] Fixed enabling of TransmitFIFOReadIncrement and
 ReceiveFIFOWriteIncrement

---
 src/uncore/spi_apb.sv | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index ebe0726c1..8442cd1b7 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -231,17 +231,22 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
   always_ff @(posedge PCLK)
     if (~PRESETn) begin
       TransmitFIFOWriteIncrement <= 1'b0;
-      TransmitFIFOReadIncrement <= 1'b0;
     end else begin
       TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
-      TransmitFIFOReadIncrement <= TransmitLoad;
     end
 
+  always_ff @(posedge PCLK)
+    if (~PRESETn) begin
+      TransmitFIFOReadIncrement <= 1'b0;
+    end else if (SCLKenable) begin
+      TransmitFIFOReadIncrement <= TransmitLoad;
+  end
+
   // Setup TransmitStart state machine
   always_ff @(posedge PCLK) begin
     if (~PRESETn) begin
       CurrState <= READY;
-    end else if (SCLKenable) begin
+    end else begin
       CurrState <= NextState;
     end
   end
@@ -273,9 +278,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
   always_ff @(posedge PCLK)
     if (~PRESETn) begin
       ReceiveFIFOReadIncrement <= 1'b0;
-      ReceiveFIFOWriteInc <= 1'b0;
     end else begin
       ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
+    end
+
+  always_ff @(posedge PCLK)
+    if (~PRESETn) begin
+      ReceiveFIFOWriteInc <= 1'b0;
+    end else if (SCLKenable) begin
       ReceiveFIFOWriteInc <= EndOfFrameDelay;
     end