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Fixed formatting

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Harshini Srinath 2023-07-30 18:06:25 -07:00 committed by GitHub
parent 1badc8a8c5
commit 4c1a07eb9c
1 changed files with 10 additions and 10 deletions
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src/fpu/postproc/normshift.sv
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@ -27,47 +27,47 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
// convert shift // convert shift
// fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp // fp -> int: | `XLEN zeros | Mantissa | 0's if necessary | << CalcExp
// process: // process:
// - start - CalcExp = 1 + XExp - Largest Bias // - start - CalcExp = 1 + XExp - Largest Bias
// | `XLEN zeros | Mantissa | 0's if nessisary | // | `XLEN zeros | Mantissa | 0's if necessary |
// //
// - shift left 1 (1) // - shift left 1 (1)
// | `XLEN-1 zeros |bit| frac | 0's if nessisary | // | `XLEN-1 zeros |bit| frac | 0's if necessary |
// . <- binary point // . <- binary point
// //
// - shift left till unbiased exponent is 0 (XExp - Largest Bias) // - shift left till unbiased exponent is 0 (XExp - Largest Bias)
// | 0's | Mantissa | 0's if nessisary | // | 0's | Mantissa | 0's if necessary |
// | keep | // | keep |
// //
// fp -> fp: // fp -> fp:
// - if result is subnormal or underflowed: // - if result is subnormal or underflowed:
// | `NF-1 zeros | Mantissa | 0's if nessisary | << NF+CalcExp-1 // | `NF-1 zeros | Mantissa | 0's if necessary | << NF+CalcExp-1
// process: // process:
// - start // - start
// | mantissa | 0's | // | mantissa | 0's |
// //
// - shift right by NF-1 (NF-1) // - shift right by NF-1 (NF-1)
// | `NF-1 zeros | mantissa | 0's | // | `NF-1 zeros | mantissa | 0's |
// //
// - shift left by CalcExp = XExp - Largest bias + new bias // - shift left by CalcExp = XExp - Largest bias + new bias
// | 0's | mantissa | 0's | // | 0's | mantissa | 0's |
// | keep | // | keep |
// //
// - if the input is subnormal: // - if the input is subnormal:
// | lzcIn | 0's if nessisary | << ZeroCnt+1 // | lzcIn | 0's if necessary | << ZeroCnt+1
// - plus 1 to shift out the first 1 // - plus 1 to shift out the first 1
// //
// int -> fp: | lzcIn | 0's if nessisary | << ZeroCnt+1 // int -> fp: | lzcIn | 0's if necessary | << ZeroCnt+1
// - plus 1 to shift out the first 1 // - plus 1 to shift out the first 1
// fma shift // fma shift
// | 00 | Sm | << LZA output // | 00 | Sm | << LZA output
// . // .
// - two extra bits so we can correct for an LZA error of 1 or 2 // - two extra bits so we can correct for an LZA error of 1 or 2
// divsqrt shift // divsqrt shift
// | Nf 0's | Qm | << calculated shift amount // | Nf 0's | Qm | << calculated shift amount
// . // .
module normshift import cvw::*; #(parameter cvw_t P) ( module normshift import cvw::*; #(parameter cvw_t P) (