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OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(

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This commit is contained in:
Ross Thompson 2023-04-17 11:10:19 -05:00
parent 5591b447d6
commit 4ad33d7acc
2 changed files with 2 additions and 2 deletions
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2
fpga/generator/xlnx_ddr3-artya7-mig.prj
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@ -43,7 +43,7 @@
<Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-125</MemoryDevice>
<TimePeriod>3000</TimePeriod>
<TimePeriod>6000</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>102.564</InputClkFreq>

2
fpga/generator/xlnx_mmcm.tcl
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@ -13,7 +13,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.6667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKIN1_JITTER_PS {10.0} \