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Merge pull request #602 from stineje/main

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update Boolean logic for all testing for divide
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Rose Thompson 2024-01-29 21:28:17 -06:00 committed by GitHub
commit 3f2bb98a77
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1 changed files with 5 additions and 5 deletions
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testbench/testbench-fp.sv
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@ -848,7 +848,7 @@ module testbenchfp;
end end
S2: begin S2: begin
DivStart = 1'b0; DivStart = 1'b0;
if ((FDivBusyE)|(~DivDone)) if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT))
nextstate = S2; nextstate = S2;
else else
nextstate = Done; nextstate = Done;
@ -960,8 +960,8 @@ module testbenchfp;
assign FMAop = (OpCtrlVal == `FMAUNIT); assign FMAop = (OpCtrlVal == `FMAUNIT);
assign DivDone = OldFDivBusyE & ~FDivBusyE; assign DivDone = OldFDivBusyE & ~FDivBusyE;
assign CheckNow = ((DivDone | ~divsqrtop) | assign CheckNow = ((DivDone | ~divsqrtop) |
(TEST == "all" | TEST == "add" | TEST == "fma" | TEST == "sub")) (TEST == "add" | TEST == "fma" | TEST == "sub") |
& (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); ((TEST == "all") & (DivDone | ~divsqrtop)));
if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin
errors += 1; errors += 1;