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Merge pull request #600 from davidharrishmc/dev

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Rose Thompson 2024-01-29 21:28:01 -06:00 committed by GitHub
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241 changed files with 934 additions and 6 deletions
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1
.gitignore vendored
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@ -184,3 +184,4 @@ sim/cfi/*
sim/branch/*
sim/obj_dir
examples/verilog/fulladder/obj_dir
config/deriv

1
bin/CModelBTBAccuracy.sh
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@ -9,6 +9,7 @@
## Computes the geometric mean for btb accuracy
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/CModelBranchAccuracy.sh
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@ -9,6 +9,7 @@
## Computes the geometric mean.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/CacheSim.py
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@ -10,6 +10,7 @@
## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/SeparateBranch.sh
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@ -12,6 +12,7 @@
## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

124
bin/derivgen.pl Executable file
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@ -0,0 +1,124 @@
#!/bin/perl -W
###########################################
## derivgen.pl
##
## Written: David_Harris@hmc.edu
## Created: 29 January 2024
## Modified:
##
## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh
## derivative configurations from the base configurations
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################
use strict;
use warnings;
import os;
use Data::Dumper;
my $curderiv = "";
my @derivlist = ();
my %derivs;
my %basederiv;
if ($#ARGV != -1) {
die("Usage: $0")
}
my $derivlist = "$ENV{WALLY}/config/derivlist.txt";
open(my $fh, $derivlist) or die "Could not open file '$derivlist' $!";
foreach my $line (<$fh>) {
chomp $line;
my @tokens = split('\s+', $line);
if ($#tokens < 0 || $tokens[0] =~ /^#/) { # skip blank lines and comments
next;
}
if ($tokens[0] =~ /deriv/) { # start of a new derivative
&terminateDeriv();
$curderiv = $tokens[1];
$basederiv{$curderiv} = $tokens[2];
@derivlist = ();
if ($#tokens > 2) {
my $inherits = $derivs{$tokens[3]};
@derivlist = @{$inherits};
}
} else { # add to the current derivative
$line =~ /\s*(\S+)\s*(.*)/;
my @entry = ($1, $2);
push(@derivlist, \@entry);
}
}
&terminateDeriv();
close($fh);
foreach my $key (keys %derivs) {
my $dir = "$ENV{WALLY}/config/deriv/$key";
system("rm -rf $dir");
system("mkdir -p $dir");
my $configunmod = "$dir/config_unmod.vh";
my $config = "$dir/config.vh";
my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh";
system("cp $base $configunmod");
open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!";
open(my $fh, '>>', $config) or die "Could not open file '$config' $!";
my $datestring = localtime();
my %hit = ();
print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n";
foreach my $line (<$unmod>) {
foreach my $entry (@{$derivs{$key}}) {
my @ent = @{$entry};
my $param = $ent[0];
my $value = $ent[1];
if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) {
$hit{$param} = 1;
# print("Hit: new line in $config for $param is $line");
}
}
print $fh $line;
}
close($fh);
close($unmod);
foreach my $entry (@{$derivs{$key}}) {
my @ent = @{$entry};
my $param = $ent[0];
if (!exists($hit{$param})) {
print("Unable to find $param in $key\n");
}
}
system("rm -f $dir/config_unmod.vh");
}
sub terminateDeriv {
if ($curderiv ne "") { # close out the previous derivative
my @dl = @derivlist;
$derivs{$curderiv} = \@dl;
}
};
sub printref {
my $ref = shift;
my @array = @{$ref};
foreach my $entry (@array) {
print join('_', @{$entry}), ', ';
}
print("\n");
}

1
bin/elf2hex.sh
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@ -9,6 +9,7 @@
## Imperas and riscv-arch-test benchmarks
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/exe2memfile.pl
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@ -11,6 +11,7 @@
## to read into a Verilog simulation with $readmemh
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

21
bin/fparchtest.sh Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/bash
#
# fparchtest.sh
# David_Harris@hmc.edu 26 December 2023
#
# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests
# Set up with (not retested)
# cd ~/repos
# git clone https://github.com/riscv/riscv-ctg.git
# git clone https://github.com/riscv/riscv-isac.git
# pip3 install git+https://github.com/riscv/riscv-ctg.git
# pip3 install git+https://github.com/riscv/riscv-isac.git
# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
RISCVCTG=/home/harris/repos/riscv-ctg
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug
#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug

1
bin/imperas-one-time.sh
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@ -9,6 +9,7 @@
## Purpose: One time setup script for running imperas.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/libppa.pl
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@ -13,6 +13,7 @@
## and for TSMC change the $cellname to the actual name of the inverter.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/parseHPMC.py
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@ -8,6 +8,7 @@
## Purpose: Parses the performance counters from a modelsim trace.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/testcount.pl
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@ -12,6 +12,7 @@
## and count how many tests are in each
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/testlist.pl
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@ -11,6 +11,7 @@
## and generate a list of tests and signature addresses for tests.vh
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/vclean.pl
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@ -11,6 +11,7 @@
## verilator should do this, but it also reports partially used signals
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
bin/wally-tool-chain-install.sh
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@ -10,6 +10,7 @@
## Purpose: Open source tool chain installation script
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

2
config/buildroot/config.vh
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@ -153,7 +153,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 1;
localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0;

515
config/derivlist.txt Normal file
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@ -0,0 +1,515 @@
###########################################
## derivlist.txt
## Wally Derivative Configuration List
##
## Written: David_Harris@hmc.edu
## Created: 29 January 2024
## Modified:
##
## Purpose: Used by sim/make deriv to generate derivative configurations
## in config/deriv that are variants of the base configurations.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################
# Format:
# begin a derivative with "deriv <derivative name> <base configuration name> <inherited config name>
# Followed by a list of parameters and their new value in the derivative configuration
# All other parameter values are inherited from the original configuration
# If <inherited config name> is not empty, all the list of parameter changes in the inherited
# configuration are also applied to this configuration
# buildroot is used for the Linux boot
deriv buildroot rv64gc
RESET_VECTOR 64'h1000
UNCORE_RAM_RANGE 64'h0FFFFFFF
UNCORE_RAM_PRELOAD 1
GPIO_LOOPBACK_TEST 0
SPI_LOOPBACK_TEST 0
UART_PRESCALE 0
PLIC_NUM_SRC 32'd53
# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM)
deriv fpga rv64gc buildroot
BOOTROM_PRELOAD 1
UNCORE_RAM_BASE 64'h2000
UNCORE_RAM_RANGE 64'hFFF
EXT_MEM_SUPPORTED 1
EXT_MEM_BASE 64'h80000000
EXT_MEM_RANGE 64'h0FFFFFFF
SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12
# The syn configurations are trimmed down for faster synthesis.
deriv syn_rv32e rv32e
DTIM_RANGE 32'h1FF
IROM_RANGE 32'h1FF
BOOTROM_RANGE 32'h1FF
UNCORE_RAM_RANGE 32'h1FF
WAYSIZEINBYTES 32'd512
NUMWAYS 32'd1
BPRED_SIZE 32'd5
BTB_SIZE 32'd5
# The other syn configurations have the same trimming
deriv syn_rv32i rv32i syn_rv32e
deriv syn_rv32imc rv32imc syn_rv32e
deriv syn_rv32gc rv32gc syn_rv32e
deriv syn_rv64i rv64i syn_rv32e
deriv syn_rv64gc rv64gc syn_rv32e
# The syn_sram configurations use SRAM macros
deriv syn_sram_rv32e rv32e
DTIM_RANGE 32'h1FF
IROM_RANGE 32'h1FF
USE_SRAM 1
# The other syn configurations have the same trimming
deriv syn_sram_rv32i rv32i syn_sram_rv32e
deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
deriv syn_sram_rv64i rv64i syn_sram_rv32e
deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
# The following syn configurations gradually turn off features
deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
PMP_ENTRIES 0
deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
PMP_ENTRIES 0
deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
ZICSR_SUPPORTED 0
deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc
ZICSR_SUPPORTED 0
deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20)
deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc
MISA (32'h00000104 | 1 << 18 | 1 << 20)
# Divider variants to check logical correctness
deriv div_2_1_rv32gc rv32gc
RADIX 32'd2
DIVCOPIES 32'd1
deriv div_2_2_rv32gc rv32gc
RADIX 32'd2
DIVCOPIES 32'd2
deriv div_2_4_rv32gc rv32gc
RADIX 32'd2
DIVCOPIES 32'd4
deriv div_4_1_rv32gc rv32gc
RADIX 32'd4
DIVCOPIES 32'd1
deriv div_4_2_rv32gc rv32gc
RADIX 32'd4
DIVCOPIES 32'd2
deriv div_4_4_rv32gc rv32gc
RADIX 32'd4
DIVCOPIES 32'd4
deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc
IDIV_ON_FPU 1
deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc
IDIV_ON_FPU 1
deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc
IDIV_ON_FPU 1
deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc
IDIV_ON_FPU 1
deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc
IDIV_ON_FPU 1
deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc
IDIV_ON_FPU 1
deriv div_2_1_rv64gc rv64gc
RADIX 32'd2
DIVCOPIES 32'd1
deriv div_2_2_rv64gc rv64gc
RADIX 32'd2
DIVCOPIES 32'd2
deriv div_2_4_rv64gc rv64gc
RADIX 32'd2
DIVCOPIES 32'd4
deriv div_4_1_rv64gc rv64gc
RADIX 32'd4
DIVCOPIES 32'd1
deriv div_4_2_rv64gc rv64gc
RADIX 32'd4
DIVCOPIES 32'd2
deriv div_4_4_rv64gc rv64gc
RADIX 32'd4
DIVCOPIES 32'd4
deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc
IDIV_ON_FPU 1
deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc
IDIV_ON_FPU 1
deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc
IDIV_ON_FPU 1
deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc
IDIV_ON_FPU 1
deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc
IDIV_ON_FPU 1
deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc
IDIV_ON_FPU 1
# RAM latency and Burst mode for bus stress testing
deriv ram_0_0_rv64gc rv64gc
RAM_LATENCY 0
BURST_EN 0
deriv ram_1_0_rv64gc rv64gc
RAM_LATENCY 1
BURST_EN 0
deriv ram_2_0_rv64gc rv64gc
RAM_LATENCY 2
BURST_EN 0
deriv ram_1_1_rv64gc rv64gc
RAM_LATENCY 1
BURST_EN 1
deriv ram_2_1_rv64gc rv64gc
RAM_LATENCY 2
BURST_EN 1
# Branch predictor simulations
deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc
BPRED_SIZE 6
deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
BPRED_SIZE 8
deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
BPRED_SIZE 10
deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
BPRED_SIZE 12
deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
BPRED_SIZE 14
deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
BPRED_SIZE 16
deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
BPRED_TYPE BP_TWOBIT
deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
RAS_SIZE 2
deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
RAS_SIZE 3
deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
RAS_SIZE 4
deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
RAS_SIZE 6
deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
RAS_SIZE 10
deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
RAS_SIZE 16
deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
BTB_SIZE 6
deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
BTB_SIZE 8
deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
BTB_SIZE 12
deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
BTB_SIZE 14
deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
BTB_SIZE 16
deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc
ICLASSPRED 0
deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc
ICLASSPRED 0
# Cache configurations
deriv noicache_rv32gc rv32gc
ICACHE_SUPPORTED 0
deriv nodcache_rv32gc rv32gc
DCACHE_SUPPORTED 0
deriv nocache_rv32gc rv32gc
ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0
deriv way_1_4096_512_rv32gc rv32gc
DCACHE_NUMWAYS 1
DCACHE_WAYSIZEINBYTES 4096
DCACHE_LINELENINBITS 512
ICACHE_NUMWAYS 1
ICACHE_WAYSIZEINBYTES 4096
ICACHE_LINELENINBITS 512
deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 1
ICACHE_NUMWAYS 1
deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
DCACHE_NUMWAYS 4
ICACHE_NUMWAYS 4
deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_WAYSIZEINBYTES 2048
ICACHE_WAYSIZEINBYTES 2048
deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 256
ICACHE_LINELENINBITS 256
deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
DCACHE_LINELENINBITS 1024
ICACHE_LINELENINBITS 1024
deriv noicache_rv64gc rv64gc
ICACHE_SUPPORTED 0
deriv nodcache_rv64gc rv64gc
DCACHE_SUPPORTED 0
deriv nocache_rv64gc rv64gc
ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0
deriv way_1_4096_512_rv64gc rv64gc
DCACHE_NUMWAYS 1
DCACHE_WAYSIZEINBYTES 4096
DCACHE_LINELENINBITS 512
ICACHE_NUMWAYS 1
ICACHE_WAYSIZEINBYTES 4096
ICACHE_LINELENINBITS 512
deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 1
ICACHE_NUMWAYS 1
deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
DCACHE_NUMWAYS 4
ICACHE_NUMWAYS 4
deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_WAYSIZEINBYTES 2048
ICACHE_WAYSIZEINBYTES 2048
deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 256
ICACHE_LINELENINBITS 256
deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
DCACHE_LINELENINBITS 1024
ICACHE_LINELENINBITS 1024
# TLB Size variants
deriv tlb2_rv32gc rv32gc
ITLB_ENTRIES 2
DTLB_ENTRIES 2
deriv tlb16_rv32gc rv32gc
ITLB_ENTRIES 16
DTLB_ENTRIES 16
deriv tlb2_rv64gc rv64gc
ITLB_ENTRIES 2
DTLB_ENTRIES 2
deriv tlb16_rv64gc rv64gc
ITLB_ENTRIES 16
DTLB_ENTRIES 16
# Feature variants
deriv misaligned_rv32gc rv32gc
ZICCLSM_SUPPORTED 1
deriv nomisaligned_rv64gc rv64gc
ZICCLSM_SUPPORTED 0
deriv nobigendian_rv32gc rv32gc
BIGENDIAN_SUPPORTED 0
deriv nobigendian_rv64gc rv64gc
BIGENDIAN_SUPPORTED 0
# Floating-point modes supported
deriv f_rv32gc rv32gc
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fh_rv32gc rv32gc
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_rv32gc rv32gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdq_rv32gc rv32gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdqh_rv32gc rv32gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv f_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fh_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fd_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdqh_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1

5
config/rv32e/config.vh
View File

@ -132,6 +132,10 @@ localparam AHBW = 32'd32;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 0;
@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 0;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;

5
config/rv32gc/config.vh
View File

@ -133,6 +133,10 @@ localparam AHBW = 32'd32;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -166,6 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
`endif
localparam ICLASSPRED = 1;
localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0;

5
config/rv32i/config.vh
View File

@ -132,6 +132,10 @@ localparam AHBW = 32'd32;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 0;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;

5
config/rv32imc/config.vh
View File

@ -131,6 +131,10 @@ localparam AHBW = 32'd32;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 0;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;

5
config/rv64fpquad/config.vh
View File

@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 1;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;

6
config/rv64gc/config.vh
View File

@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6;
localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 1;
localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0;
@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0;
localparam USE_SRAM = 0;
`include "config-shared.vh"

5
config/rv64i/config.vh
View File

@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
// Test modes
// AHB
localparam RAM_LATENCY = 0;
localparam BURST_EN = 1;
// Tie GPIO outputs back to inputs
localparam GPIO_LOOPBACK_TEST = 1;
localparam SPI_LOOPBACK_TEST = 1;
@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16;
localparam ICLASSPRED = 0;
localparam SVADU_SUPPORTED = 0;
localparam ZMMUL_SUPPORTED = 0;

1
docs/Dockerfile
View File

@ -7,6 +7,7 @@
## Purpose: Dockerfile for Wally docker container creation
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
fpga/generator/insert_debug_comment.sh
View File

@ -7,6 +7,7 @@
## Modified: 20 January 2023
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
fpga/probe
View File

@ -7,6 +7,7 @@
## Modified: 16 August 2023
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
fpga/proberange
View File

@ -7,6 +7,7 @@
## Modified: 16 August 2023
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
fpga/probes
View File

@ -7,6 +7,7 @@
## Modified: 16 August 2023
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
gitflow.txt
View File

@ -1,5 +1,6 @@
###########################################
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

6
sim/Makefile
View File

@ -1,5 +1,5 @@
all: riscoftests memfiles coveragetests
all: riscoftests memfiles coveragetests deriv
# *** Build old tests/imperas-riscv-tests for now;
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
@ -60,3 +60,7 @@ memfiles:
coveragetests:
make -C ../tests/coverage/ --jobs
deriv:
derivgen.pl

1
sim/coverage-exclusions-rv64gc.do
View File

@ -7,6 +7,7 @@
#// For example, signals hardwired to 0 should not be checked for toggle coverage
#//
#// A component of the CORE-V-WALLY configurable RISC-V project.
#// https://github.com/openhwgroup/cvw
#//
#// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
#//

6
sim/lint-wally
View File

@ -1,14 +1,14 @@
#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
# The verilator lint tool is faster and better than Questa so it is best to run this first.
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do
#for config in rv64gc; do
echo "$config linting..."
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

1
sim/rv64gc_CacheSim.py
View File

@ -10,6 +10,7 @@
## Purpose: Run the cache simulator on each rv64gc test suite in turn.
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
sim/sim-imperas
View File

@ -10,6 +10,7 @@
## Purpose: Run wally with imperas
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##

1
src/cache/cache.sv vendored
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/cache/cacheLRU.sv vendored
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/cache/cachefsm.sv vendored
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/cache/cacheway.sv vendored
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/cache/subcachelineread.sv vendored
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 7
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/ahbcacheinterface.sv
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/ahbinterface.sv
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/buscachefsm.sv
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/busfsm.sv
View File

@ -10,6 +10,7 @@
// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/controllerinput.sv
View File

@ -14,6 +14,7 @@
// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/ebu.sv
View File

@ -14,6 +14,7 @@
// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/ebu/ebufsmarb.sv
View File

@ -11,6 +11,7 @@
// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fclassify.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fcmp.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fctrl.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrt.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtfgen2.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtfgen4.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtfsm.sv
View File

@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtuslc2.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtuslc4.sv
View File

@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fhazard.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

3
src/fpu/fli.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 16
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
@ -174,7 +175,7 @@ module fli import cvw::*; #(parameter cvw_t P) (
////////////////////////////
if (P.Q_SUPPORTED) begin
logic [63:0] QImm;
logic [127:0] QImm;
always_comb begin
case(Rs1)
0: QImm = 128'hBFFF0000000000000000000000000000;

1
src/fpu/fma/fma.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmaadd.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmaalign.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmaexpadd.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmalza.sv
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@ -10,6 +10,7 @@
// See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmamult.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fma/fmasign.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fpu.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fregfile.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/fsgninj.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/cvtshiftcalc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/divshiftcalc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/flags.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/fmashiftcalc.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/negateintres.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/normshift.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/postprocess.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/resultsign.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/round.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/roundsign.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/shiftcorrection.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/postproc/specialcase.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/unpack.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/fpu/unpackinput.sv
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@ -9,6 +9,7 @@
// Documentation: RISC-V System on Chip Design Chapter 13
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/adder.sv
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@ -7,6 +7,7 @@
// Purpose: Adder
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/aplusbeq0.sv
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@ -7,6 +7,7 @@
// Purpose: Determine if A+B = 0. Used in FP divider.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/arrs.sv
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@ -10,6 +10,7 @@
// rising edge, but then syncs the falling edge to the posedge clk.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/binencoder.sv
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@ -6,6 +6,7 @@
// Purpose: one-hot to binary encoding.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//

1
src/generic/clockgater.sv
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@ -7,6 +7,7 @@
// Purpose: Clock gater model. Must use standard cell for synthesis.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/counter.sv
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@ -7,6 +7,7 @@
// Purpose: Counter with reset and enable
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

1
src/generic/csa.sv
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@ -7,6 +7,7 @@
// Purpose: 3:2 carry-save adder
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//

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