diff --git a/sim/lint-wally b/sim/lint-wally
index c82d1603b..3125e79ea 100755
--- a/sim/lint-wally
+++ b/sim/lint-wally
@@ -1,6 +1,6 @@
 #!/bin/bash
 # check for warnings in Verilog code
-# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
+# The verilator lint tool is faster and better than Questa so it is best to run this first.
 export PATH=$PATH:/usr/local/bin/
 verilator=`which verilator`
 
diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv
index dedb230b0..cf3b736d7 100644
--- a/src/fpu/fli.sv
+++ b/src/fpu/fli.sv
@@ -175,7 +175,7 @@ module fli import cvw::*;  #(parameter cvw_t P) (
   ////////////////////////////
   
   if (P.Q_SUPPORTED) begin
-    logic [63:0] QImm;
+    logic [127:0] QImm;
     always_comb begin
         case(Rs1) 
             0:  QImm = 128'hBFFF0000000000000000000000000000;