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Merge pull request #1073 from naichewa/main

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Correct some SPI Delay0 register behavior, simplify unneeded Delay0 logic
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Rose Thompson 2024-11-08 13:15:35 -06:00 committed by GitHub
commit 3146f7394e
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1 changed files with 29 additions and 47 deletions
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src/uncore/spi_controller.sv
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@ -75,7 +75,6 @@ module spi_controller (
logic ShiftEdgePulse; logic ShiftEdgePulse;
logic SampleEdgePulse; logic SampleEdgePulse;
logic EndOfFramePulse; logic EndOfFramePulse;
logic PhaseOneOffset;
// Frame stuff // Frame stuff
logic [3:0] BitNum; logic [3:0] BitNum;
@ -93,6 +92,7 @@ module spi_controller (
logic [7:0] sckcs; logic [7:0] sckcs;
logic [7:0] intercs; logic [7:0] intercs;
logic [7:0] interxfr; logic [7:0] interxfr;
logic Phase;
logic HasCSSCK; logic HasCSSCK;
logic HasSCKCS; logic HasSCKCS;
@ -109,7 +109,6 @@ module spi_controller (
logic DelayIsNext; logic DelayIsNext;
logic DelayState; logic DelayState;
// Convenient Delay Reg Names // Convenient Delay Reg Names
assign cssck = Delay0[7:0]; assign cssck = Delay0[7:0];
assign sckcs = Delay0[15:8]; assign sckcs = Delay0[15:8];
@ -142,6 +141,7 @@ module spi_controller (
assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame; assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame;
assign EndTransmission = TransmitFIFOEmpty & EndOfFrame; assign EndTransmission = TransmitFIFOEmpty & EndOfFrame;
assign Phase = SckMode[0];
always_ff @(posedge PCLK) begin always_ff @(posedge PCLK) begin
if (~PRESETn) begin if (~PRESETn) begin
@ -152,7 +152,7 @@ module spi_controller (
DelayCounter <= 0; DelayCounter <= 0;
end else begin end else begin
// SCK logic for delay times // SCK logic for delay times
if (TransmitStart) begin if (TransmitStart & ~DelayState) begin
SCK <= 0; SCK <= 0;
end else if (SCLKenable) begin end else if (SCLKenable) begin
SCK <= ~SCK; SCK <= ~SCK;
@ -161,19 +161,21 @@ module spi_controller (
// Counter for all four delay types // Counter for all four delay types
if (DelayState & SCK & SCLKenable) begin if (DelayState & SCK & SCLKenable) begin
DelayCounter <= DelayCounter + 8'd1; DelayCounter <= DelayCounter + 8'd1;
end else if (SCLKenable & EndOfDelay) begin end else if ((SCLKenable & EndOfDelay) | Transmitting) begin
DelayCounter <= 8'd0; DelayCounter <= 8'd0;
end end
// SPICLK Logic // SPICLK Logic
if (TransmitStart) begin
if (TransmitStart & ~DelayState) begin
SPICLK <= SckMode[1]; SPICLK <= SckMode[1];
end else if (SCLKenable & Transmitting) begin end else if (SCLKenable) begin
SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
end end
// Reset divider // Reset divider
if (SCLKenable | TransmitStart | ResetSCLKenable) begin if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin
DivCounter <= 12'b0; DivCounter <= 12'b0;
end else begin end else begin
DivCounter <= DivCounter + 12'd1; DivCounter <= DivCounter + 12'd1;
@ -208,35 +210,18 @@ module spi_controller (
always_ff @(posedge ~PCLK) begin always_ff @(posedge ~PCLK) begin
if (~PRESETn | TransmitStart) begin if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0; ShiftEdge <= 0;
PhaseOneOffset <= 0;
SampleEdge <= 0; SampleEdge <= 0;
EndOfFrame <= 0; EndOfFrame <= 0;
end else begin end else if (^SckMode) begin
PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrame;
case(SckMode)
2'b00: begin
ShiftEdge <= SPICLK & ShiftEdgePulse;
SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse;
end
2'b01: begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse & PhaseOneOffset;
SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse;
end
2'b10: begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse; ShiftEdge <= ~SPICLK & ShiftEdgePulse;
SampleEdge <= SPICLK & SampleEdgePulse; SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse; EndOfFrame <= ~SPICLK & EndOfFramePulse;
end end else begin
2'b11: begin ShiftEdge <= SPICLK & ShiftEdgePulse;
ShiftEdge <= SPICLK & ShiftEdgePulse & PhaseOneOffset;
SampleEdge <= ~SPICLK & SampleEdgePulse; SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse; EndOfFrame <= SPICLK & EndOfFramePulse;
end end
endcase end
end
end
// Logic for continuing to transmit through Delay states after end of frame // Logic for continuing to transmit through Delay states after end of frame
assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR; assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
@ -263,18 +248,19 @@ module spi_controller (
TRANSMIT: begin // TRANSMIT case -------------------------------- TRANSMIT: begin // TRANSMIT case --------------------------------
case(CSMode) case(CSMode)
AUTOMODE: begin AUTOMODE: begin
if (EndTransmission) NextState = INACTIVE; if (EndTransmission & ~HasSCKCS) NextState = INACTIVE;
else if (EndOfFrame) NextState = SCKCS; else if (EndOfFrame & HasSCKCS) NextState = SCKCS;
else if (EndOfFrame & ~HasSCKCS) NextState = INTERCS;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end end
HOLDMODE: begin HOLDMODE: begin
if (EndTransmission) NextState = HOLD; if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; else if (EndTransmission) NextState = HOLD;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end end
OFFMODE: begin OFFMODE: begin
if (EndTransmission) NextState = INACTIVE; if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; else if (EndTransmission) NextState = HOLD;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end end
default: NextState = TRANSMIT; default: NextState = TRANSMIT;
@ -282,14 +268,7 @@ module spi_controller (
end end
SCKCS: begin // SCKCS case -------------------------------------- SCKCS: begin // SCKCS case --------------------------------------
if (EndOfSCKCS) begin if (EndOfSCKCS) begin
if (~TransmitRegLoaded) begin NextState = INTERCS;
// if (CSMode == AUTOMODE) NextState = INACTIVE;
if (CSMode == HOLDMODE) NextState = HOLD;
else NextState = INACTIVE;
end else begin
if (HasINTERCS) NextState = INTERCS;
else NextState = TRANSMIT;
end
end else begin end else begin
NextState = SCKCS; NextState = SCKCS;
end end
@ -303,15 +282,18 @@ module spi_controller (
end end
INTERCS: begin // INTERCS case ---------------------------------- INTERCS: begin // INTERCS case ----------------------------------
if (EndOfINTERCS) begin if (EndOfINTERCS) begin
if (HasCSSCK) NextState = CSSCK; if (TransmitRegLoaded) begin
else NextState = TRANSMIT; if (HasCSSCK) NextState = CSSCK;
else NextState = TRANSMIT;
end else NextState = INACTIVE;
end else begin end else begin
NextState = INTERCS; NextState = INTERCS;
end end
end end
INTERXFR: begin // INTERXFR case -------------------------------- INTERXFR: begin // INTERXFR case --------------------------------
if (EndOfINTERXFR) begin if (EndOfINTERXFR) begin
NextState = TRANSMIT; if (TransmitRegLoaded) NextState = TRANSMIT;
else NextState = HOLD;
end else begin end else begin
NextState = INTERXFR; NextState = INTERXFR;
end end