From 927398a017ede9eee0b2f9d27e5f924577dbfa30 Mon Sep 17 00:00:00 2001 From: naichewa Date: Thu, 7 Nov 2024 10:17:22 -0800 Subject: [PATCH 1/5] Fix SPI state skipping sck-cs delay when at end of transmission --- src/uncore/spi_controller.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 37c1e3ac9..a0aab008a 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -263,8 +263,9 @@ module spi_controller ( TRANSMIT: begin // TRANSMIT case -------------------------------- case(CSMode) AUTOMODE: begin - if (EndTransmission) NextState = INACTIVE; - else if (EndOfFrame) NextState = SCKCS; + if (EndTransmission & ~HasSCKCS) NextState = INACTIVE; + else if (EndOfFrame & HasSCKCS) NextState = SCKCS; + else if (EndOfFrame & ~HasSCKCS) NextState = INTERCS; else NextState = TRANSMIT; end HOLDMODE: begin From 7637f3e33b99e5d8e2404f7f9f5b90d71433de81 Mon Sep 17 00:00:00 2001 From: naichewa Date: Thu, 7 Nov 2024 10:19:55 -0800 Subject: [PATCH 2/5] Fix erroneous implicit sckcs and cssck phase delays --- src/uncore/spi_controller.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index a0aab008a..7a5126f2c 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -93,6 +93,7 @@ module spi_controller ( logic [7:0] sckcs; logic [7:0] intercs; logic [7:0] interxfr; + logic Phase; logic HasCSSCK; logic HasSCKCS; @@ -142,6 +143,7 @@ module spi_controller ( assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame; assign EndTransmission = TransmitFIFOEmpty & EndOfFrame; + assign Phase = SckMode[0]; always_ff @(posedge PCLK) begin if (~PRESETn) begin @@ -166,10 +168,12 @@ module spi_controller ( end // SPICLK Logic + if (TransmitStart) begin SPICLK <= SckMode[1]; - end else if (SCLKenable & Transmitting) begin - SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + end else if (SCLKenable) begin + if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; end // Reset divider From 79643586515878de143d1667d1e12c53210bf358 Mon Sep 17 00:00:00 2001 From: naichewa Date: Thu, 7 Nov 2024 10:47:51 -0800 Subject: [PATCH 3/5] Fix erroneous implicit sckcs and cssck phase delays --- src/uncore/spi_controller.sv | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 7a5126f2c..77cad340f 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -75,7 +75,6 @@ module spi_controller ( logic ShiftEdgePulse; logic SampleEdgePulse; logic EndOfFramePulse; - logic PhaseOneOffset; // Frame stuff logic [3:0] BitNum; @@ -212,35 +211,18 @@ module spi_controller ( always_ff @(posedge ~PCLK) begin if (~PRESETn | TransmitStart) begin ShiftEdge <= 0; - PhaseOneOffset <= 0; SampleEdge <= 0; EndOfFrame <= 0; - end else begin - PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrame; - case(SckMode) - 2'b00: begin - ShiftEdge <= SPICLK & ShiftEdgePulse; - SampleEdge <= ~SPICLK & SampleEdgePulse; - EndOfFrame <= SPICLK & EndOfFramePulse; - end - 2'b01: begin - ShiftEdge <= ~SPICLK & ShiftEdgePulse & PhaseOneOffset; - SampleEdge <= SPICLK & SampleEdgePulse; - EndOfFrame <= ~SPICLK & EndOfFramePulse; - end - 2'b10: begin + end else if (^SckMode) begin ShiftEdge <= ~SPICLK & ShiftEdgePulse; SampleEdge <= SPICLK & SampleEdgePulse; EndOfFrame <= ~SPICLK & EndOfFramePulse; - end - 2'b11: begin - ShiftEdge <= SPICLK & ShiftEdgePulse & PhaseOneOffset; + end else begin + ShiftEdge <= SPICLK & ShiftEdgePulse; SampleEdge <= ~SPICLK & SampleEdgePulse; EndOfFrame <= SPICLK & EndOfFramePulse; - end - endcase - end - end + end + end // Logic for continuing to transmit through Delay states after end of frame assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR; From 987015a2a707068576af5b3bad3675f177e40384 Mon Sep 17 00:00:00 2001 From: naichewa Date: Thu, 7 Nov 2024 12:14:23 -0800 Subject: [PATCH 4/5] Fix SPI Delay1 behavior --- src/uncore/spi_controller.sv | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 77cad340f..939457954 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -162,7 +162,7 @@ module spi_controller ( // Counter for all four delay types if (DelayState & SCK & SCLKenable) begin DelayCounter <= DelayCounter + 8'd1; - end else if (SCLKenable & EndOfDelay) begin + end else if ((SCLKenable & EndOfDelay) | Transmitting) begin DelayCounter <= 8'd0; end @@ -255,13 +255,13 @@ module spi_controller ( else NextState = TRANSMIT; end HOLDMODE: begin - if (EndTransmission) NextState = HOLD; - else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; + if (EndOfFrame & HasINTERXFR) NextState = INTERXFR; + else if (EndTransmission) NextState = HOLD; else NextState = TRANSMIT; end OFFMODE: begin - if (EndTransmission) NextState = INACTIVE; - else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; + if (EndOfFrame & HasINTERXFR) NextState = INTERXFR; + else if (EndTransmission) NextState = HOLD; else NextState = TRANSMIT; end default: NextState = TRANSMIT; @@ -269,14 +269,7 @@ module spi_controller ( end SCKCS: begin // SCKCS case -------------------------------------- if (EndOfSCKCS) begin - if (~TransmitRegLoaded) begin - // if (CSMode == AUTOMODE) NextState = INACTIVE; - if (CSMode == HOLDMODE) NextState = HOLD; - else NextState = INACTIVE; - end else begin - if (HasINTERCS) NextState = INTERCS; - else NextState = TRANSMIT; - end + NextState = INTERCS; end else begin NextState = SCKCS; end @@ -290,15 +283,18 @@ module spi_controller ( end INTERCS: begin // INTERCS case ---------------------------------- if (EndOfINTERCS) begin - if (HasCSSCK) NextState = CSSCK; - else NextState = TRANSMIT; + if (TransmitRegLoaded) begin + if (HasCSSCK) NextState = CSSCK; + else NextState = TRANSMIT; + end else NextState = INACTIVE; end else begin NextState = INTERCS; end end INTERXFR: begin // INTERXFR case -------------------------------- if (EndOfINTERXFR) begin - NextState = TRANSMIT; + if (TransmitRegLoaded) NextState = TRANSMIT; + else NextState = HOLD; end else begin NextState = INTERXFR; end From 396a17623b070efc276790a2a1faa20f07e528d0 Mon Sep 17 00:00:00 2001 From: naichewa Date: Fri, 8 Nov 2024 11:05:38 -0800 Subject: [PATCH 5/5] Fixed TransmitStart resetting SCK and delay counter while already counting --- src/uncore/spi_controller.sv | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 939457954..dee3d3c99 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -109,7 +109,6 @@ module spi_controller ( logic DelayIsNext; logic DelayState; - // Convenient Delay Reg Names assign cssck = Delay0[7:0]; assign sckcs = Delay0[15:8]; @@ -153,7 +152,7 @@ module spi_controller ( DelayCounter <= 0; end else begin // SCK logic for delay times - if (TransmitStart) begin + if (TransmitStart & ~DelayState) begin SCK <= 0; end else if (SCLKenable) begin SCK <= ~SCK; @@ -168,7 +167,7 @@ module spi_controller ( // SPICLK Logic - if (TransmitStart) begin + if (TransmitStart & ~DelayState) begin SPICLK <= SckMode[1]; end else if (SCLKenable) begin if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; @@ -176,7 +175,7 @@ module spi_controller ( end // Reset divider - if (SCLKenable | TransmitStart | ResetSCLKenable) begin + if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin DivCounter <= 12'b0; end else begin DivCounter <= DivCounter + 12'd1;