From 3108b58290d7dfe0f05d1ee47d5c7b078873b453 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 10 Nov 2023 14:55:36 -0800 Subject: [PATCH] Simplified integer postnormalization shift --- src/fpu/fdivsqrt/fdivsqrt.sv | 6 +++--- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 7 ++----- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 12 ++++++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 751486f86..ac5c2c338 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Integer div/rem signals logic BZeroM; // Denominator is zero logic IntDivM; // Integer operation - logic [P.DIVBLEN:0] mM, IntDivNormShiftM; // Shift amounts + logic [P.DIVBLEN:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases @@ -77,7 +77,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( .FmtE, .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE, // Int-specific .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE, - .BZeroM, .IntDivNormShiftM, .mM, .AM, + .BZeroM, .IntNormShiftM, .AM, .IntDivM, .W64M, .ALTBM, .AsM, .BsM); fdivsqrtfsm #(P) fdivsqrtfsm( // FSM @@ -96,6 +96,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, .UmM, .WZeroE, .DivStickyM, // Int-specific - .IntDivNormShiftM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, + .IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, .FIntDivResultM); endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 58649e3a8..3b6115201 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -37,7 +37,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic Firstun, SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, - input logic [P.DIVBLEN:0] mM, IntDivNormShiftM, + input logic [P.DIVBLEN:0] IntNormShiftM, output logic [P.DIVb:0] UmM, // result significand output logic WZeroE, output logic DivStickyM, @@ -96,7 +96,6 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( // Integer quotient or remainder correction, normalization, and special cases if (P.IDIV_ON_FPU) begin:intpostproc // Int supported - logic [P.DIVBLEN:0] NormShiftM; logic [P.DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM; logic signed [P.DIVb+3:0] PreResultM, PreIntResultM; @@ -110,10 +109,8 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( mux2 #(P.DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM); // Select quotient or remainder and do normalization shift - localparam DIVa = (P.DIVb+1-P.XLEN); // used for idiv on fpu: Shift residual right by b - (XLEN-1) to put remainder in lsbs of integer result - mux2 #(P.DIVBLEN+1) normshiftmux(IntDivNormShiftM, (mM + (P.DIVBLEN+1)'(DIVa)), RemOpM, NormShiftM); mux2 #(P.DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); - assign PreIntResultM = $signed(PreResultM >>> NormShiftM); + assign PreIntResultM = $signed(PreResultM >>> IntNormShiftM); // special case logic // terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B| diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 35757e480..137f54d99 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -42,7 +42,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( input logic IntDivE, W64E, output logic ISpecialCaseE, output logic [P.DURLEN-1:0] CyclesE, - output logic [P.DIVBLEN:0] mM, IntDivNormShiftM, + output logic [P.DIVBLEN:0] IntNormShiftM, output logic ALTBM, IntDivM, W64M, output logic AsM, BsM, BZeroM, output logic [P.XLEN-1:0] AM @@ -193,10 +193,15 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE); if (P.IDIV_ON_FPU) begin:intpipelineregs - logic [P.DIVBLEN:0] IntDivNormShiftE; + logic [P.DIVBLEN:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; + logic RemOpE; + /* verilator lint_off WIDTH */ assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain + assign IntRemNormShiftE = mE + (P.DIVb+1-P.XLEN); // m + b - (N-1) for remainder normalization shift /* verilator lint_on WIDTH */ + assign RemOpE = Funct3E[1]; + mux2 #(P.DIVBLEN+1) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE); // pipeline registers flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); @@ -204,8 +209,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM); flopen #(1) bsignreg(clk, IFDivStartE, BsE, BsM); - flopen #(P.DIVBLEN+1) nsreg(clk, IFDivStartE, IntDivNormShiftE, IntDivNormShiftM); - flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM); + flopen #(P.DIVBLEN+1) nsreg(clk, IFDivStartE, IntNormShiftE, IntNormShiftM); flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM); if (P.XLEN==64) flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);