From 2aa4db470bd41f0328578eb5783d785e5e683862 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 4 May 2021 13:03:08 -0500 Subject: [PATCH] Fixed synthesis bug with icache valid bit. --- wally-pipelined/src/ifu/icacheMem.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/ifu/icacheMem.sv b/wally-pipelined/src/ifu/icacheMem.sv index de83eb568..9c1321dd9 100644 --- a/wally-pipelined/src/ifu/icacheMem.sv +++ b/wally-pipelined/src/ifu/icacheMem.sv @@ -89,7 +89,9 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p // Correctly handle the valid bits always_ff @(posedge clk, posedge reset) begin - if (reset || flush) begin + if (reset) begin + ValidOut <= {NUMLINES{1'b0}}; + end else if (flush) begin ValidOut <= {NUMLINES{1'b0}}; end else begin if (WriteEnable) begin