diff --git a/wally-pipelined/src/ifu/icacheMem.sv b/wally-pipelined/src/ifu/icacheMem.sv index de83eb568..9c1321dd9 100644 --- a/wally-pipelined/src/ifu/icacheMem.sv +++ b/wally-pipelined/src/ifu/icacheMem.sv @@ -89,7 +89,9 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p // Correctly handle the valid bits always_ff @(posedge clk, posedge reset) begin - if (reset || flush) begin + if (reset) begin + ValidOut <= {NUMLINES{1'b0}}; + end else if (flush) begin ValidOut <= {NUMLINES{1'b0}}; end else begin if (WriteEnable) begin