From 74238defc37651cf6f0b930921807c354d884b8c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 20:23:19 -0600 Subject: [PATCH 01/14] Progress. --- sim/wave.do | 7 +++++-- testbench/testbench.sv | 39 +++++++++++++++++++++++++++++++-------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 90ed0b720..43ff1226b 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -662,8 +662,11 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart +add wave -noupdate -expand -group testbench /testbench/TestComplete +add wave -noupdate -expand -group testbench /testbench/CurrState TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {372450 ns} 0} {{Cursor 3} {403021 ns} 1} +WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {1405857 ns} 0} {{Cursor 3} {403021 ns} 1} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -679,4 +682,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {372177 ns} {372771 ns} +WaveRestoreZoom {0 ns} {16302587 ns} diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3526622bc..15d15aea0 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -85,7 +85,7 @@ module testbench; logic riscofTest; logic Validate; logic SelectTest; - + logic TestComplete; // pick tests based on modes supported initial begin @@ -176,6 +176,7 @@ module testbench; STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, + STATE_COPY_RAM, STATE_CHECK_TEST, STATE_CHECK_TEST_WAIT, STATE_VALIDATE, @@ -218,8 +219,9 @@ module testbench; STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; else NextState = STATE_RUN_TEST; - STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; + STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM; else NextState = STATE_RUN_TEST; + STATE_COPY_RAM: NextState = STATE_CHECK_TEST; STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; else NextState = STATE_CHECK_TEST_WAIT; STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; @@ -240,6 +242,8 @@ module testbench; assign ResetCntEn = CurrState == STATE_RESET_TEST; assign Validate = CurrState == STATE_VALIDATE; assign SelectTest = CurrState == STATE_INIT_TEST; + assign CopyRAM = TestComplete & CurrState == STATE_COPY_RAM; + assign DCacheFlushStart = CurrState == STATE_COPY_RAM; // fsm reset counter counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); @@ -380,6 +384,8 @@ module testbench; // load memories with program image //////////////////////////////////////////////////////////////////////////////// + integer IndexTemp; + logic [P.XLEN-0] value; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -403,6 +409,14 @@ module testbench; if (LoadMem) begin $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); end + if (CopyRAM) begin + for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin + //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. + //value = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; + testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; + //$display("Index = %x, Value = %x, Dest Index = %x", IndexTemp, value, ((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp); + end + end end end if (P.DTIM_SUPPORTED) begin @@ -411,6 +425,12 @@ module testbench; $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); $display("Read memfile %s", memfilename); end + if (CopyRAM) begin + for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin + //if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. + testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp]; + end + end end end @@ -502,14 +522,15 @@ module testbench; logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; - assign DCacheFlushStart = ecf & + assign TestComplete = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + //assign DCacheFlushStart = TestComplete; + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); task automatic CheckSignature; @@ -567,11 +588,13 @@ module testbench; logic [P.XLEN-1:0] sig; // ************************************** // ***** BUG BUG BUG make sure RT undoes this. - if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); - if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin + //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin + if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); From 2e792606ddca76108769a20d9a99d95894a2005d Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 12:06:00 -0600 Subject: [PATCH 02/14] More progress. Most tests are passing in modelsim. --- testbench/testbench.sv | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 15d15aea0..3607a5f06 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -242,7 +242,7 @@ module testbench; assign ResetCntEn = CurrState == STATE_RESET_TEST; assign Validate = CurrState == STATE_VALIDATE; assign SelectTest = CurrState == STATE_INIT_TEST; - assign CopyRAM = TestComplete & CurrState == STATE_COPY_RAM; + assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST; assign DCacheFlushStart = CurrState == STATE_COPY_RAM; // fsm reset counter @@ -385,7 +385,6 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// integer IndexTemp; - logic [P.XLEN-0] value; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -412,9 +411,7 @@ module testbench; if (CopyRAM) begin for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - //value = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; - //$display("Index = %x, Value = %x, Dest Index = %x", IndexTemp, value, ((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp); end end end @@ -590,14 +587,16 @@ module testbench; // ***** BUG BUG BUG make sure RT undoes this. //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); + //$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h", + // TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]); $stop; //***debug end i = i + 1; From 418ae0decc55038b65f8ed4a9da607db87c82b0b Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 14:18:21 -0600 Subject: [PATCH 03/14] Fixed some regression tests with David's help. --- .../references/WALLY-mmu-sv32-svadu-01.reference_output | 2 +- .../rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S | 1 + .../WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output | 4 ++-- .../privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S | 4 ++++ 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output index d0485cba3..1f6ccbd2c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output @@ -39,7 +39,7 @@ beef0110 0000000d # Test 11.3.1.3.6(a) page fault on read when A = 0 00000bad 0000000f # Test 11.3.1.3.7(a) page fault on write when D = 0 -deadbeef # Test 11.3.1.3.7(a) successful read when D = 0 +12345678 # Test 11.3.1.3.7(a) successful read when D = 0 00000009 # call from going to m mode from s mode 0000000b # ecall from going to S mode from m mode beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.ADUE=1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S index 400d34760..f4c30a8e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S @@ -88,6 +88,7 @@ test_cases: .4byte 0x80805EA0, 0xBEEF0440, write32_test # 11.3.1.3.3 .4byte 0x8000FFA0, 0x11100393, write32_test # write executable code for "li x7, 0x111; ret" to executable region. .4byte 0x8000FFA4, 0x00008067, write32_test # Used for 11.3.1.3.1, 11.3.1.3.2 +.4byte 0x80803658, 0x12345678, write32_test # initialize memory for 11.3.1.3.7(a) # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) .4byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output index ca5c4d38f..ce5c4cc3a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output @@ -92,8 +92,8 @@ beef0110 # Test 11.3.1.3.4: read test success 00000000 0000000f # Test 11.3.1.3.7(a): write test with page fault 00000000 -deadbeef # read test success but nothing was written so read back default -deadbeef +beef0991 # read test success but nothing was written so read back default +0880dead 00000009 # ecall from going to M mode from S mode 00000000 0000000B # ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 0c4786729..56d36aa6a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -124,6 +124,10 @@ test_cases: .8byte 0x84212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 .8byte 0x8020A400, 0x0550DEADBEEF0660, write64_test # 11.3.1.3.9 .8byte 0x80205000, 0x0770DEADBEEF0880, write64_test # 11.3.1.2.2 junk in memory location corresponding to invalid page + +#.8byte 0x800ffab8, 0x0880deadbeef0990, write64_test # 11.3.1.1.4 +.8byte 0x80203aa0, 0x0880deadbeef0991, write64_test # 11.3.1.3.7(a) +#.8byte 0x80205000, 0x0770DEADBEEF0880, write64_test # 11.3.1.2.2 junk in memory location corresponding to invalid page # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) .8byte 0x0, 0x0, goto_baremetal# satp.MODE = baremetal / no translation. From 726efee1e205f540272f0e1c3c284c8c315c56fa Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 15:53:48 -0600 Subject: [PATCH 04/14] Fixed bugs in the cbom test. --- .../references/WALLY-cbom-01.reference_output | 12 ++++++++---- .../rv64i_m/privilege/src/WALLY-cbom-01.S | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output index 8d394ca19..2059466b7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output @@ -444,9 +444,13 @@ ffffffff ffffffff ffffffff ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff 0bad0bad # controls -0bad0bad -0bad0bad -0bad0bad -0bad0bad 0bad0bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index 74145955a..f8725e08b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -624,7 +624,7 @@ Destination2: Destination3: .fill 128, 4, 0xdeadbeef signature: - .fill 40, 4, 0x0bad0bad + .fill 44, 4, 0x0bad0bad RVMODEL_DATA_END From b04ad23c33743027f74346db60670c274514b246 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 16:16:59 -0600 Subject: [PATCH 05/14] Fixed bugs in the wally64periph signature. --- .../privilege/references/WALLY-periph-01.reference_output | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output index fd88590e3..6c2080fff 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output @@ -440,7 +440,7 @@ FFFFFFCC # serviced low ip 00000065 00000060 00000001 -00000000 +000000FF 00000000 00000000 00000000 @@ -488,7 +488,7 @@ FFFFFFFE 0000006e 00000060 00000001 -00000000 +000000FF 00000000 00000000 00000000 From 49b1b7c7f9a73fcd62cca926b04c5850fff7101e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 16:51:56 -0600 Subject: [PATCH 06/14] Fixed the last uninitialized memory issue in the priv tests. --- .../rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S index 814c0cf18..5cecb41ce 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S @@ -114,7 +114,10 @@ test_cases: .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 .8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code - +.8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a) + +#.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4 + # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) .8byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation. .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output From d617eb097728bf2f451f8c61227dbbf4f519fbf2 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 19 Dec 2023 16:56:40 -0600 Subject: [PATCH 07/14] DON'T keep this commit. --- src/uncore/ram_ahb.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 896c2a4cb..6c16c675d 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -51,6 +51,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, logic memwrite, memwriteD, memread; logic nextHREADYRam; logic DelayReady; + logic [P.XLEN-1:0] HRDATA2; // a new AHB transactions starts when HTRANS requests a transaction, // the peripheral is selected, and the previous transaction is completing @@ -72,7 +73,13 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, // single-ported RAM ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1), - .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); + .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HRDATA2)); + + //assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2; + // **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues. + // PRIV sv48-svadu test not working without it. + assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; + //assign HREADRam = HRDATA2; // use this to add arbitrary latency to ram. Helps test AHB controller correctness if(`RAM_LATENCY > 0) begin From 9ee1ffe8fe1fd79023f64e1829d91f007af3113c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 11:29:31 -0600 Subject: [PATCH 08/14] Almost working with modelsim and verilator. --- src/uncore/ram_ahb.sv | 4 +- testbench/testbench.sv | 116 +++++++---------------------------------- 2 files changed, 20 insertions(+), 100 deletions(-) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 6c16c675d..f78998d9d 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -78,8 +78,8 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, //assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2; // **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues. // PRIV sv48-svadu test not working without it. - assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; - //assign HREADRam = HRDATA2; + //assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; + assign HREADRam = HRDATA2; // use this to add arbitrary latency to ram. Helps test AHB controller correctness if(`RAM_LATENCY > 0) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3607a5f06..ece7500d5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -85,7 +85,7 @@ module testbench; logic riscofTest; logic Validate; logic SelectTest; - logic TestComplete; + // pick tests based on modes supported initial begin @@ -176,7 +176,6 @@ module testbench; STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, - STATE_COPY_RAM, STATE_CHECK_TEST, STATE_CHECK_TEST_WAIT, STATE_VALIDATE, @@ -219,9 +218,8 @@ module testbench; STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; else NextState = STATE_RUN_TEST; - STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM; + STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; else NextState = STATE_RUN_TEST; - STATE_COPY_RAM: NextState = STATE_CHECK_TEST; STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; else NextState = STATE_CHECK_TEST_WAIT; STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; @@ -242,8 +240,6 @@ module testbench; assign ResetCntEn = CurrState == STATE_RESET_TEST; assign Validate = CurrState == STATE_VALIDATE; assign SelectTest = CurrState == STATE_INIT_TEST; - assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST; - assign DCacheFlushStart = CurrState == STATE_COPY_RAM; // fsm reset counter counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); @@ -275,7 +271,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin + if (dut.core.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -324,7 +320,6 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation //////////////////////////////////////////////////////////////////////////////// -/* -----\/----- EXCLUDED -----\/----- integer adrindex; always @(posedge clk) begin if (ResetMem) // program memory is sometimes reset @@ -344,50 +339,13 @@ module testbench; end end end - -----/\----- EXCLUDED -----/\----- */ - // still not working in this format -/* -----\/----- EXCLUDED -----\/----- - integer adrindex; - if (P.UNCORE_RAM_SUPPORTED) begin - always @(posedge clk) begin - if (ResetMem) // program memory is sometimes reset - for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; - end - end - - genvar adrindex2; - - if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0; - end - end - - if (P.BPRED_SUPPORTED) begin - always @(posedge clk) - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0; - for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0; - end - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0; - end - end - -----/\----- EXCLUDED -----/\----- */ - //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - - integer IndexTemp; - if (P.SDC_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin + always @(posedge clk) begin + if (LoadMem) begin + if (P.SDC_SUPPORTED) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; @@ -395,41 +353,13 @@ module testbench; //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; - end + end + else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); end - end else if (P.IROM_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - end - end - end else if (P.BUS_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - end - if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; - end - end - end - end - if (P.DTIM_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); - $display("Read memfile %s", memfilename); - end - if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp]; - end - end - end - end + end //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -519,15 +449,14 @@ module testbench; logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; - assign TestComplete = ecf & + assign DCacheFlushStart = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - //assign DCacheFlushStart = TestComplete; - + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); task automatic CheckSignature; @@ -579,24 +508,15 @@ module testbench; testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); /* verilator lint_off INFINITELOOP */ - /* verilator lint_off WIDTHXZEXPAND */ while (signature[i] !== 'bx) begin - /* verilator lint_on WIDTHXZEXPAND */ logic [P.XLEN-1:0] sig; - // ************************************** - // ***** BUG BUG BUG make sure RT undoes this. - //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); - //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin - if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin + if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - //$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h", - // TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]); $stop; //***debug end i = i + 1; From 9de434a61bc95f9effa262c8f0a5bfbaa95d7ea6 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 12:05:25 -0600 Subject: [PATCH 09/14] "Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis. --- src/generic/mem/ram1p1rwbe.sv | 2 +- src/uncore/ram_ahb.sv | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4af3c255c..95572228a 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE output logic [WIDTH-1:0] dout ); - logic [WIDTH-1:0] RAM[DEPTH-1:0]; + bit [WIDTH-1:0] RAM[DEPTH-1:0]; // *************************************************************************** // TRUE SRAM macro diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index f78998d9d..896c2a4cb 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -51,7 +51,6 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, logic memwrite, memwriteD, memread; logic nextHREADYRam; logic DelayReady; - logic [P.XLEN-1:0] HRDATA2; // a new AHB transactions starts when HTRANS requests a transaction, // the peripheral is selected, and the previous transaction is completing @@ -73,13 +72,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, // single-ported RAM ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1), - .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HRDATA2)); - - //assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2; - // **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues. - // PRIV sv48-svadu test not working without it. - //assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; - assign HREADRam = HRDATA2; + .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness if(`RAM_LATENCY > 0) begin From a8ab3c8342f3cea47dd787d599844ba5b7c481e3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 12:25:34 -0600 Subject: [PATCH 10/14] Ok that is a stange bug. The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue. --- testbench/common/DCacheFlushFSM.sv | 2 +- testbench/testbench.sv | 116 ++++++++++++++++++++++++----- 2 files changed, 99 insertions(+), 19 deletions(-) diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 152aaa173..1f41968c3 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -35,7 +35,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) genvar adr; - logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; + bit [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; logic startD; if(P.DCACHE_SUPPORTED) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ece7500d5..3607a5f06 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -85,7 +85,7 @@ module testbench; logic riscofTest; logic Validate; logic SelectTest; - + logic TestComplete; // pick tests based on modes supported initial begin @@ -176,6 +176,7 @@ module testbench; STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, + STATE_COPY_RAM, STATE_CHECK_TEST, STATE_CHECK_TEST_WAIT, STATE_VALIDATE, @@ -218,8 +219,9 @@ module testbench; STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; else NextState = STATE_RUN_TEST; - STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; + STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM; else NextState = STATE_RUN_TEST; + STATE_COPY_RAM: NextState = STATE_CHECK_TEST; STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; else NextState = STATE_CHECK_TEST_WAIT; STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; @@ -240,6 +242,8 @@ module testbench; assign ResetCntEn = CurrState == STATE_RESET_TEST; assign Validate = CurrState == STATE_VALIDATE; assign SelectTest = CurrState == STATE_INIT_TEST; + assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST; + assign DCacheFlushStart = CurrState == STATE_COPY_RAM; // fsm reset counter counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); @@ -271,7 +275,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (TEST == "coremark") - if (dut.core.EcallFaultM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -320,6 +324,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation //////////////////////////////////////////////////////////////////////////////// +/* -----\/----- EXCLUDED -----\/----- integer adrindex; always @(posedge clk) begin if (ResetMem) // program memory is sometimes reset @@ -339,13 +344,50 @@ module testbench; end end end + -----/\----- EXCLUDED -----/\----- */ + // still not working in this format +/* -----\/----- EXCLUDED -----\/----- + integer adrindex; + if (P.UNCORE_RAM_SUPPORTED) begin + always @(posedge clk) begin + if (ResetMem) // program memory is sometimes reset + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + end + end + + genvar adrindex2; + + if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin + for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0; + end + end + + if (P.BPRED_SUPPORTED) begin + always @(posedge clk) + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0; + for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0; + end + for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0; + end + end + -----/\----- EXCLUDED -----/\----- */ + //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - always @(posedge clk) begin - if (LoadMem) begin - if (P.SDC_SUPPORTED) begin + + integer IndexTemp; + if (P.SDC_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; @@ -353,13 +395,41 @@ module testbench; //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; - end - else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); - $display("Read memfile %s", memfilename); + end end - end + end else if (P.IROM_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + end + end + end else if (P.BUS_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + end + if (CopyRAM) begin + for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin + //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. + testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; + end + end + end + end + if (P.DTIM_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); + end + if (CopyRAM) begin + for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin + //if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. + testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp]; + end + end + end + end //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -449,14 +519,15 @@ module testbench; logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; - assign DCacheFlushStart = ecf & + assign TestComplete = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + //assign DCacheFlushStart = TestComplete; + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); task automatic CheckSignature; @@ -508,15 +579,24 @@ module testbench; testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); /* verilator lint_off INFINITELOOP */ + /* verilator lint_off WIDTHXZEXPAND */ while (signature[i] !== 'bx) begin + /* verilator lint_on WIDTHXZEXPAND */ logic [P.XLEN-1:0] sig; - if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + // ************************************** + // ***** BUG BUG BUG make sure RT undoes this. + //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); - if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin + //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin + if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); + //$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h", + // TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]); $stop; //***debug end i = i + 1; From 18a96740d5686bfbe0330f0c9858754a4931eecd Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 13:10:20 -0600 Subject: [PATCH 11/14] Revert RAM logic to bit change. Added logic to hptw to prevent x propagation. --- src/generic/mem/ram1p1rwbe.sv | 2 +- src/mmu/hptw.sv | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 95572228a..4af3c255c 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE output logic [WIDTH-1:0] dout ); - bit [WIDTH-1:0] RAM[DEPTH-1:0]; + logic [WIDTH-1:0] RAM[DEPTH-1:0]; // *************************************************************************** // TRUE SRAM macro diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index ab5e571c8..80e4fc9f0 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -102,7 +102,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay; logic HPTWAccessFaultDelay; logic TakeHPTWFault, TakeHPTWFaultDelay; - + logic [P.XLEN-1:0] ReadDataNoXM; + // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; @@ -154,7 +155,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0 + assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation. + mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); assign SaveHPTWAdr = WalkerState == L0_ADR; @@ -190,7 +192,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 end else begin // block: hptwwrites - assign NextPTE = ReadDataM; + assign NextPTE = ReadDataNoXM; assign HPTWAdr = HPTWReadAdr; assign HPTWUpdateDA = '0; assign UpdatePTE = '0; From b68dd74f89692f4c5c37d3745b502b56269807c5 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 13:16:32 -0600 Subject: [PATCH 12/14] Reverted logic to bit change. --- src/mmu/hptw.sv | 2 +- testbench/common/DCacheFlushFSM.sv | 2 +- testbench/testbench.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 80e4fc9f0..322a730dd 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -155,7 +155,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation. + assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 1f41968c3..152aaa173 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -35,7 +35,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) genvar adr; - bit [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; + logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; logic startD; if(P.DCACHE_SUPPORTED) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3607a5f06..3166383dc 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -187,7 +187,7 @@ module testbench; logic LoadMem; logic ResetCntEn; logic ResetCntRst; - + logic CopyRAM; string signame, memfilename, pathname; integer begin_signature_addr; From 1b59182d59d894688bd1823f1c872407c5cd427e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 14:55:37 -0600 Subject: [PATCH 13/14] Updated tests with ending label. --- testbench/testbench.sv | 102 ++++++------------ .../rv32i_m/D/src/WALLY-fld-01.S | 4 + .../riscv-test-suite/rv32i_m/I/src/E-add-01.S | 3 + .../rv32i_m/I/src/E-addi-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-and-01.S | 3 + .../rv32i_m/I/src/E-andi-01.S | 3 + .../rv32i_m/I/src/E-auipc-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-beq-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-bge-01.S | 3 + .../rv32i_m/I/src/E-bgeu-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-blt-01.S | 3 + .../rv32i_m/I/src/E-bltu-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-bne-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-jal-01.S | 3 + .../rv32i_m/I/src/E-jalr-01.S | 3 + .../rv32i_m/I/src/E-lb-align-01.S | 3 + .../rv32i_m/I/src/E-lbu-align-01.S | 3 + .../rv32i_m/I/src/E-lh-align-01.S | 3 + .../rv32i_m/I/src/E-lhu-align-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-lui-01.S | 3 + .../rv32i_m/I/src/E-lw-align-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-or-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-ori-01.S | 3 + .../rv32i_m/I/src/E-sb-align-01.S | 3 + .../rv32i_m/I/src/E-sh-align-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-sll-01.S | 3 + .../rv32i_m/I/src/E-slli-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-slt-01.S | 3 + .../rv32i_m/I/src/E-slti-01.S | 3 + .../rv32i_m/I/src/E-sltiu-01.S | 3 + .../rv32i_m/I/src/E-sltu-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-sra-01.S | 3 + .../rv32i_m/I/src/E-srai-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-srl-01.S | 3 + .../rv32i_m/I/src/E-srli-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-sub-01.S | 3 + .../rv32i_m/I/src/E-sw-align-01.S | 3 + .../riscv-test-suite/rv32i_m/I/src/E-xor-01.S | 3 + .../rv32i_m/I/src/E-xori-01.S | 3 + .../rv32i_m/I/src/WALLY-ADD.S | 3 + .../rv32i_m/I/src/WALLY-SLT.S | 3 + .../rv32i_m/I/src/WALLY-SLTU.S | 3 + .../rv32i_m/I/src/WALLY-SUB.S | 3 + .../rv32i_m/I/src/WALLY-XOR.S | 3 + .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 3 + .../rv32i_m/privilege/src/WALLY-cbom-01.S | 3 + .../rv32i_m/privilege/src/WALLY-cboz-01.S | 4 +- .../rv32i_m/privilege/src/WALLY-lrsc-01.S | 3 + .../rv32i_m/privilege/src/WALLY-periph-01.S | 3 + .../rv64i_m/I/src/WALLY-ADD.S | 3 + .../rv64i_m/I/src/WALLY-SLT.S | 3 + .../rv64i_m/I/src/WALLY-SLTU.S | 3 + .../rv64i_m/I/src/WALLY-SUB.S | 3 + .../rv64i_m/I/src/WALLY-XOR.S | 3 + .../rv64i_m/K_unratified/src/aes64ds-01.S | 3 + .../rv64i_m/K_unratified/src/aes64ds-rwp1.S | 3 + .../rv64i_m/K_unratified/src/aes64dsm-01.S | 3 + .../rv64i_m/K_unratified/src/aes64dsm-rwp1.S | 3 + .../rv64i_m/K_unratified/src/aes64es-01.S | 3 + .../rv64i_m/K_unratified/src/aes64es-rwp1.S | 3 + .../rv64i_m/K_unratified/src/aes64esm-01.S | 3 + .../rv64i_m/K_unratified/src/aes64esm-rwp1.S | 3 + .../rv64i_m/K_unratified/src/aes64im-01.S | 3 + .../rv64i_m/K_unratified/src/aes64im-rwp1.S | 3 + .../rv64i_m/K_unratified/src/aes64im-rwp2.S | 3 + .../rv64i_m/K_unratified/src/aes64ks1i-01.S | 3 + .../rv64i_m/K_unratified/src/aes64ks2-01.S | 3 + .../rv64i_m/K_unratified/src/andn-01.S | 3 + .../rv64i_m/K_unratified/src/clmul-01.S | 3 + .../rv64i_m/K_unratified/src/clmulh-01.S | 3 + .../rv64i_m/K_unratified/src/orn-01.S | 3 + .../rv64i_m/K_unratified/src/pack-01.S | 3 + .../rv64i_m/K_unratified/src/packh-01.S | 3 + .../rv64i_m/K_unratified/src/packu-01.S | 3 + .../rv64i_m/K_unratified/src/packuw-01.S | 3 + .../rv64i_m/K_unratified/src/packw-01.S | 3 + .../rv64i_m/K_unratified/src/rev.b-01.S | 3 + .../rv64i_m/K_unratified/src/rev8-01.S | 3 + .../rv64i_m/K_unratified/src/rev8.w-01.S | 3 + .../rv64i_m/K_unratified/src/rol-01.S | 3 + .../rv64i_m/K_unratified/src/rolw-01.S | 3 + .../rv64i_m/K_unratified/src/ror-01.S | 3 + .../rv64i_m/K_unratified/src/rori-01.S | 3 + .../rv64i_m/K_unratified/src/roriw-01.S | 3 + .../rv64i_m/K_unratified/src/rorw-01.S | 3 + .../rv64i_m/K_unratified/src/sha256sig0-01.S | 3 + .../K_unratified/src/sha256sig0-rwp1.S | 3 + .../K_unratified/src/sha256sig0-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha256sig1-01.S | 3 + .../K_unratified/src/sha256sig1-rwp1.S | 3 + .../K_unratified/src/sha256sig1-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha256sum0-01.S | 3 + .../K_unratified/src/sha256sum0-rwp1.S | 3 + .../K_unratified/src/sha256sum0-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha256sum1-01.S | 3 + .../K_unratified/src/sha256sum1-rwp1.S | 3 + .../K_unratified/src/sha256sum1-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha512sig0-01.S | 3 + .../K_unratified/src/sha512sig0-rwp1.S | 3 + .../K_unratified/src/sha512sig0-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha512sig1-01.S | 3 + .../K_unratified/src/sha512sig1-rwp1.S | 3 + .../K_unratified/src/sha512sig1-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha512sum0-01.S | 3 + .../K_unratified/src/sha512sum0-rwp1.S | 3 + .../K_unratified/src/sha512sum0-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sha512sum1-01.S | 3 + .../K_unratified/src/sha512sum1-rwp1.S | 3 + .../K_unratified/src/sha512sum1-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sm3p0-01.S | 3 + .../rv64i_m/K_unratified/src/sm3p0-rwp1.S | 3 + .../rv64i_m/K_unratified/src/sm3p0-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sm3p1-01.S | 3 + .../rv64i_m/K_unratified/src/sm3p1-rwp1.S | 3 + .../rv64i_m/K_unratified/src/sm3p1-rwp2.S | 3 + .../rv64i_m/K_unratified/src/sm4ed-01.S | 3 + .../rv64i_m/K_unratified/src/sm4ed-rwp1.S | 3 + .../rv64i_m/K_unratified/src/sm4ks-01.S | 3 + .../rv64i_m/K_unratified/src/sm4ks-rwp1.S | 3 + .../rv64i_m/K_unratified/src/xnor-01.S | 3 + .../rv64i_m/K_unratified/src/xperm.b-01.S | 3 + .../rv64i_m/K_unratified/src/xperm.n-01.S | 3 + .../rv64i_m/Zifencei/src/Fencei.S | 3 + .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 3 + .../rv64i_m/privilege/src/WALLY-cbom-01.S | 3 + .../rv64i_m/privilege/src/WALLY-cboz-01.S | 3 + .../rv64i_m/privilege/src/WALLY-lrsc-01.S | 3 + .../src/WALLY-misaligned-access-01.S | 3 + 128 files changed, 414 insertions(+), 71 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3166383dc..6bce57714 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -37,7 +37,7 @@ module testbench; parameter DEBUG=0; parameter TEST="none"; parameter PrintHPMCounters=0; - parameter BPRED_LOGGER=1; + parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; @@ -190,7 +190,7 @@ module testbench; logic CopyRAM; string signame, memfilename, pathname; - integer begin_signature_addr; + integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -253,6 +253,8 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// logic [P.XLEN-1:0] testadr; assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; + assign signature_size = end_signature_addr - begin_signature_addr; always @(posedge clk) begin if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; @@ -321,70 +323,15 @@ module testbench; end - //////////////////////////////////////////////////////////////////////////////// - // Some memories are not reset, but should be zeros or set to some initial value for simulation - //////////////////////////////////////////////////////////////////////////////// -/* -----\/----- EXCLUDED -----\/----- - integer adrindex; - always @(posedge clk) begin - if (ResetMem) // program memory is sometimes reset - if (P.UNCORE_RAM_SUPPORTED) - for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; - if(reset) begin // branch predictor must always be reset - if (P.BPRED_SUPPORTED) begin - // local history only - if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) - for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; - for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - end - end - end - -----/\----- EXCLUDED -----/\----- */ - - // still not working in this format -/* -----\/----- EXCLUDED -----\/----- - integer adrindex; - if (P.UNCORE_RAM_SUPPORTED) begin - always @(posedge clk) begin - if (ResetMem) // program memory is sometimes reset - for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; - end - end - - genvar adrindex2; - - if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0; - end - end - - if (P.BPRED_SUPPORTED) begin - always @(posedge clk) - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0; - for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0; - end - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0; - end - end - -----/\----- EXCLUDED -----/\----- */ - //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - integer IndexTemp; + integer ShadowIndex; + integer LogXLEN; + integer StartIndex; + integer EndIndex; + integer BaseIndex; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -403,15 +350,20 @@ module testbench; $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); end end - end else if (P.BUS_SUPPORTED) begin + end else if (P.BUS_SUPPORTED) begin : bus_supported always @(posedge clk) begin if (LoadMem) begin $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); end if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; + LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64 + StartIndex = begin_signature_addr >> LogXLEN; + EndIndex = (end_signature_addr >> LogXLEN) + 8; + BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; + $display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x", + begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN); + for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; end end end @@ -423,9 +375,14 @@ module testbench; $display("Read memfile %s", memfilename); end if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp]; + LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64 + StartIndex = begin_signature_addr >> LogXLEN; + EndIndex = (end_signature_addr >> LogXLEN) + 8; + BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; + $display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x", + begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN); + for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex]; end end end @@ -626,14 +583,15 @@ task automatic updateProgramAddrLabelArray; inout integer ProgramAddrLabelArray [string]; // Gets the memory location of begin_signature integer ProgramLabelMapFP, ProgramAddrMapFP; + ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); - if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files // *** RT: I'm a bit confused by the required initialization here. ProgramAddrLabelArray["begin_signature"] = 0; ProgramAddrLabelArray["tohost"] = 0; + ProgramAddrLabelArray["sig_end_canary"] = 0; while (!$feof(ProgramLabelMapFP)) begin string label, adrstr; integer returncode; @@ -642,6 +600,10 @@ task automatic updateProgramAddrLabelArray; if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex(); end end + + if(ProgramAddrLabelArray["begin"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile); + if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile); + $fclose(ProgramLabelMapFP); $fclose(ProgramAddrMapFP); /* verilator lint_on WIDTHTRUNC */ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S index 79b1c963e..498c68fce 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S @@ -76,6 +76,10 @@ gpr_save: #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: + RVMODEL_DATA_END // ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S // David_Harris@hmc.edu & Katherine Parry diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S index 4abf30fdf..a85ce8b44 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S @@ -2997,5 +2997,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S index 87ce8463e..619bf6f28 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S @@ -2887,5 +2887,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S index dca83d0f0..b768ec1bb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S @@ -3022,5 +3022,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S index 2114d6aee..212178e6a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S @@ -2847,5 +2847,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S index 517a4b8d1..6ce10b6f1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S @@ -387,5 +387,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S index 946402467..4b9c621f1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S @@ -3027,5 +3027,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S index d8cd00477..45da8a3c6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S @@ -3012,5 +3012,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S index 43bf2ec72..e4d89fc09 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S @@ -3717,5 +3717,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S index a23350a44..540d301aa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S @@ -3007,5 +3007,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S index e6e5b69ac..ef04e47c0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S @@ -3712,5 +3712,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S index 92ccd2b4f..faccec958 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S @@ -3007,5 +3007,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S index 2fd3e9e2b..f351234d6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S @@ -152,5 +152,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S index c8ac34760..1b0e15adf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S @@ -212,5 +212,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S index d42f83ccd..88f7d876e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S @@ -162,5 +162,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S index bc2c0527d..069c91382 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S @@ -162,5 +162,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S index e16cb695d..9ca986ac7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S @@ -152,5 +152,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S index 9e4427ca5..4676f9265 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S @@ -157,5 +157,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S index f1257005f..ef879ec4d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S @@ -387,5 +387,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S index e1f368a9b..f3429cd11 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S @@ -157,5 +157,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S index 193785007..2e944e959 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S @@ -3032,5 +3032,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S index 3c8078862..9a2ef6651 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S @@ -2862,5 +2862,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S index 3eaf9072c..9fc9f1ca9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S @@ -462,5 +462,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S index 86d7c2781..17354ee56 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S @@ -432,5 +432,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S index f219b7af4..3aedb337b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S @@ -517,5 +517,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S index 754c14a5d..e098b8b32 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S @@ -522,5 +522,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S index f7c57a553..be7255504 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S @@ -2987,5 +2987,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S index c0a3feccd..f079caf72 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S @@ -2887,5 +2887,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S index 79336c4f0..1d2ea3fb4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S @@ -3562,5 +3562,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S index b28398c3d..c6bbf7514 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S @@ -3692,5 +3692,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S index 7e3e8c253..cd357fa37 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S @@ -527,5 +527,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S index e87f2b740..79cc17757 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S @@ -512,5 +512,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S index 80f27c5fd..d8121944f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S @@ -522,5 +522,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S index 8ecc2f5dc..d45ea9d47 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S @@ -517,5 +517,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S index 60ce1b737..e8ef3b8b3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S @@ -3002,5 +3002,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S index 71dd41b89..52e2eb629 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S @@ -412,5 +412,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S index 41fa0ac9d..cd622faac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S @@ -2997,5 +2997,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S index cc3f509f7..ecb6fac25 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S @@ -2877,5 +2877,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S index 9b6561514..b07384e00 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S @@ -132,6 +132,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S index 10e5bc509..8f7269e7f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S index aa080daf9..2c8dab781 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S index b7f5fa299..70bb79ef8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S index ea658637d..884d8c1a3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index abbfbaf56..654c13568 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1428,6 +1428,9 @@ RVMODEL_DATA_BEGIN test_1_res: .fill 1024, 4, 0xdeadbeef +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END #ifdef rvtest_mtrap_routine diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S index b4d4bae3c..2edd1fc55 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S @@ -468,5 +468,8 @@ Destination3: signature: .fill 16, 4, 0x0bad0bad +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S index 92e046bd1..ceb3c3603 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S @@ -372,6 +372,8 @@ Destination2: .fill 16, 4, 0xdeadbeef signature: .fill 16, 4, 0x0bad0bad - +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S index 2ea73ed35..4b4968be9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S @@ -113,4 +113,7 @@ RVMODEL_DATA_BEGIN # signature output wally_signature: .fill 6, 4, -1 +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S index 4c06a2def..3789f9683 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S @@ -917,4 +917,7 @@ RVMODEL_DATA_BEGIN # signature output wally_signature: .fill 0x200, 8, 0x00000000 +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S index ed51aca50..26b2f501c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S index 134bfe2aa..8dd500f83 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S index d3671a1e5..0aec30e56 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S index bd71d8ba0..1157c194c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S index b91ba798f..949672e42 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S @@ -133,6 +133,9 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S index 1b573f563..a1ffd16e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S @@ -360,5 +360,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S index 652fdcad2..dd41ee1d5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S @@ -385,5 +385,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S index d01a79487..c6522eb85 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S @@ -360,5 +360,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S index 9895fdffb..09a5cc8b1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S @@ -385,5 +385,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S index e870378f8..d5347e4f1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S @@ -360,5 +360,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S index 135f6a5e5..9a08f8ffa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S @@ -385,5 +385,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S index b623390e8..bbb646755 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S @@ -360,5 +360,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S index 1f01ceffc..2cd8b297e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S @@ -385,5 +385,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S index f926ced17..0659bd0e9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S index d827a5915..63d15021a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S index 281316aa8..4dbb06c87 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S index 193161514..7616326ea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S @@ -505,5 +505,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S index 3f40ce4aa..9385c36a9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S @@ -1180,5 +1180,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S index daf30b85d..49b72ae25 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S index e46e5636f..611aca7cb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S index aac8a1997..937e4980c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S @@ -2712,5 +2712,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S index 2c76117d3..1903398fe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S @@ -2712,5 +2712,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S index 65270346f..ee1995cf4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S @@ -2702,5 +2702,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S index f25688408..ac7884aad 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S index 6e96f15cd..25dcba909 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S @@ -2692,5 +2692,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S index 84bc2ca74..bd8e00ea1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S index 842dead52..decb80d53 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S index ed52f53dc..42d68e344 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S @@ -2157,5 +2157,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S index 1a0dcaf50..e3f8a7ef4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S @@ -2157,5 +2157,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S index b9e5d6ab1..8e57a59d8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S @@ -2157,5 +2157,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S index 945868cea..2854f2b96 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S @@ -2712,5 +2712,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S index f34961f3b..1b5351ee5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S index e54d69fae..bec81a1db 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S index 64b60a7f1..91b414049 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S @@ -1527,5 +1527,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S index f9d6a21ac..1270e98d0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S @@ -1512,5 +1512,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S index c38ced3ae..96c1d8dbe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S index 36a20d1fb..5951cc45a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S index 6e17b1d87..48e3f05ba 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S index df040e50b..cd1f76563 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S index 11c729bef..be943441c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S index 23e180ee9..7d147a4bb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S index b06950bd4..c7a7474fa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S index bd40a36ac..65f752670 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S index 77c5577fe..373c688b0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S index 3e3c833f0..511778482 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S index 7c84af1fc..7854abe88 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S index 834741471..bc46f31db 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S index 8e2c36a0d..4d057d447 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S index 654ce3e25..e85415807 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S index 93a6a38a7..0e6d8f686 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S index 2eea575e1..bd25a3831 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S index 200d8a8a1..92ef9a051 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S index e5e7ee37a..7daf6c2b1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S index b7bfa3a9e..c31ee9218 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S index 6c75a3a32..fe3419c44 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S index 4d71aa33d..36cc0c412 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S index e1d7d2bc3..82a40511c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S index d1bdc6f12..bb011edc6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S index 0ef60a2ef..97d184445 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S index 318e75df2..faf0a53cf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S index 73a31131f..5fcf4fec6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S index 72c238d3f..db0556e96 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S index c567bd969..6975f3f44 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S index 77423add8..e2c42c26a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S @@ -1275,5 +1275,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S index 80d605ce8..34a1d2f6f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S @@ -965,5 +965,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S index 5a4aa340b..62b003137 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S @@ -300,5 +300,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S index 5b11998a0..b9b5b5d47 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S @@ -1485,5 +1485,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S index ccd7d481e..a0a9d7a3f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S @@ -411,5 +411,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S index b6a43b991..abc13221d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S @@ -1485,5 +1485,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S index 8cb95a8bb..05b2330ac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S @@ -411,5 +411,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S index e8675ad95..3e48b21d3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S @@ -2707,5 +2707,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S index 5f1f7e668..de93a7a4e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S @@ -2812,5 +2812,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S index 1f02df067..c822eb12c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S @@ -2812,5 +2812,8 @@ gpr_save: .fill 32*(XLEN/32),4,0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S index 330ea5c63..01773ae04 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S @@ -93,4 +93,7 @@ gpr_save: .fill 32*(XLEN/32), 4, 0xdeadbeef #endif +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 67d76c6ab..d939c130e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -1463,6 +1463,9 @@ RVMODEL_DATA_BEGIN test_1_res: .fill 1024, 4, 0xdeadbeef +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END #ifdef rvtest_mtrap_routine diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index f8725e08b..31b11874b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -625,6 +625,9 @@ Destination3: .fill 128, 4, 0xdeadbeef signature: .fill 44, 4, 0x0bad0bad +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S index 1fe3e120b..97c3946eb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S @@ -372,6 +372,9 @@ Destination2: .fill 16, 4, 0xdeadbeef signature: .fill 32, 4, 0x0bad0bad +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S index fd8b6ceaa..6258b0807 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S @@ -135,4 +135,7 @@ RVMODEL_DATA_BEGIN wally_signature: .fill 12, 8, -1 +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S index 3ff89a237..a831df75a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S @@ -747,6 +747,9 @@ Double7DstData: signature: .fill 225, 1, 0x00 +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S // David_Harris@hmc.edu & Katherine Parry From 70d0169019d5ff974b726084c7fe409708aa3f59 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 14:57:52 -0600 Subject: [PATCH 14/14] All regression tests which matter are running! --- testbench/testbench.sv | 4 ---- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 6bce57714..3f7aeea33 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -360,8 +360,6 @@ module testbench; StartIndex = begin_signature_addr >> LogXLEN; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; - $display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x", - begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN); for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; end @@ -379,8 +377,6 @@ module testbench; StartIndex = begin_signature_addr >> LogXLEN; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; - $display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x", - begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN); for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex]; end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S index 6c985c98b..dc6dde0af 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S @@ -917,4 +917,7 @@ RVMODEL_DATA_BEGIN # signature output wally_signature: .fill 0x200, 8, 0x00000000 +sig_end_canary: +.int 0x0 +rvtest_sig_end: RVMODEL_DATA_END