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Update irom.sv

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Program clean up
This commit is contained in:
Harshini Srinath 2023-06-12 12:44:09 -07:00 committed by GitHub
parent a5561c2cf6
commit 19e8acff70
1 changed files with 6 additions and 8 deletions
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14
src/ifu/irom.sv
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@ -25,10 +25,10 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module irom import cvw::*; #(parameter cvw_t P) ( module irom import cvw::*; #(parameter cvw_t P) (
input logic clk, input logic clk,
input logic ce, // Chip Enable. 0: Holds IROMInstrF constant input logic ce, // Chip Enable. 0: Holds IROMInstrF constant
input logic [P.XLEN-1:0] Adr, // PCNextFSpill input logic [P.XLEN-1:0] Adr, // PCNextFSpill
output logic [31:0] IROMInstrF // Instruction read data output logic [31:0] IROMInstrF // Instruction read data
); );
localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width
@ -36,14 +36,13 @@ module irom import cvw::*; #(parameter cvw_t P) (
localparam OFFSET = $clog2(XLENBYTES); localparam OFFSET = $clog2(XLENBYTES);
logic [P.XLEN-1:0] IROMInstrFFull; logic [P.XLEN-1:0] IROMInstrFFull;
logic [31:0] RawIROMInstrF; logic [31:0] RawIROMInstrF;
logic [1:0] AdrD;
logic [1:0] AdrD;
flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD); flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull; if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
else begin else begin
// IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two // IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two
// haves. Adr is the Next PCF not PCF so we delay 1 cycle. // haves. Adr is the Next PCF not PCF so we delay 1 cycle.
assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0]; assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
@ -52,4 +51,3 @@ module irom import cvw::*; #(parameter cvw_t P) (
// The spill logic will handle merging the two together. // The spill logic will handle merging the two together.
assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF; assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
endmodule endmodule