From 19e8acff70359a1f597a5736d4df75c2f6df1ed6 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Mon, 12 Jun 2023 12:44:09 -0700 Subject: [PATCH] Update irom.sv Program clean up --- src/ifu/irom.sv | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 321dd9fa8..1339c26fa 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -25,10 +25,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module irom import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic ce, // Chip Enable. 0: Holds IROMInstrF constant + input logic clk, + input logic ce, // Chip Enable. 0: Holds IROMInstrF constant input logic [P.XLEN-1:0] Adr, // PCNextFSpill - output logic [31:0] IROMInstrF // Instruction read data + output logic [31:0] IROMInstrF // Instruction read data ); localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width @@ -36,14 +36,13 @@ module irom import cvw::*; #(parameter cvw_t P) ( localparam OFFSET = $clog2(XLENBYTES); logic [P.XLEN-1:0] IROMInstrFFull; - logic [31:0] RawIROMInstrF; - - logic [1:0] AdrD; + logic [31:0] RawIROMInstrF; + logic [1:0] AdrD; flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD); rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull; - else begin + else begin // IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two // haves. Adr is the Next PCF not PCF so we delay 1 cycle. assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0]; @@ -52,4 +51,3 @@ module irom import cvw::*; #(parameter cvw_t P) ( // The spill logic will handle merging the two together. assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF; endmodule -