From b692c913c4908bbaf7e3407727681eb216c69f0b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 18 Nov 2023 20:56:50 -0800 Subject: [PATCH 1/3] Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile --- config/rv32gc/config.vh | 2 +- synthDC/Makefile | 4 ++-- synthDC/extractSummary.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index e095e6252..52baad796 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -169,7 +169,7 @@ localparam ZMMUL_SUPPORTED = 0; // FPU division architecture localparam RADIX = 32'd4; -localparam DIVCOPIES = 32'd4; +localparam DIVCOPIES = 32'd2; // bit manipulation localparam ZBA_SUPPORTED = 1; diff --git a/synthDC/Makefile b/synthDC/Makefile index 2183cab83..7968a7b52 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -94,10 +94,10 @@ endif ifneq ($(MOD), orig) # PMP 0 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh + sed -i 's/PMP_ENTRIES.*\(64\|16\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh ifneq ($(MOD), PMP0) # no priv - sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh + sed -i 's/ZICSR_SUPPORTED.*1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh ifneq ($(MOD), noPriv) # turn off FPU sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/config.vh diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 7a3f45ddd..d6f5933a9 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -252,7 +252,7 @@ if __name__ == '__main__': TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") techdict = {} - techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 1440.600027, 714.057, 0.658023) + techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 2581, 18, 0.685) techdict['sky90'] = TechSpec('gray', 'o', args.sky90freq, 43.2e-3, 1440.600027, 714.057, 0.658023) techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) From 887cf935dce54c77af64f71ca6d49cbb6e012f6c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Nov 2023 06:49:07 -0800 Subject: [PATCH 2/3] wallySynthAll.sh automates running all synthesis experiments without maxopt --- benchmarks/embench/embench_arch_sweep.py | 7 ++++--- synthDC/wallySynthAll.sh | 13 +++++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) create mode 100755 synthDC/wallySynthAll.sh diff --git a/benchmarks/embench/embench_arch_sweep.py b/benchmarks/embench/embench_arch_sweep.py index ad629320a..130a70581 100755 --- a/benchmarks/embench/embench_arch_sweep.py +++ b/benchmarks/embench/embench_arch_sweep.py @@ -10,7 +10,8 @@ from datetime import datetime import re import collections -archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"] +#archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"] +archs = ["rv32imafdc_zba_zbb_zbc_zbs_zicsr", "rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr"] def calcgeomean(d, arch): progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"] @@ -81,6 +82,6 @@ def run_arch_sweep(): os.system("mv -f wally"+res+".json "+dir+"/wally"+res+"_"+arch+".json") return dir -#directory = run_arch_sweep() -directory = "run_20231116_071322" +directory = run_arch_sweep() +#directory = "run_20231117_082325" tabulate_arch_sweep(directory) \ No newline at end of file diff --git a/synthDC/wallySynthAll.sh b/synthDC/wallySynthAll.sh new file mode 100755 index 000000000..9c085601c --- /dev/null +++ b/synthDC/wallySynthAll.sh @@ -0,0 +1,13 @@ +# Run all Wally synthesis experiments from chapter 8 +./wallySynth.py --freqsweep 330 --tech sky130 +./wallySynth.py --freqsweep 870 --tech sky90 +./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram +./wallySynth.py --configsweep --tech sky130 --targetfreq 330 +./wallySynth.py --configsweep --tech sky90 --targetfreq 870 +./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram +./wallySynth.py --featuresweep --tech sky130 --targetfreq 330 +./wallySynth.py --featuresweep --tech sky90 --targetfreq 870 +./wallySynth.py --featuresweep --tech tsmc28psyn --targetfreq 2800 --usesram +# Extract summary data (run this by hand after all experiments finish) +#./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800 + From 8cb433cb66045512b885d1f08335c8c4d39bc1b9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Nov 2023 19:33:57 -0800 Subject: [PATCH 3/3] Commented IROM preloading --- addins/riscv-arch-test | 2 +- src/generic/mem/rom1p1r.sv | 2 +- src/ifu/irom.sv | 4 +++- synthDC/wallySynthAll.sh | 7 ++++--- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 9f9bdd62d..eb0a38922 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 9f9bdd62d3e37fcd8ad1b1a39d71694ccf1d74f3 +Subproject commit eb0a3892215ad2384702db02da1551a59701ec67 diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 5a45e354a..617a779ff 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -47,7 +47,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) initial begin if (PRELOAD_ENABLED) begin - $readmemh("../../../fpga/src/boot.mem", ROM, 0); + $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0); end end diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 0d4286e43..0b29c72cf 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -39,7 +39,9 @@ module irom import cvw::*; #(parameter cvw_t P) ( logic [31:0] RawIROMInstrF; logic [2:1] AdrD; - rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); + // preload IROM with the FPGA bootloader by default so that it syntehsizes to something, avoiding having the IEU optimized away because instructions are all 0 + // the testbench replaces these dummy contents with the actual program of interest during simulation + rom1p1r #(ADDR_WDITH, P.XLEN, 1) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull)); if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull; else begin // IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two diff --git a/synthDC/wallySynthAll.sh b/synthDC/wallySynthAll.sh index 9c085601c..9af40a379 100755 --- a/synthDC/wallySynthAll.sh +++ b/synthDC/wallySynthAll.sh @@ -1,7 +1,8 @@ # Run all Wally synthesis experiments from chapter 8 -./wallySynth.py --freqsweep 330 --tech sky130 -./wallySynth.py --freqsweep 870 --tech sky90 -./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram +# However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail +#./wallySynth.py --freqsweep 330 --tech sky130 +#./wallySynth.py --freqsweep 870 --tech sky90 +#./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram ./wallySynth.py --configsweep --tech sky130 --targetfreq 330 ./wallySynth.py --configsweep --tech sky90 --targetfreq 870 ./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram