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Simplify FSM

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This commit is contained in:
David Harris 2022-08-29 04:32:27 -07:00
parent 6961e499dc
commit 16cde5f87e
1 changed files with 1 additions and 1 deletions
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pipelined/src/fpu/fdivsqrtfsm.sv
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@ -103,7 +103,7 @@ module fdivsqrtfsm(
if (SpecialCase) state <= #1 DONE;
else state <= #1 BUSY;
end else if (state == BUSY) begin
if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin
if ((step == 1) | WZero) begin
state <= #1 DONE;
end
step <= step - 1;