diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index c4780bcee..d506ad3b1 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -103,7 +103,7 @@ module fdivsqrtfsm(
           if (SpecialCase) state <= #1 DONE;
           else             state <= #1 BUSY;
       end else if (state == BUSY) begin
-          if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin
+          if ((step == 1) | WZero) begin
               state <= #1 DONE;
           end
           step <= step - 1;