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mergingMerge branch 'main' of github.com:Thomas-J-Kidd/cvw

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Thomas Kidd 2024-01-16 11:35:17 -06:00
commit 14a00041e7
27 changed files with 259 additions and 153 deletions
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21
bin/wally-tool-chain-install.sh
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@ -138,6 +138,27 @@ sudo make install
# package manager. Sail has so many dependencies that it can be difficult to install. # package manager. Sail has so many dependencies that it can be difficult to install.
# This script works for Ubuntu. # This script works for Ubuntu.
# Alex Solomatnikov found these commands worked to build Sail for Centos 8 on 1/12/24
#sudo su -
#dnf install ocaml.x86_64
#pip3 install z3-solver
#wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh
#sh install.sh
#opam init
#exit
#ocaml -version
#opam switch create 5.1.0
#eval $(opam config env)
#git clone --recurse-submodules git@github.com:riscv/sail-riscv.git
#cd sail-riscv
#make
#ARCH=RV32 make
#ARCH=RV64 make
#git log -1
#cp -p c_emulator/riscv_sim_RV* /tools/sail-riscv/d7a3d8012fd579f40e53a29569141d72dd5e0c32/bin/.
# This was an earlier attemp to prepare to install Sail on RedHat 8
# Do these commands only for RedHat / Rocky 8 to build from source. # Do these commands only for RedHat / Rocky 8 to build from source.
#cd $RISCV #cd $RISCV
#git clone https://github.com/Z3Prover/z3.git #git clone https://github.com/Z3Prover/z3.git

2
config/rv64gc/config.vh
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@ -107,7 +107,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0; localparam BOOTROM_PRELOAD = 1'b0;
localparam UNCORE_RAM_SUPPORTED = 1'b1; localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0; localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam EXT_MEM_SUPPORTED = 1'b0; localparam EXT_MEM_SUPPORTED = 1'b0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;

2
docs/Dockerfile
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@ -30,7 +30,7 @@ FROM debian
RUN apt update RUN apt update
# INSTALL # INSTALL
RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano RUN apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
RUN pip3 install chardet==3.0.4 RUN pip3 install chardet==3.0.4
RUN pip3 install urllib3==1.22 RUN pip3 install urllib3==1.22

2
examples/fp/softfloat_demo/Makefile
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@ -6,7 +6,7 @@ LFLAGS = -L.
# Link against the riscv-isa-sim version of SoftFloat rather than # Link against the riscv-isa-sim version of SoftFloat rather than
# the regular version to get RISC-V NaN behavior # the regular version to get RISC-V NaN behavior
#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat #IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a #LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
SRCS = $(wildcard *.c) SRCS = $(wildcard *.c)

7
examples/fp/softfloat_demo/softfloat_demoDP.c
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@ -38,16 +38,19 @@ void printF64 (char *msg, float64_t d) {
int i, j; int i, j;
conv.v = d.v; // use union to convert between hexadecimal and floating-point views conv.v = d.v; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d); printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
} }
void printF128 (char *msg, float128_t q) { void printF128 (char *msg, float128_t q) {
qp conv; qp conv;
int i, j; int i, j;
char buf[64];
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q); //printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);
} }
void printFlags(void) { void printFlags(void) {

13
examples/fp/softfloat_demo/softfloat_demoQP.c
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@ -38,16 +38,23 @@ void printF64 (char *msg, float64_t d) {
int i, j; int i, j;
conv.v = d.v; // use union to convert between hexadecimal and floating-point views conv.v = d.v; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d); printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
} }
void printF128 (char *msg, float128_t q) { void printF128 (char *msg, float128_t q) {
qp conv; qp conv;
int i, j; int i, j;
char buf[64];
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
// Some compilers can understand %Q for printf on quad precision instead of the
// API call of quadmath_snprintf
// printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);
} }
void printFlags(void) { void printFlags(void) {
@ -74,6 +81,8 @@ int main() {
float128_t x, y, z; float128_t x, y, z;
float128_t r; float128_t r;
uint32_t u, v, w;
int32_t a, b, c;
x.v[1] = 0xBFFF988ECE97DFEB; x.v[1] = 0xBFFF988ECE97DFEB;
x.v[0] = 0xC3BBA082445B4836; x.v[0] = 0xC3BBA082445B4836;

7
examples/fp/softfloat_demo/softfloat_demoSP.c
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@ -38,16 +38,19 @@ void printF64 (char *msg, float64_t d) {
int i, j; int i, j;
conv.v = d.v; // use union to convert between hexadecimal and floating-point views conv.v = d.v; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d); printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
} }
void printF128 (char *msg, float128_t q) { void printF128 (char *msg, float128_t q) {
qp conv; qp conv;
int i, j; int i, j;
char buf[64];
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
printf("%s: ", msg); // print out nicely printf("%s: ", msg); // print out nicely
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q); //printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);
} }
void printFlags(void) { void printFlags(void) {

3
setup.csh
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@ -46,4 +46,7 @@ extend PATH /usr/local/bin/verilator # Change this for your path to Verilator
#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) #set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas #setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
# Verilator needs a larger stack to simulate CORE-V Wally
limit stacksize unlimited
echo "setup done" echo "setup done"

2
src/fpu/fclassify.sv
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@ -37,7 +37,7 @@ module fclassify import cvw::*; #(parameter cvw_t P) (
); );
logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal
logic NInf, NZero, NNorm, NSubnorm; // is the input a negitive infinity/zero/normal/subnormal logic NInf, NZero, NNorm, NSubnorm; // is the input a negative infinity/zero/normal/subnormal
logic XNorm; // is the input normal logic XNorm; // is the input normal
// determine the sub categories // determine the sub categories

2
src/fpu/fctrl.sv
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@ -215,7 +215,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
// rounding modes: // rounding modes:
// 000 - round to nearest, ties to even // 000 - round to nearest, ties to even
// 001 - round twords 0 - round to min magnitude // 001 - round twords 0 - round to min magnitude
// 010 - round down - round twords negitive infinity // 010 - round down - round twords negative infinity
// 011 - round up - round twords positive infinity // 011 - round up - round twords positive infinity
// 100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero // 100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
// 111 - dynamic - choose FRM_REGW as rounding mode // 111 - dynamic - choose FRM_REGW as rounding mode

6
src/fpu/fcvt.sv
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@ -80,7 +80,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// negation // negation
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// 1) negate the input if the input is a negitive singed integer // 1) negate the input if the input is a negative singed integer
// 2) trim the input to the proper size (kill the 32 most significant zeroes if needed) // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed)
assign PosInt = Cs ? -Int : Int; assign PosInt = Cs ? -Int : Int;
@ -182,7 +182,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias}; assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
// find if the result is dnormal or underflows // find if the result is dnormal or underflows
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - if Calculated expoenent is 0 or negative (and the input/result is not exactaly 0)
// - can't underflow an integer to Fp conversion // - can't underflow an integer to Fp conversion
assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp; assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// shifter // shifter
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
// kill the shift if it's negitive // kill the shift if it's negative
// select the amount to shift by // select the amount to shift by
// fp -> int: // fp -> int:
// - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0

14
src/fpu/fma/fmaadd.sv
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@ -42,8 +42,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
output logic [3*P.NF+3:0] Sm // the positive sum output logic [3*P.NF+3:0] Sm // the positive sum
); );
logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negative sum
logic NegSum; // was the sum negitive logic NegSum; // was the sum negative
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Addition // Addition
@ -54,8 +54,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
// Kill the product if the product is too small to effect the addition (determined in fma1.sv) // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
assign PmKilled = {2*P.NF+2{~KillProd}}&Pm; assign PmKilled = {2*P.NF+2{~KillProd}}&Pm;
// Do the addition // Do the addition
// - calculate a positive and negitive sum in parallel // - calculate a positive and negative sum in parallel
// if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum // if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum
// prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation // prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation
// ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA // ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA
// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation // addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
@ -66,10 +66,10 @@ module fmaadd import cvw::*; #(parameter cvw_t P) (
// Choose the positive sum and accompanying LZA result. // Choose the positive sum and accompanying LZA result.
assign Sm = NegSum ? NegPreSum : PreSum; assign Sm = NegSum ? NegPreSum : PreSum;
// is the result negitive // is the result negative
// if p - z is the Sum negitive // if p - z is the Sum negative
// if -p + z is the Sum positive // if -p + z is the Sum positive
// if -p - z then the Sum is negitive // if -p - z then the Sum is negative
assign Ss = NegSum^Ps; assign Ss = NegSum^Ps;
assign Se = KillProd ? {2'b0, Ze} : Pe; assign Se = KillProd ? {2'b0, Ze} : Pe;
endmodule endmodule

2
src/fpu/fma/fmaalign.sv
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@ -45,7 +45,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// determine the shift count for alignment // determine the shift count for alignment
// - negitive means Z is larger, so shift Z left // - negative means Z is larger, so shift Z left
// - positive means the product is larger, so shift Z right // - positive means the product is larger, so shift Z right
// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze}; assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze};

4
src/fpu/postproc/divshiftcalc.sv
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@ -36,7 +36,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
); );
logic [P.LOGNORMSHIFTSZ-1:0] NormShift; // normalized result shift amount logic [P.LOGNORMSHIFTSZ-1:0] NormShift; // normalized result shift amount
logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive) logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negative)
logic [P.NE+1:0] DivSubnormShift; // subnormal result shift amount logic [P.NE+1:0] DivSubnormShift; // subnormal result shift amount
// is the result subnormal // is the result subnormal
@ -62,7 +62,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
// shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF); assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
// if the shift amount is negitive then don't shift (keep sticky bit) // if the shift amount is negative then don't shift (keep sticky bit)
// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;

8
src/fpu/postproc/flags.sv
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@ -47,7 +47,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
input logic Int64, // convert to 64 bit integer input logic Int64, // convert to 64 bit integer
input logic Signed, // convert to a signed integer input logic Signed, // convert to a signed integer
input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt
input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits
// divsqrt // divsqrt
input logic DivOp, // conversion opperation? input logic DivOp, // conversion opperation?
input logic Sqrt, // Sqrt? input logic Sqrt, // Sqrt?
@ -122,7 +122,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
// calulate overflow flag: // calulate overflow flag:
// if the result is greater than or equal to the max exponent(not taking into account sign) // if the result is greater than or equal to the max exponent(not taking into account sign)
// | and the exponent isn't negitive // | and the exponent isn't negative
// | | if the input isnt infinity or NaN // | | if the input isnt infinity or NaN
// | | | // | | |
assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero); assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero);
@ -132,7 +132,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// calculate underflow flag: detecting tininess after rounding // calculate underflow flag: detecting tininess after rounding
// the exponent is negitive // the exponent is negative
// | the result is subnormal // | the result is subnormal
// | | the result is normal and rounded from a Subnorm // | | the result is normal and rounded from a Subnorm
// | | | and if given an unbounded exponent the result does not round // | | | and if given an unbounded exponent the result does not round
@ -170,7 +170,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
// invalid flag for integer result // invalid flag for integer result
// if the input is NaN or infinity // if the input is NaN or infinity
// | if the integer res overflows (out of range) // | if the integer res overflows (out of range)
// | | if the input was negitive but ouputing to a unsigned number // | | if the input was negative but ouputing to a unsigned number
// | | | the res doesn't round to zero // | | | the res doesn't round to zero
// | | | | or the res rounds up out of bounds // | | | | or the res rounds up out of bounds
// | | | | and the res didn't underflow // | | | | and the res didn't underflow

8
src/fpu/postproc/resultsign.sv
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@ -47,7 +47,7 @@ module resultsign(
// determine the sign for a result of 0 // determine the sign for a result of 0
// The IEEE754-2019 standard specifies: // The IEEE754-2019 standard specifies:
// - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity
// - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result // - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result
// - if x = +0 or -0 then x+x=x and x-(-x)=x // - if x = +0 or -0 then x+x=x and x-(-x)=x
// - the sign of a product is the exclisive or or the opperand's signs // - the sign of a product is the exclisive or or the opperand's signs
@ -63,10 +63,10 @@ module resultsign(
assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs; assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
// determine the sign of an infinity result // determine the sign of an infinity result
// is the result negitive // is the result negative
// if p - z is the Sum negitive // if p - z is the Sum negative
// if -p + z is the Sum positive // if -p + z is the Sum positive
// if -p - z then the Sum is negitive // if -p - z then the Sum is negative
assign Infs = ZInf ? FmaAs : FmaPs; assign Infs = ZInf ? FmaAs : FmaPs;
// select the result sign // select the result sign

66
src/fpu/postproc/specialcase.sv
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@ -266,8 +266,32 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
// integer result selection // integer result selection
/////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////
// Causes undefined behavior for invalid:
// Invalid cases are different for IEEE 754 vs. RISC-V. For RISC-V, typical results are used
// unsigned: if invalid (e.g., negative fp to unsigned int, result should overflow and
// overflows to the maximum value
// signed: if invalid, result should overflow to maximum negative value
// but is undefined and used for information only
// Note: The IEEE 754 result comes from values in TestFloat for x86_64
// IEEE 754
// select the overflow integer res // select the overflow integer res
// - negitive infinity and out of range negitive input // - negative infinity and out of range negative input
// | int | long |
// signed | -2^31 | -2^63 |
// unsigned | 2^32-1 | 2^64-1 |
//
// - positive infinity and out of range positive input and NaNs
// | int | long |
// signed | -2^31 |-2^63 |
// unsigned | 2^32-1 | 2^64-1 |
//
// other: 32 bit unsigned res should be sign extended as if it were a signed number
// RISC-V
// select the overflow integer res
// - negative infinity and out of range negative input
// | int | long | // | int | long |
// signed | -2^31 | -2^63 | // signed | -2^31 | -2^63 |
// unsigned | 0 | 0 | // unsigned | 0 | 0 |
@ -278,22 +302,38 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
// unsigned | 2^32-1 | 2^64-1 | // unsigned | 2^32-1 | 2^64-1 |
// //
// other: 32 bit unsinged res should be sign extended as if it were a signed number // other: 32 bit unsinged res should be sign extended as if it were a signed number
always_comb
if(Signed) if(P.IEEE754) begin
if(Xs&~NaNIn) // signed negitive always_comb
if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; if(Signed)
else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; if(Xs&~NaNIn) // signed negative
else // signed positive if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}}; else // signed positive
else if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive else
if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negative
else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
end else begin
always_comb
if(Signed)
if(Xs&~NaNIn) // signed negative
if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
else // signed positive
if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}};
else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
else
if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negative
else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
end
// select the integer output // select the integer output
// - if the input is invalid (out of bounds NaN or Inf) then output overflow res // - if the input is invalid (out of bounds NaN or Inf) then output overflow res
// - if the input underflows // - if the input underflows
// - if rounding and signed opperation and negitive input, output -1 // - if rounding and signed opperation and negative input, output -1
// - otherwise output a rounded 0 // - otherwise output a rounded 0
// - otherwise output the normal res (trmined and sign extended if nessisary) // - otherwise output the normal res (trmined and sign extended if nessisary)
always_comb always_comb

11
src/ieu/alu.sv
View File

@ -101,11 +101,16 @@ module alu import cvw::*; #(parameter cvw_t P) (
// Zicond block // Zicond block
if (P.ZICOND_SUPPORTED) begin: zicond if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero, KillB; logic BZero;
assign BZero = (B == 0); // check if rs2 = 0 assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result // Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez // If B = 0 for czero.eqz or if B != 0 for czero.nez
assign KillB = BZero & CZero[0] | ~BZero & CZero[1]; always_comb
assign ZeroCondMaskInvB = |CZero ? {P.XLEN{~KillB}} : CondMaskInvB; // extend to full width case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
endmodule endmodule

8
src/ifu/decompress.sv
View File

@ -165,14 +165,14 @@ module decompress import cvw::*; #(parameter cvw_t P) (
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
else // if (instr16[6:5] == 2'b11) else // if (instr16[6:5] == 2'b11)
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
else if (instr16[12:10] == 3'b111) begin else begin // (instr16[12:10] == 3'b111)
if (instr16[6:5] == 2'b00 & P.XLEN > 32) if (instr16[6:5] == 2'b00 & P.XLEN > 32)
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
else if (instr16[6:5] == 2'b01 & P.XLEN > 32) else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED)
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
@ -188,9 +188,9 @@ module decompress import cvw::*; #(parameter cvw_t P) (
IllegalCompInstrD = 1; IllegalCompInstrD = 1;
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
end end
end else begin // illegal instruction /** end else begin // illegal instruction
IllegalCompInstrD = 1; IllegalCompInstrD = 1;
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
end end
5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j 5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz 5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz

4
src/privileged/csrs.sv
View File

@ -160,9 +160,9 @@ module csrs import cvw::*; #(parameter cvw_t P) (
CSRSReadValM = 0; CSRSReadValM = 0;
IllegalCSRSAccessM = 1; IllegalCSRSAccessM = 1;
end end
STIMECMPH: if (STCE) STIMECMPH: if (STCE & P.XLEN == 32) // not supported for RV64
CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]}; CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]};
else begin // not supported for RV64 else begin
CSRSReadValM = 0; CSRSReadValM = 0;
IllegalCSRSAccessM = 1; IllegalCSRSAccessM = 1;
end end

162
testbench/testbench-fp.sv
View File

@ -882,98 +882,88 @@ module testbenchfp;
// - the sign of the NaN does not matter for the opperations being tested // - the sign of the NaN does not matter for the opperations being tested
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
case (FmtVal) case (FmtVal)
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) | (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
(ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]}))); (ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | 2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) | (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
(ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]}))); (ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | 2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) | (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
(ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]}))); (ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | 2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
endcase endcase
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
case (OpCtrlVal[1:0]) case (OpCtrlVal[1:0])
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
(AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) | (AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
(YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]}))); (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})));
2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | 2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
(AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) | (AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) |
(XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
(YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]}))); (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})));
2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | 2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
(AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) | (AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) |
(XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
(YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]}))); (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})));
2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | 2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
(AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) | (AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]}))); (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
endcase endcase
else NaNGood = 1'b0; // integers can't be NaNs else NaNGood = 1'b0; // integers can't be NaNs
/////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////
// ||||||| ||| ||| ||||||| ||||||| ||| ||| // ||||||| ||| ||| ||||||| ||||||| ||| |||
// ||| ||| ||| ||| ||| ||| ||| // ||| ||| ||| ||| ||| ||| |||
// ||| |||||||||| ||||||| ||| |||||| // ||| |||||||||| ||||||| ||| ||||||
// ||| ||| ||| ||| ||| ||| ||| // ||| ||| ||| ||| ||| ||| |||
// ||||||| ||| ||| ||||||| ||||||| ||| ||| // ||||||| ||| ||| ||||||| ||||||| ||| |||
/////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////
// check if result is correct // check if result is correct
// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
assign FMAop = (OpCtrlVal == `FMAUNIT); assign FMAop = (OpCtrlVal == `FMAUNIT);
assign DivDone = OldFDivBusyE & ~FDivBusyE; assign DivDone = OldFDivBusyE & ~FDivBusyE;
// Maybe change OpCtrl but for now just look at TEST for fma test // Maybe change OpCtrl but for now just look at TEST for fma test
assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
if (~(ResMatch & FlagMatch) & CheckNow) begin if (~(ResMatch & FlagMatch) & CheckNow) begin
errors += 1; errors += 1;
$display("\nError in %s", Tests[TestNum]); $display("\nError in %s", Tests[TestNum]);
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$stop; $stop;
end end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
// TestFloat sets the result to all 1's when there is an invalid result, however in errors += 1;
// http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says $display("\nError in %s", Tests[TestNum]);
// for an unsigned integer result 0 is also okay $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
// TestFloat outputs 800... for both the largest integer values for both positive and negitive numbers but $stop;
// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... end
else if ( ((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & ~FlagMatch ) begin
// ResMatch & FlagMatch checks the result again. It is checked within the
// test again to avoid issues related when the values change tests (e.g., f16_eq_rne -> f16_eq_rz)
if (~(ResMatch & FlagMatch)) begin
errors += 1;
$display("\nError in %s", Tests[TestNum]);
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$stop;
end
end end
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof

38
tests/coverage/ifu.S
View File

@ -40,12 +40,40 @@ main:
.hword 0x2002 // c.fldsp fs0, 0 .hword 0x2002 // c.fldsp fs0, 0
.hword 0xA002 // c.fsdsp fs0, 0 .hword 0xA002 // c.fsdsp fs0, 0
.hword 0x9C41 // line 134 Illegal compressed instruction .hword 0x9C41 // line 134 Illegal compressed instruction
# could restore assembly language versions when GCC supports Zcb
# c.lbu s1, 0(s0) // exercise c.lbu
mv s0, sp
.hword 0x8004 // c.lbu s1, 0(s0)
//.hword 0x9C01 //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else # Zcb coverage tests
# could restore assembly language versions when GCC supports Zcb
mv s0, sp
#c.lbu s1, 0(s0) // exercise c.lbu
.hword 0x8004 // c.lbu s1, 0(s0)
#c.lh s1, 0(s0) // exercise c.lh
.hword 0x8444 // c.lh s1, 0(s0)
#c.lhu s1, 0(s0) // exercise c.lhu
.hword 0x8404 // c.lhu s1, 0(s0)
#c.sb s1, 0(s0) // exercise c.sb
.hword 0x8804 // c.sb s1, 0(s0)
#c.sh s1, 0(s0) // exercise c.sh
.hword 0x8C04 // c.sh s1, 0(s0)
.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
li s0, 0xFF
# c.zext.b s0 // exercise c.zext.b
.hword 0x9C61 // c.zext.b s0
# c.sext.b s0 // exercise c.sext.b
.hword 0x9C65 // c.sext.b s0
# c.zext.h s0 // exercise c.zext.h
.hword 0x9C69 // c.zext.h s0
# c.sext.h s0 // exercise c.sext.h
.hword 0x9C6D // c.sext.h s0
# c.zext.w s0 // exercise c.zext.w
.hword 0x9C71 // c.zext.w s0
# c.not s0 // exercise c.not
.hword 0x9C75 // c.not s0
.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else

4
tests/coverage/tlbmisc.S
View File

@ -40,6 +40,10 @@ main:
sw t5, 0(t0) sw t5, 0(t0)
fence.i fence.i
# Test not being able to write illegal SATP mode
li t5, 0xA000000000080010
csrw satp, t5
# Page table root address at 0x80010000; SV48 # Page table root address at 0x80010000; SV48
li t5, 0x9000000000080010 li t5, 0x9000000000080010
csrw satp, t5 csrw satp, t5

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
View File

@ -87,8 +87,8 @@ test_cases:
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
# second page table to check context switches with satp # second page table to check context switches with satp
.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage .8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) .8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
# test 11.3.1.1.2 write values to Paddrs in each page # test 11.3.1.1.2 write values to Paddrs in each page
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
@ -192,7 +192,7 @@ test_cases:
# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping
# test 11.3.1.4.2 Test Global mapping # test 11.3.1.4.2 Test Global mapping

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
View File

@ -108,8 +108,8 @@ test_cases:
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
# second page table to check context switches with satp # second page table to check context switches with satp
.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage .8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) .8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
# test 11.3.1.1.2 write values to Paddrs in each page # test 11.3.1.1.2 write values to Paddrs in each page
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
@ -249,7 +249,7 @@ test_cases:
# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping
# test 11.3.1.4.2 Test Global mapping # test 11.3.1.4.2 Test Global mapping

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
View File

@ -113,7 +113,7 @@ test_cases:
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7 .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7
# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
@ -187,7 +187,7 @@ test_cases:
# test 11.3.1.3.5 eXecute flag # test 11.3.1.3.5 eXecute flag
# executes on pages with X = 1 already tested in 11.3.1.3.1 # executes on pages with X = 1 already tested in 11.3.1.3.1
.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 .8byte 0x010087888000, 0x2, executable_test # execute fault when X=0
# In the following two tests, SVADU is not supported, so the software handles the A/D bits # In the following two tests, SVADU is not supported, so the software handles the A/D bits
# Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits # Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
View File

@ -113,7 +113,7 @@ test_cases:
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a) .8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a)
#.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4 #.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4
@ -188,7 +188,7 @@ test_cases:
# test 11.3.1.3.5 eXecute flag # test 11.3.1.3.5 eXecute flag
# executes on pages with X = 1 already tested in 11.3.1.3.1 # executes on pages with X = 1 already tested in 11.3.1.3.1
.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 .8byte 0x010087888000, 0x2, executable_test # execute fault when X=0
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits # In the following two tests, SVADU is supported, so the hardware handles the A/D bits