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91 lines
3.9 KiB
Systemverilog
91 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// fmaalign.sv
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA alginment shift
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//
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// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fmaalign import cvw::*; #(parameter cvw_t P) (
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input logic [P.NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [P.NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*P.NF+3:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ASticky, // Sticky bit calculated from the aliged addend
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output logic KillProd // should the product be set to zero
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);
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logic [P.NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
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logic [4*P.NF+3:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*P.NF+3:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic KillZ; // should the addend be killed
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///////////////////////////////////////////////////////////////////////////////
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// Alignment shifter
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///////////////////////////////////////////////////////////////////////////////
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// determine the shift count for alignment
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// - negative means Z is larger, so shift Z left
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// - positive means the product is larger, so shift Z right
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// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze};
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// Default Addition with only inital left shift
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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assign ZmPreshifted = {Zm,(3*P.NF+3)'(0)};
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assign KillProd = (ACnt[P.NE+1]&~ZZero)|XZero|YZero;
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assign KillZ = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(3));
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always_comb begin
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// If the product is too small to effect the sum, kill the product
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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if (KillProd) begin
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ZmShifted = {(P.NF+2)'(0), Zm, (2*P.NF+1)'(0)};
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ASticky = ~(XZero|YZero);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the product to be considered too small
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// - The 2 extra bits are needed for rounding
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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end else if (KillZ) begin
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ZmShifted = 0;
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ASticky = ~ZZero;
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// If the Addend is shifted right
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// | 53'b0 | 106'b(product) | 1'b0 |
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// | addnend |
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end else begin
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ZmShifted = ZmPreshifted >> ACnt;
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ASticky = |(ZmShifted[P.NF-1:0]);
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end
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end
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assign Am = ZmShifted[4*P.NF+3:P.NF];
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endmodule
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