Merge branch 'main' of https://github.com/openhwgroup/cvw

Plus major cleanup of wally-batch.do

sim/wally-batch.do

@@ -28,14 +28,14 @@ vlib wkdir/work_${1}_${2}
 # Create directory for coverage data
 mkdir -p cov
 
-# Need to be able to pass arguments to vopt.  Unforunately argv does not work because
-# it takes on different values if vsim and the do file are called from the command line or
-# if the do file isd called from questa sim directly.  This chunk of code uses the $4 through $n
-# variables and compacts into a single list for passing to vopt.
 set coverage 0
 set CoverageVoptArg ""
 set CoverageVsimArg ""
 
+# Need to be able to pass arguments to vopt.  Unforunately argv does not work because
+# it takes on different values if vsim and the do file are called from the command line or
+# if the do file isd called from questa sim directly.  This chunk of code uses the $4 through $n
+# variables and compacts into a single list for passing to vopt.
 set configOptions ""
 set from 4
 set step 1
@@ -67,17 +67,12 @@ if {$argc >= 3} {
 # do wally-pipelined-batch.do ../config/rv32imc rv32imc
 
 vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
+
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-if {$coverage} {
+vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
-    #        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
+vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829 ${CoverageVsimArg}
-    puts "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
+
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt ${CoverageVoptArg}
-    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829 ${CoverageVsimArg}
-} else {
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt
-    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
-}
 #    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
 # power add generates the logging necessary for said generation.
 # power add -r /dut/core/*
@@ -86,7 +81,6 @@ run -all
 
 
 if {$coverage} {
-    puts "???????????????????????????"
     echo "Saving coverage to ${1}_${2}.ucdb"
     do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
     coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb

src/fpu/fctrl.sv

@@ -237,11 +237,10 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
                                     5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q   q->l
                                     5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q  q->lu
                                   endcase
-                      // coverage on
+                      // coverage off
+                      // Not covered in testing because rv64gc is not RV64Q or RV32D
                       7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) 
                                                   ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x  (Zfa) *** untested, controls could be wrong
-                      // Not covered in testing because rv64gc does not support quad precision
-                      // coverage off
                       7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) 
                                                   ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x  (Zfa)
                       // coverage on

testbench/testbench.sv

@@ -320,7 +320,7 @@ module testbench;
     if (TEST == "coremark")
       if (dut.core.priv.priv.EcallFaultM) begin
         $display("Benchmark: coremark is done.");
-        $finish;
+        $stop;
       end
     if(Validate) begin
       if (TEST == "embench") begin
@@ -357,7 +357,7 @@ module testbench;
       if (test == tests.size()) begin
         if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
         else $display("FAIL: %d test programs had errors", totalerrors);
-        $finish;
+        $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
       end
     end
   end
@@ -798,7 +798,7 @@ end
         errors = errors+1;
         $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
 			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
-        $finish;
+        $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
       end
     end
     if (errors) $display("%s failed with %d errors. :(", TestName, errors);

testbench/tests.vh

@@ -1134,10 +1134,10 @@ string imperas32f[] = '{
 
     string arch64zfh_fma[] = '{
     `RISCVARCHTEST,
-    //"rv64i_m/F/src/fmadd_b15-01.S",
+    "rv64i_m/Zfh/src/fmadd_b15-01.S",
-    "rv64i_m/Zfh/src/fmsub_b15-01.S"
+    "rv64i_m/Zfh/src/fmsub_b15-01.S",
-    // "rv64i_m/F/src/fnmadd_b15-01.S",
+    "rv64i_m/Zfh/src/fnmadd_b15-01.S",
-    // "rv64i_m/F/src/fnmsub_b15-01.S"
+    "rv64i_m/Zfh/src/fnmsub_b15-01.S"
   };
 
   string arch64f_divsqrt[] = '{
@@ -2178,10 +2178,10 @@ string arch64zbs[] = '{
 
 string arch32zfh_fma[] = '{
     `RISCVARCHTEST,
-    //"rv32i_m/D/src/fmadd.d_b15-01.S",
+    "rv32i_m/Zfh/src/fmadd_b15-01.S",
-    //"rv32i_m/D/src/fmsub.d_b15-01.S",
+    "rv32i_m/Zfh/src/fmsub_b15-01.S",
-    // "rv32i_m/D/src/fnmadd.d_b15-01.S",
+    "rv32i_m/Zfh/src/fnmadd_b15-01.S",
-    "rv32i_m/Zfh/src/fnmsub.d_b15-01.S"
+    "rv32i_m/Zfh/src/fnmsub_b15-01.S"
   };
 
   string arch32d_divsqrt[] = '{

tests/coverage/fpu.S

@@ -40,12 +40,24 @@ main:
     # zfa instructions (because Zfa tests aren't running yet)
     fli.d fs0, 16
     fcvtmod.w.d t0, fs0, rtz
-    fminm.d fs1, fs0, fs0
+#    fminm.d fs1, fs0, fs0
-    fmaxm.d fs1, fs0, fs0
+#    fmaxm.d fs1, fs0, fs0
+#    fltq.d t0, fs1, ft0
+#    fleq.d t0, fs1, ft0
+    fcvt.d.q fs1, fs0
+    fcvt.h.q fs1, fs0
+    fcvt.s.q fs1, fs0
+    # round for now because these tests are excluded from Zfa until rounding is implemented
+    fround.s fs1, fs0       
+    froundnx.s fs1, fs0
     fround.d fs1, fs0       
     froundnx.d fs1, fs0
-    fltq.d t0, fs1, ft0
+    fround.h fs1, fs0
-    fleq.d t0, fs1, ft0
+    froundnx.h fs1, fs0
+    fround.s fs1, fs0
+    froundnx.s fs1, fs0
+    fmvp.d.x
+
 
     #Result Sign Test Coverage
     la t0, TestData2