From 0bc01fffbb60696209b1cdaa6539ed53bd7513cb Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 6 Feb 2024 16:33:38 -0800 Subject: [PATCH 1/3] fixed two-bit bpred configurations in derivlist.txt --- config/derivlist.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index fdb17dfd3..32768a3af 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -328,22 +328,22 @@ deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc -INSTR_CLASS_PRED 0 +BPRED_TYPE `BP_TWOBIT deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc INSTR_CLASS_PRED 0 From 5bde0db64b1255570d22a6be9eb8b4e8c6232c03 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 7 Feb 2024 04:55:29 -0800 Subject: [PATCH 2/3] Added ZFH FMA tests from https://github.com/riscv-non-isa/riscv-arch-test/pull/367 --- testbench/tests.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 1fe1e6faa..11afd2224 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1134,10 +1134,10 @@ string imperas32f[] = '{ string arch64zfh_fma[] = '{ `RISCVARCHTEST, - //"rv64i_m/F/src/fmadd_b15-01.S", - "rv64i_m/Zfh/src/fmsub_b15-01.S" - // "rv64i_m/F/src/fnmadd_b15-01.S", - // "rv64i_m/F/src/fnmsub_b15-01.S" + "rv64i_m/Zfh/src/fmadd_b15-01.S", + "rv64i_m/Zfh/src/fmsub_b15-01.S", + "rv64i_m/Zfh/src/fnmadd_b15-01.S", + "rv64i_m/Zfh/src/fnmsub_b15-01.S" }; string arch64f_divsqrt[] = '{ @@ -2178,10 +2178,10 @@ string arch64zbs[] = '{ string arch32zfh_fma[] = '{ `RISCVARCHTEST, - //"rv32i_m/D/src/fmadd.d_b15-01.S", - //"rv32i_m/D/src/fmsub.d_b15-01.S", - // "rv32i_m/D/src/fnmadd.d_b15-01.S", - "rv32i_m/Zfh/src/fnmsub.d_b15-01.S" + "rv32i_m/Zfh/src/fmadd_b15-01.S", + "rv32i_m/Zfh/src/fmsub_b15-01.S", + "rv32i_m/Zfh/src/fnmadd_b15-01.S", + "rv32i_m/Zfh/src/fnmsub_b15-01.S" }; string arch32d_divsqrt[] = '{ From e7364290e3f4214fdba119a5f0134f65708c86a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 7 Feb 2024 06:27:53 -0800 Subject: [PATCH 3/3] Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage --- src/fpu/fctrl.sv | 5 ++--- testbench/testbench.sv | 6 +++--- tests/coverage/fpu.S | 22 +++++++++++++++++----- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 60edbfd8a..788ac2e27 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -237,11 +237,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu endcase - // coverage on + // coverage off + // Not covered in testing because rv64gc is not RV64Q or RV32D 7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong - // Not covered in testing because rv64gc does not support quad precision - // coverage off 7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa) // coverage on diff --git a/testbench/testbench.sv b/testbench/testbench.sv index debe7b827..1bd841074 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -310,7 +310,7 @@ module testbench; if (TEST == "coremark") if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); - $finish; + $stop; end if(Validate) begin if (TEST == "embench") begin @@ -347,7 +347,7 @@ module testbench; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); - $finish; + $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage end end end @@ -631,7 +631,7 @@ module testbench; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - $finish; + $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage end end if (errors) $display("%s failed with %d errors. :(", TestName, errors); diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index f4777392e..fbdaa20ac 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -40,12 +40,24 @@ main: # zfa instructions (because Zfa tests aren't running yet) fli.d fs0, 16 fcvtmod.w.d t0, fs0, rtz - fminm.d fs1, fs0, fs0 - fmaxm.d fs1, fs0, fs0 - fround.d fs1, fs0 +# fminm.d fs1, fs0, fs0 +# fmaxm.d fs1, fs0, fs0 +# fltq.d t0, fs1, ft0 +# fleq.d t0, fs1, ft0 + fcvt.d.q fs1, fs0 + fcvt.h.q fs1, fs0 + fcvt.s.q fs1, fs0 + # round for now because these tests are excluded from Zfa until rounding is implemented + fround.s fs1, fs0 + froundnx.s fs1, fs0 + fround.d fs1, fs0 froundnx.d fs1, fs0 - fltq.d t0, fs1, ft0 - fleq.d t0, fs1, ft0 + fround.h fs1, fs0 + froundnx.h fs1, fs0 + fround.s fs1, fs0 + froundnx.s fs1, fs0 + fmvp.d.x + #Result Sign Test Coverage la t0, TestData2