diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 865ebc74d..0af178c94 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -149,8 +149,8 @@ module cacheLRU
       for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
     else if(CacheEn) begin
       // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
-      if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU;
-      else                                   CurrLRU = #1 LRUMemory[CacheSetTag];
+      if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;
+      else                                   CurrLRU = LRUMemory[CacheSetTag];
       if(LRUWriteEn)                         LRUMemory[PAdr] = NextLRU;
     end
   end
diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv
index 2e7db3d6e..0a69feebb 100644
--- a/testbench/testbench-xcelium.sv
+++ b/testbench/testbench-xcelium.sv
@@ -216,8 +216,8 @@ module testbench;
   end
 
   always_ff @(posedge clk)
-    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
-    else CurrState <= #1 NextState;  
+    if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
+    else CurrState <= NextState;  
 
   // fsm next state logic
   always_comb begin
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index fb12eb082..ee725c245 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -248,8 +248,8 @@ module testbench;
   end
 
   always_ff @(posedge clk)
-    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
-    else CurrState <= #1 NextState;  
+    if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
+    else CurrState <= NextState;  
 
   // fsm next state logic
   always_comb begin