mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed some lint errors in derived configs
This commit is contained in:
David Harris
parent
d9003da8e0
commit
0abfe5cb55
@ -59,10 +59,10 @@ BPRED_SIZE 32'd12
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# The syn configurations are trimmed down for faster synthesis.
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deriv syn_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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UNCORE_RAM_RANGE 32'h1FF
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DTIM_RANGE 64'h1FF
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IROM_RANGE 64'h1FF
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BOOTROM_RANGE 64'h1FF
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UNCORE_RAM_RANGE 64'h1FF
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WAYSIZEINBYTES 32'd512
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NUMWAYS 32'd1
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BPRED_SIZE 32'd5
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@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e
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# The syn_sram configurations use SRAM macros
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deriv syn_sram_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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DTIM_RANGE 64'h1FF
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IROM_RANGE 64'h1FF
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USE_SRAM 1
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# The other syn configurations have the same trimming
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@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
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# The following syn configurations gradually turn off features
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deriv syn_pmp0_rv64gc rv64gc syn_rv64gc
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PMP_ENTRIES 0
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PMP_ENTRIES 32'd0
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deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc
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PMP_ENTRIES 0
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PMP_ENTRIES 32'd0
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deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc
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ZICSR_SUPPORTED 0
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@ -203,95 +203,95 @@ IDIV_ON_FPU 1
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# RAM latency and Burst mode for bus stress testing
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deriv ram_0_0_rv64gc rv64gc
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RAM_LATENCY 0
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RAM_LATENCY 32'd0
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BURST_EN 0
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deriv ram_1_0_rv64gc rv64gc
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RAM_LATENCY 1
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RAM_LATENCY 32'd1
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BURST_EN 0
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deriv ram_2_0_rv64gc rv64gc
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RAM_LATENCY 2
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RAM_LATENCY 32'd2
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BURST_EN 0
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deriv ram_1_1_rv64gc rv64gc
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RAM_LATENCY 1
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RAM_LATENCY 32'd1
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BURST_EN 1
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deriv ram_2_1_rv64gc rv64gc
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RAM_LATENCY 2
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RAM_LATENCY 32'd2
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BURST_EN 1
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# Branch predictor simulations
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deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc
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BPRED_SIZE 6
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BPRED_SIZE 32'd6
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deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
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BPRED_SIZE 8
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BPRED_SIZE 32'd8
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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BPRED_SIZE 10
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BPRED_SIZE 32'd10
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deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
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BPRED_SIZE 12
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BPRED_SIZE 32'd12
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deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
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BPRED_SIZE 14
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BPRED_SIZE 32'd14
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deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
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BPRED_SIZE 16
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BPRED_SIZE 32'd16
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deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc
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BPRED_TYPE BP_TWOBIT
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BPRED_TYPE `BP_TWOBIT
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 2
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RAS_SIZE 32'd2
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deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
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RAS_SIZE 3
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RAS_SIZE 32'd3
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deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
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RAS_SIZE 4
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RAS_SIZE 32'd4
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deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
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RAS_SIZE 6
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RAS_SIZE 32'd6
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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RAS_SIZE 10
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RAS_SIZE 32'd10
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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RAS_SIZE 16
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RAS_SIZE 32'd16
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deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
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BTB_SIZE 6
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BTB_SIZE 32'd6
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deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
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BTB_SIZE 8
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BTB_SIZE 32'd8
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deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
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BTB_SIZE 12
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BTB_SIZE 32'd12
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deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
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BTB_SIZE 14
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BTB_SIZE 32'd14
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deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
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BTB_SIZE 16
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BTB_SIZE 32'd16
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deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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INSTR_CLASS_PRED 0
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@ -375,36 +375,36 @@ ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv32gc rv32gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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DCACHE_LINELENINBITS 32'd512
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ICACHE_NUMWAYS 32'd1
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ICACHE_WAYSIZEINBYTES 32'd4096
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ICACHE_LINELENINBITS 32'd512
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deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 1
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ICACHE_NUMWAYS 1
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DCACHE_NUMWAYS 32'd1
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ICACHE_NUMWAYS 32'd1
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deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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DCACHE_NUMWAYS 32'd4
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ICACHE_NUMWAYS 32'd4
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deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc
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DCACHE_NUMWAYS 8
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ICACHE_NUMWAYS 8
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DCACHE_NUMWAYS 32'd8
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ICACHE_NUMWAYS 32'd8
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deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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DCACHE_WAYSIZEINBYTES 32'd2048
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ICACHE_WAYSIZEINBYTES 32'd2048
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deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 256
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ICACHE_LINELENINBITS 256
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DCACHE_LINELENINBITS 32'd256
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ICACHE_LINELENINBITS 32'd256
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deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc
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DCACHE_LINELENINBITS 1024
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ICACHE_LINELENINBITS 1024
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DCACHE_LINELENINBITS 32'd1024
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ICACHE_LINELENINBITS 32'd1024
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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@ -417,50 +417,50 @@ ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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deriv way_1_4096_512_rv64gc rv64gc
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DCACHE_NUMWAYS 1
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DCACHE_WAYSIZEINBYTES 4096
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DCACHE_LINELENINBITS 512
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ICACHE_NUMWAYS 1
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ICACHE_WAYSIZEINBYTES 4096
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ICACHE_LINELENINBITS 512
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DCACHE_NUMWAYS 32'd1
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DCACHE_WAYSIZEINBYTES 32'd4096
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DCACHE_LINELENINBITS 32'd512
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ICACHE_NUMWAYS 32'd1
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ICACHE_WAYSIZEINBYTES 32'd4096
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ICACHE_LINELENINBITS 32'd512
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deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
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DCACHE_NUMWAYS 1
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ICACHE_NUMWAYS 1
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DCACHE_NUMWAYS 32'd1
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ICACHE_NUMWAYS 32'd1
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deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc
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DCACHE_NUMWAYS 4
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ICACHE_NUMWAYS 4
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DCACHE_NUMWAYS 32'd4
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ICACHE_NUMWAYS 32'd4
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deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_WAYSIZEINBYTES 2048
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ICACHE_WAYSIZEINBYTES 2048
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DCACHE_WAYSIZEINBYTES 32'd2048
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ICACHE_WAYSIZEINBYTES 32'd2048
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deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_LINELENINBITS 256
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ICACHE_LINELENINBITS 256
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DCACHE_LINELENINBITS 32'd256
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ICACHE_LINELENINBITS 32'd256
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deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc
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DCACHE_LINELENINBITS 1024
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ICACHE_LINELENINBITS 1024
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DCACHE_LINELENINBITS 32'd1024
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ICACHE_LINELENINBITS 32'd1024
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# TLB Size variants
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deriv tlb2_rv32gc rv32gc
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ITLB_ENTRIES 2
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DTLB_ENTRIES 2
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ITLB_ENTRIES 32'd2
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DTLB_ENTRIES 32'd2
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deriv tlb16_rv32gc rv32gc
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ITLB_ENTRIES 16
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DTLB_ENTRIES 16
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ITLB_ENTRIES 32'd16
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DTLB_ENTRIES 32'd16
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deriv tlb2_rv64gc rv64gc
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ITLB_ENTRIES 2
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DTLB_ENTRIES 2
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ITLB_ENTRIES 32'd2
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DTLB_ENTRIES 32'd2
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deriv tlb16_rv64gc rv64gc
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ITLB_ENTRIES 16
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DTLB_ENTRIES 16
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ITLB_ENTRIES 32'd16
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DTLB_ENTRIES 32'd16
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# Feature variants
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@ -102,6 +102,7 @@ localparam cvw_t P = '{
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BPRED_NUM_LHR : BPRED_NUM_LHR,
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BTB_SIZE : BTB_SIZE,
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RAS_SIZE : RAS_SIZE,
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INSTR_CLASS_PRED : INSTR_CLASS_PRED,
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RADIX : RADIX,
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DIVCOPIES : DIVCOPIES,
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ZBA_SUPPORTED : ZBA_SUPPORTED,
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@ -1,14 +1,26 @@
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#!/bin/bash
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# check for warnings in Verilog code
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# The verilator lint tool is faster and better than Questa so it is best to run this first.
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export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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basepath=$(dirname $0)/..
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for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do
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#for config in rv64gc; do
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if [ "$1" == "-nightly" ]; then
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
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derivconfigs=`ls $WALLY/config/deriv`
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for entry in $derivconfigs
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do
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configs[${#configs[@]}]=$entry
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done
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else
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
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fi
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for config in ${configs[@]}; do
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echo "$config linting..."
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if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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echo "Exiting after $config lint due to errors or warnings"
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exit 1
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fi
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2
src/cache/cacheLRU.sv
vendored
2
src/cache/cacheLRU.sv
vendored
@ -143,7 +143,7 @@ module cacheLRU
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// This is a two port memory.
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// Every cycle must read from CacheSetData and each load/store must write the new LRU.
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always_ff @(posedge clk) begin
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if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
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if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0;
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if(CacheEn) begin
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if(ClearValid & ~FlushStage)
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LRUMemory[PAdr] <= '0;
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@ -162,6 +162,7 @@ typedef struct packed {
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int BPRED_SIZE;
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int BTB_SIZE;
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int RAS_SIZE;
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logic INSTR_CLASS_PRED; // is class predictor enabled
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// FPU division architecture
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int RADIX;
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@ -270,9 +270,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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// floating-point load immediate: fli
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if (P.ZFA_SUPPORTED) begin
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logic [4:0] Rs1E;
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logic [1:0] Fmt2E; // Two-bit format field from instruction
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flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
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fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE));
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flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
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fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE));
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end else assign FliResE = '0;
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// fmv.*.x: NaN Box SrcA to extend integer to requested FP size
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@ -287,7 +289,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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FmtE, PreIntSrcE); // NaN boxing zeroes
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end
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// fmvp.*.x: Select pair of registers
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if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED))
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if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN))
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assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x
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else assign IntSrcE = PreIntSrcE;
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@ -311,11 +313,11 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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end
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// sign extend to XLEN if necessary
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if (P.FLEN>P.XLEN)
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if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
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else assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
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if (P.FLEN >= 2*P.XLEN)
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if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
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else assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
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else
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assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
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assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE};
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mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
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// E/M pipe registers
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@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
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endcase
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end
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assign CycleFlag = Cycle == P.RAM_LATENCY;
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assign CycleFlag = Cycle == P.RAM_LATENCY[7:0];
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assign CntEn = NextState == DELAY;
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assign DelayReady = NextState == DELAY;
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assign CntRst = NextState == READY;
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