From 0abfe5cb5544f542531bbf15ed22d07a292655a9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 11:39:59 -0800 Subject: [PATCH] Fixed some lint errors in derived configs --- config/derivlist.txt | 156 ++++++++++++++++---------------- config/shared/parameter-defs.vh | 1 + sim/lint-wally | 18 +++- src/cache/cacheLRU.sv | 2 +- src/cvw.sv | 1 + src/fpu/fpu.sv | 14 +-- src/uncore/ram_ahb.sv | 2 +- 7 files changed, 105 insertions(+), 89 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index bcffb1ec5..53cb3b8f1 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -59,10 +59,10 @@ BPRED_SIZE 32'd12 # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF -BOOTROM_RANGE 32'h1FF -UNCORE_RAM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +BOOTROM_RANGE 64'h1FF +UNCORE_RAM_RANGE 64'h1FF WAYSIZEINBYTES 32'd512 NUMWAYS 32'd1 BPRED_SIZE 32'd5 @@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e # The syn_sram configurations use SRAM macros deriv syn_sram_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF USE_SRAM 1 # The other syn configurations have the same trimming @@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e # The following syn configurations gradually turn off features deriv syn_pmp0_rv64gc rv64gc syn_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc ZICSR_SUPPORTED 0 @@ -203,95 +203,95 @@ IDIV_ON_FPU 1 # RAM latency and Burst mode for bus stress testing deriv ram_0_0_rv64gc rv64gc -RAM_LATENCY 0 +RAM_LATENCY 32'd0 BURST_EN 0 deriv ram_1_0_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 0 deriv ram_2_0_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 0 deriv ram_1_1_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 1 deriv ram_2_1_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 1 # Branch predictor simulations deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc -BPRED_SIZE 6 +BPRED_SIZE 32'd6 deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc -BPRED_SIZE 8 +BPRED_SIZE 32'd8 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -BPRED_SIZE 10 +BPRED_SIZE 32'd10 deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc -BPRED_SIZE 12 +BPRED_SIZE 32'd12 deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc -BPRED_SIZE 14 +BPRED_SIZE 32'd14 deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc -BPRED_SIZE 16 +BPRED_SIZE 32'd16 deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 2 +RAS_SIZE 32'd2 deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc -RAS_SIZE 3 +RAS_SIZE 32'd3 deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc -RAS_SIZE 4 +RAS_SIZE 32'd4 deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc -RAS_SIZE 6 +RAS_SIZE 32'd6 deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 10 +RAS_SIZE 32'd10 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -RAS_SIZE 16 +RAS_SIZE 32'd16 deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc -BTB_SIZE 6 +BTB_SIZE 32'd6 deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc -BTB_SIZE 8 +BTB_SIZE 32'd8 deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc -BTB_SIZE 12 +BTB_SIZE 32'd12 deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc -BTB_SIZE 14 +BTB_SIZE 32'd14 deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc -BTB_SIZE 16 +BTB_SIZE 32'd16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc INSTR_CLASS_PRED 0 @@ -375,36 +375,36 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv32gc rv32gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 8 -ICACHE_NUMWAYS 8 +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 deriv noicache_rv64gc rv64gc ICACHE_SUPPORTED 0 @@ -417,50 +417,50 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv64gc rv64gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 # TLB Size variants deriv tlb2_rv32gc rv32gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv32gc rv32gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 deriv tlb2_rv64gc rv64gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv64gc rv64gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 # Feature variants diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index bf4c11198..464e3c0f9 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -102,6 +102,7 @@ localparam cvw_t P = '{ BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, RAS_SIZE : RAS_SIZE, + INSTR_CLASS_PRED : INSTR_CLASS_PRED, RADIX : RADIX, DIVCOPIES : DIVCOPIES, ZBA_SUPPORTED : ZBA_SUPPORTED, diff --git a/sim/lint-wally b/sim/lint-wally index 3125e79ea..3d28a62ec 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,14 +1,26 @@ #!/bin/bash # check for warnings in Verilog code # The verilator lint tool is faster and better than Questa so it is best to run this first. + export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do -#for config in rv64gc; do + +if [ "$1" == "-nightly" ]; then + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc + derivconfigs=`ls $WALLY/config/deriv` + for entry in $derivconfigs + do + configs[${#configs[@]}]=$entry + done +else + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc) +fi + +for config in ${configs[@]}; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 70f129d4b..870633405 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -143,7 +143,7 @@ module cacheLRU // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. always_ff @(posedge clk) begin - if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; + if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; if(CacheEn) begin if(ClearValid & ~FlushStage) LRUMemory[PAdr] <= '0; diff --git a/src/cvw.sv b/src/cvw.sv index c9d737d8f..75f83f68b 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -162,6 +162,7 @@ typedef struct packed { int BPRED_SIZE; int BTB_SIZE; int RAS_SIZE; + logic INSTR_CLASS_PRED; // is class predictor enabled // FPU division architecture int RADIX; diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 90ec10dee..85021d269 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -270,9 +270,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // floating-point load immediate: fli if (P.ZFA_SUPPORTED) begin logic [4:0] Rs1E; + logic [1:0] Fmt2E; // Two-bit format field from instruction flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); - fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); + flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E); + fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); end else assign FliResE = '0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size @@ -287,7 +289,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( FmtE, PreIntSrcE); // NaN boxing zeroes end // fmvp.*.x: Select pair of registers - if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED)) + if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN)) assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x else assign IntSrcE = PreIntSrcE; @@ -311,11 +313,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( end // sign extend to XLEN if necessary - if (P.FLEN>P.XLEN) - if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* - else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; + if (P.FLEN >= 2*P.XLEN) + if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* + else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index e14728513..98bdfcb09 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == P.RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY[7:0]; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY;