2021-11-30 00:32:51 +00:00
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dst := IP
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2022-10-24 20:38:39 +00:00
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|
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# vcu118
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|
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|
#export XILINX_PART := xcvu9p-flga2104-2L-e
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#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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2022-11-07 15:20:05 +00:00
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#export board := vcu118
|
2022-10-24 20:38:39 +00:00
|
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|
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# vcu108
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|
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|
export XILINX_PART := xcvu095-ffva2104-2-e
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|
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
|
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|
|
|
export board := vcu108
|
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|
|
|
|
2021-11-30 00:32:51 +00:00
|
|
|
|
2021-12-03 16:05:13 +00:00
|
|
|
all: FPGA
|
2021-11-30 00:32:51 +00:00
|
|
|
|
2021-12-03 16:05:13 +00:00
|
|
|
FPGA: IP
|
2022-11-07 15:20:05 +00:00
|
|
|
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
2021-12-03 16:05:13 +00:00
|
|
|
|
|
|
|
|
IP: $(dst)/xlnx_proc_sys_reset.log \
|
2022-10-24 20:38:39 +00:00
|
|
|
$(dst)/xlnx_ddr4-$(board).log \
|
2021-11-30 00:32:51 +00:00
|
|
|
$(dst)/xlnx_axi_clock_converter.log \
|
|
|
|
|
$(dst)/xlnx_ahblite_axi_bridge.log
|
|
|
|
|
|
|
|
|
|
$(dst)/%.log: %.tcl
|
|
|
|
|
mkdir -p IP
|
|
|
|
|
cd IP;\
|
|
|
|
|
vivado -mode batch -source ../$*.tcl | tee $*.log
|
2021-11-30 00:42:28 +00:00
|
|
|
|
2021-12-03 16:05:13 +00:00
|
|
|
cleanIP:
|
|
|
|
|
rm -rf IP
|
|
|
|
|
|
|
|
|
|
cleanLogs:
|
|
|
|
|
rm -rf *.jou *.log
|
|
|
|
|
|
|
|
|
|
cleanFPGA:
|
|
|
|
|
rm -rf WallyFPGA.* reports sim .Xil
|
|
|
|
|
|
|
|
|
|
cleanAll: cleanIP cleanLogs cleanFPGA
|
