60 lines
2.6 KiB
Markdown
60 lines
2.6 KiB
Markdown
## Required Pkgs
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1. iverilog
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2. make
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3. gtkwave
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4. yosys
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4. nextpnr
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5. icestrom
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## Installation
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Script assumes Makefile template, and GoBoard constraints file are in the same directory. If this is not wanted
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`cat "$DIR"/goboard_Makefile_template >> "$project_name"/Makefile`
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and
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`cat "$DIR"/Go_Board_Constraints.pcf >> "$project_name"/"$project_name"_constraints_top.pcf`
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can be changed to the location of the Makefile template and constraints file
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## Usage
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Once the script is called, there will be a prompt for the project name - which is the only required field, your name, and sid.
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After this the directory structure will be created with source, results, submodules, testbench, and turnin.
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## Directories
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#### testbench
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The testbench directory is where the Makefile will look for the top module which must end in `_tb.v.`
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Multiple files may be in this directory, however the desired testbench must be the only file ending with `_tb.v`
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#### source
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The source directory is for all modules not including the testbench.
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#### results
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The results directory will contain the output file that can be run with `vvp` as well as the `.vcd` file that can be viewed with `gtkwave`
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#### submodules
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Other verilog projects which were created using the script can be placed in this directory. `make` will compile `.v` files within the `source` directories of each of the submodules.
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#### turnin
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All files added to the turnin directory will be compressed when `make tin` is run,
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## make commands
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#### make
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Running `make` while in the project directory will compile the source files and place the output file the `results` directory. Additionaly, this will set the dumpfile to `simx.vcd` in the `results` directory which can be viewed with `gtkwave`.
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#### make sim
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Running `make sim` while in the project directory will use `vvp` to run the compiled output file.
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#### make view
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Running `make view` while in the project directory will open the dump file with `gtkwave`.
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#### make test
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Running `make view` while in the project directory is similar to `make`, however the dumpfile will be set to `/dev/null` to avoid creating a `.vcd` file.
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#### make synth
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Running `make synth` while in the project directory will use yosys to attempt to synthesize the Verilog for the ice40 FPGA on the GoBoard
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#### make par
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Running `make par` while in the project directory will use nextpnr-ice40 to place and route on the ice40 FPGA
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#### make pack
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Running `make par` while in the project directory will use icepack to create a bin file
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#### make prog
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Running `make par` while in the project directory will program the Goboard with the bin file
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