forked from Github_Repos/cvw
35 lines
821 B
Systemverilog
35 lines
821 B
Systemverilog
module sd_crc_7(BITVAL, Enable, CLK, RST, CRC);
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input BITVAL;// Next input bit
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input Enable;
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input CLK; // Current bit valid (Clock)
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input RST; // Init CRC value
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output [6:0] CRC; // Current output CRC value
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reg [6:0] CRC;
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// We need output registers
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wire inv;
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assign inv = BITVAL ^ CRC[6]; // XOR required?
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always @(posedge CLK or posedge RST) begin
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if (RST) begin
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CRC = 0;
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end
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else begin
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if (Enable==1) begin
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CRC[6] = CRC[5];
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CRC[5] = CRC[4];
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CRC[4] = CRC[3];
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CRC[3] = CRC[2] ^ inv;
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CRC[2] = CRC[1];
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CRC[1] = CRC[0];
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CRC[0] = inv;
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end
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end
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end
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endmodule
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