forked from Github_Repos/cvw
133 lines
3.3 KiB
Systemverilog
133 lines
3.3 KiB
Systemverilog
///////////////////////////////////////////
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// sd_top_tb.sv
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//
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// Written: Ross Thompson September 20, 2021
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// Modified:
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module sd_top_tb();
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localparam g_COUNT_WIDTH = 8;
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logic a_RST;
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logic i_SD_CMD;
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logic o_SD_CMD;
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logic o_SD_CMD_OE;
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wire [3:0] i_SD_DAT;
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logic o_SD_CLK;
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logic [32:9] i_BLOCK_ADDR;
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logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
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logic o_READY_FOR_READ;
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logic i_READ_REQUEST;
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logic [3:0] o_DATA_TO_CORE;
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logic o_DATA_VALID;
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logic o_LAST_NIBBLE;
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logic [4095:0] ReadData;
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logic o_SD_RESTARTING;
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logic [2:0] o_ERROR_CODE_Q;
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logic o_FATAL_ERROR;
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// Driver
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wire PAD;
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logic r_CLK;
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// clock
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sd_top #(g_COUNT_WIDTH) DUT
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(.CLK(r_CLK),
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.a_RST(a_RST),
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.i_SD_CMD(i_SD_CMD),
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.o_SD_CMD(o_SD_CMD),
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.o_SD_CMD_OE(o_SD_CMD_OE),
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.i_SD_DAT(i_SD_DAT),
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.o_SD_CLK(o_SD_CLK),
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.i_BLOCK_ADDR(i_BLOCK_ADDR),
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.o_READY_FOR_READ(o_READY_FOR_READ),
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.o_SD_RESTARTING(o_SD_RESTARTING),
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.o_ERROR_CODE_Q(o_ERROR_CODE_Q),
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.o_FATAL_ERROR(o_FATAL_ERROR),
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.i_READ_REQUEST(i_READ_REQUEST),
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.o_DATA_TO_CORE(o_DATA_TO_CORE),
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.ReadData(ReadData),
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.o_DATA_VALID(o_DATA_VALID),
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.o_LAST_NIBBLE(o_LAST_NIBBLE),
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.i_COUNT_IN_MAX(i_COUNT_IN_MAX),
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.LIMIT_SD_TIMERS(1'b1));
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sdModel sdcard
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(.sdClk(o_SD_CLK),
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.cmd(PAD),
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.dat(i_SD_DAT));
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// tri state pad
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// replace with I/O standard cell or FPGA gate.
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assign PAD = o_SD_CMD_OE ? o_SD_CMD : 1'bz;
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assign i_SD_CMD = PAD;
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always
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begin
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r_CLK = 1; # 5; r_CLK = 0; # 5;
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end
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initial $readmemh("ramdisk2.hex", sdcard.FLASHmem);
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initial begin
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a_RST = 1'b0;
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i_BLOCK_ADDR = 24'h100000;
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i_COUNT_IN_MAX = '0;
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i_READ_REQUEST = 1'b0;
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# 5;
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i_COUNT_IN_MAX = -62;
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# 10;
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a_RST = 1'b1;
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# 4800;
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a_RST = 1'b0;
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# 2000000;
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i_READ_REQUEST = 1'b0;
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# 10000;
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i_READ_REQUEST = 1'b1;
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# 10000;
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i_READ_REQUEST = 1'b0;
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end
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endmodule
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