forked from Github_Repos/cvw
18 lines
650 B
Systemverilog
18 lines
650 B
Systemverilog
module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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input logic [31:0] InstrW,
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// output logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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