forked from Github_Repos/cvw
172 lines
7.7 KiB
Systemverilog
172 lines
7.7 KiB
Systemverilog
///////////////////////////////////////////
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// controller.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Top level controller module
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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module controller(
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input logic clk, reset,
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// Decode stage control signals
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input logic [6:0] OpD,
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input logic [2:0] Funct3D,
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input logic Funct7b5D,
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output logic [2:0] ImmSrcD,
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input logic StallD, FlushD,
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input logic IllegalCompInstrD,
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// Execute stage control signals
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input logic FlushE,
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input logic [2:0] FlagsE,
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output logic PCSrcE, // for datapath and Hazard Unit
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output logic [4:0] ALUControlE,
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output logic ALUSrcAE, ALUSrcBE,
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output logic TargetSrcE,
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output logic MemReadE, // for Hazard Unit
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// Memory stage control signals
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input logic FlushM,
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output logic [1:0] MemRWM,
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output logic CSRWriteM, PrivilegedM, IllegalInstrFaultM,
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output logic [2:0] Funct3M,
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output logic RegWriteM, // for Hazard Unit
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// Writeback stage control signals
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input logic FlushW,
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output logic RegWriteW, // for datapath and Hazard Unit
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output logic [1:0] ResultSrcW,
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output logic InstrValidW,
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// Stall during CSRs
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output logic CSRWritePendingDEM,
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// Exceptions
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input logic InstrAccessFaultF,
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output logic InstrAccessFaultM);
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// pipelined control signals
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logic RegWriteD, RegWriteE;
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logic [1:0] ResultSrcD, ResultSrcE, ResultSrcM;
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logic [1:0] MemRWD, MemRWE;
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logic JumpD, JumpE;
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logic BranchD, BranchE;
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logic [1:0] ALUOpD;
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logic [4:0] ALUControlD;
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logic ALUSrcAD, ALUSrcBD;
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logic TargetSrcD, W64D;
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logic CSRWriteD, CSRWriteE;
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logic [2:0] Funct3E;
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logic InstrValidE, InstrValidM;
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logic PrivilegedD, PrivilegedE;
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logic InstrAccessFaultD, InstrAccessFaultE;
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logic IllegalInstrFaultD, IllegalInstrMergedD, IllegalInstrFaultE;
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logic [18:0] ControlsD;
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logic PreIllegalInstrFaultD;
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logic aluc3D;
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logic subD, sraD, sltD, sltuD;
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logic BranchTakenE;
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logic zeroE, ltE, ltuE;
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// Decode stage pipeline control register and logic
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flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
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// Main Instruction Decoder
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always_comb
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case(OpD)
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// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_TargetSrc_W64_CSRWrite_Privileged_Illegal
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7'b0000011: ControlsD = 19'b1_000_01_10_01_0_00_0_0_0_0_0_0; // lw
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7'b0100011: ControlsD = 19'b0_001_01_01_00_0_00_0_0_0_0_0_0; // sw
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7'b0110011: ControlsD = 19'b1_000_00_00_00_0_10_0_0_0_0_0_0; // R-type
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7'b0111011: ControlsD = 19'b1_000_00_00_00_0_10_0_0_1_0_0_0; // R-type W instructions for RV64i
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7'b1100011: ControlsD = 19'b0_010_00_00_00_1_01_0_0_0_0_0_0; // beq
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7'b0010011: ControlsD = 19'b1_000_01_00_00_0_10_0_0_0_0_0_0; // I-type ALU
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7'b0011011: ControlsD = 19'b1_000_01_00_00_0_10_0_0_1_0_0_0; // IW-type ALU for RV64i
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7'b1101111: ControlsD = 19'b1_011_00_00_10_0_00_1_0_0_0_0_0; // jal
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7'b1100111: ControlsD = 19'b1_000_00_00_10_0_00_1_1_0_0_0_0; // jalr
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7'b0010111: ControlsD = 19'b1_100_11_00_00_0_00_0_0_0_0_0_0; // auipc
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7'b0110111: ControlsD = 19'b1_100_01_00_00_0_11_0_0_0_0_0_0; // lui
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7'b0001111: ControlsD = 19'b0_000_00_00_00_0_00_0_0_0_0_0_0; // fence = nop
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7'b1110011: if (Funct3D == 3'b000)
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ControlsD = 19'b0_000_00_00_00_0_00_0_0_0_0_1_0; // privileged; decoded further in priveleged modules
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else
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ControlsD = 19'b1_000_00_00_11_0_00_0_0_0_1_0_0; // csrs
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7'b0000000: ControlsD = 19'b0_000_00_00_00_0_00_0_0_0_0_0_1; // illegal instruction
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default: ControlsD = 19'b0_000_00_00_00_0_00_0_0_0_0_0_1; // non-implemented instruction
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endcase
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// unswizzle control bits
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// squash control signals if coming from an illegal compressed instruction
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assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
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ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRWriteD,
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PrivilegedD, PreIllegalInstrFaultD} = ControlsD & ~IllegalCompInstrD;
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assign IllegalInstrFaultD = PreIllegalInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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// ALU Decoding
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assign sltD = (Funct3D == 3'b010);
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7b5D & OpD[5]);
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assign sraD = (Funct3D == 3'b101 & Funct7b5D);
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assign aluc3D = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
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always_comb
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case(ALUOpD)
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2'b00: ALUControlD = 5'b00000; // addition
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2'b01: ALUControlD = 5'b01000; // subtraction
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2'b11: ALUControlD = 5'b01110; // pass B through for lui
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default: ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions
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endcase
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// Execute stage pipeline control register and logic
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floprc #(23) controlregE(clk, reset, FlushE,
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{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRWriteD, PrivilegedD, IllegalInstrFaultD, InstrAccessFaultD, Funct3D, 1'b1},
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{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRWriteE, PrivilegedE, IllegalInstrFaultE, InstrAccessFaultE, Funct3E, InstrValidE});
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// Branch Logic
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assign {zeroE, ltE, ltuE} = FlagsE;
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always_comb
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case(Funct3E)
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3'b000: BranchTakenE = zeroE; // beq
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3'b001: BranchTakenE = ~zeroE; // bne
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3'b100: BranchTakenE = ltE; // blt
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3'b101: BranchTakenE = ~ltE; // bge
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3'b110: BranchTakenE = ltuE; // bltu
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3'b111: BranchTakenE = ~ltuE; // bgeu
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default: BranchTakenE = 1'b0; // undefined mode
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endcase
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assign PCSrcE = JumpE | BranchE & BranchTakenE;
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assign MemReadE = MemRWE[1];
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// Memory stage pipeline control register
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floprc #(13) controlregM(clk, reset, FlushM,
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{RegWriteE, ResultSrcE, MemRWE, CSRWriteE, PrivilegedE, IllegalInstrFaultE, InstrAccessFaultE, Funct3E, InstrValidE},
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{RegWriteM, ResultSrcM, MemRWM, CSRWriteM, PrivilegedM, IllegalInstrFaultM, InstrAccessFaultM, Funct3M, InstrValidM});
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// Writeback stage pipeline control register
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floprc #(4) controlregW(clk, reset, FlushW,
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{RegWriteM, ResultSrcM, InstrValidM},
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{RegWriteW, ResultSrcW, InstrValidW});
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assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
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endmodule
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