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cvw/benchmarks/riscv-coremark
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Ross Thompson 9ddd065340 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
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coremark Coremark updates 2021-11-30 11:16:13 -08:00
old Coremark Diretory cleanup, removed syscall warning about noreturn, rresults are good. 2021-11-19 07:39:15 -08:00
riscv64-baremetal Coremark updates 2021-11-30 11:16:13 -08:00
.gitignore CoreMark cleanup 2021-11-18 20:23:55 -08:00
.gitmodules CoreMark cleanup 2021-11-18 20:23:55 -08:00
LICENSE CoreMark cleanup 2021-11-18 20:23:55 -08:00
Makefile Updated coremark testbench with the extra ports from FPGA merge. 2021-12-08 13:40:32 -06:00