forked from Github_Repos/cvw
137 lines
2.8 KiB
Systemverilog
137 lines
2.8 KiB
Systemverilog
// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular
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// leading zero detector circuit," in Electronics Letters, vol. 29,
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// no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193.
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module lz2 (P, V, B0, B1);
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input logic B0;
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input logic B1;
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output logic P;
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output logic V;
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assign V = B0 | B1;
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assign P = B0 & ~B1;
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endmodule // lz2
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// Note: This module is not made out of two lz2's - why not? (MJS)
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module lz4 (ZP, ZV, B0, B1, V0, V1);
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output logic [1:0] ZP;
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output logic ZV;
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input logic B0;
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input logic B1;
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input logic V0;
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input logic V1;
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assign ZP[0] = V0 ? B0 : B1;
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assign ZP[1] = ~V0;
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assign ZV = V0 | V1;
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endmodule // lz4
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// Note: This module is not made out of two lz4's - why not? (MJS)
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module lz8 (ZP, ZV, B);
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input logic [7:0] B;
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output logic [2:0] ZP;
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output logic ZV;
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logic s1p0;
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logic s1v0;
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logic s1p1;
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logic s1v1;
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logic s2p0;
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logic s2v0;
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logic s2p1;
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logic s2v1;
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logic [1:0] ZPa;
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logic [1:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz2 l1(s1p0, s1v0, B[2], B[3]);
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lz2 l2(s1p1, s1v1, B[0], B[1]);
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lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1);
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lz2 l4(s2p0, s2v0, B[6], B[7]);
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lz2 l5(s2p1, s2v1, B[4], B[5]);
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lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1);
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assign ZP[1:0] = ZVb ? ZPb : ZPa;
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assign ZP[2] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz8
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module lz16 (ZP, ZV, B);
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input logic [15:0] B;
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output logic [3:0] ZP;
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output logic ZV;
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logic [2:0] ZPa;
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logic [2:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz8 l1(ZPa, ZVa, B[7:0]);
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lz8 l2(ZPb, ZVb, B[15:8]);
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assign ZP[2:0] = ZVb ? ZPb : ZPa;
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assign ZP[3] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz16
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module lz32 (ZP, ZV, B);
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input logic [31:0] B;
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output logic [4:0] ZP;
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output logic ZV;
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logic [3:0] ZPa;
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logic [3:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz16 l1(ZPa, ZVa, B[15:0]);
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lz16 l2(ZPb, ZVb, B[31:16]);
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assign ZP[3:0] = ZVb ? ZPb : ZPa;
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assign ZP[4] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz32
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// This module returns the number of leading zeros ZP in the 64-bit
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// number B. If there are no ones in B, then ZP and ZV are both 0.
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module lz64 (ZP, ZV, B);
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input logic [63:0] B;
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output logic [5:0] ZP;
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output logic ZV;
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logic [4:0] ZPa;
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logic [4:0] ZPb;
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logic ZVa;
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logic ZVb;
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lz32 l1(ZPa, ZVa, B[31:0]);
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lz32 l2(ZPb, ZVb, B[63:32]);
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assign ZV = ZVa | ZVb;
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assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}};
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assign ZP[5] = ~ZVb & ZV;
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endmodule // lz64
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